source: rtems/c/src/lib/libcpu/mips/configure.in @ b4d0d18e

4.104.114.84.95
Last change on this file since b4d0d18e was b4d0d18e, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 13, 2000 at 5:52:53 PM

2000-12-13 Joel Sherrill <joel@…>

  • shared/.cvsignore, shared/Makefile.am, shared/cache/.cvsignore, shared/cache/Makefile.am, shared/cache/cache.c, shared/cache/cache_.h, shared/interrupts/.cvsignore, shared/interrupts/Makefile.am, shared/interrupts/installisrentries.c, shared/interrupts/isr_entries.S, shared/interrupts/maxvectors.c, tx39/.cvsignore, tx39/Makefile.am, tx39/include/.cvsignore, tx39/include/Makefile.am, tx39/include/tx3904.h: New file. Moved some pieces of interrupt processing from score/cpu to libcpu/mips since many interrupt servicing characteristics are CPU model dependent. This patch addresses the number of interrupt sources and where the ISR prologues are located. The only way to currently install the ISR prologues requires that the prologues be installed into RAM.
  • Property mode set to 100644
File size: 846 bytes
Line 
1dnl Process this file with autoconf to produce a configure script.
2dnl
3dnl $Id$
4
5AC_PREREQ(2.13)
6AC_INIT(clock)
7RTEMS_TOP(../../../../..)
8AC_CONFIG_AUX_DIR(../../../../..)
9
10RTEMS_CANONICAL_TARGET_CPU
11
12AM_INIT_AUTOMAKE(rtems-c-src-lib-libcpu-mips,$RTEMS_VERSION,no)
13AM_MAINTAINER_MODE
14
15RTEMS_ENABLE_BARE
16RTEMS_ENV_RTEMSBSP
17
18RTEMS_CHECK_CPU
19RTEMS_CANONICAL_HOST
20
21RTEMS_PROJECT_ROOT
22
23RTEMS_PROG_CC_FOR_TARGET
24RTEMS_CANONICALIZE_TOOLS
25
26RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP)
27RTEMS_CHECK_BSP_CACHE(RTEMS_BSP)
28
29AM_CONDITIONAL(r46xx, test "$RTEMS_CPU_MODEL" = "R4600" \
30|| test "$RTEMS_CPU_MODEL" = "R4650" )
31
32AM_CONDITIONAL(tx39, test "$RTEMS_CPU_MODEL" = "tx3904")
33
34# Explicitly list all Makefiles here
35AC_OUTPUT(
36Makefile
37clock/Makefile
38shared/Makefile
39shared/cache/Makefile
40shared/interrupts/Makefile
41tx39/Makefile
42tx39/include/Makefile
43timer/Makefile)
Note: See TracBrowser for help on using the repository browser.