source: rtems/c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c @ bc7bb65

4.104.114.84.95
Last change on this file since bc7bb65 was bc7bb65, checked in by Ralf Corsepius <ralf.corsepius@…>, on 05/10/05 at 07:45:19

2005-05-10 Ralf Corsepius <ralf.corsepius@…>

  • au1x00/vectorisrs/vectorisrs.c: Eliminate unsigned32.
  • Property mode set to 100644
File size: 3.8 KB
RevLine 
[74fb4e1f]1/*
2 *  Au1x00 Interrupt Vectoring
3 *
4 * Copyright (c) 2005 by Cogent Computer Systems
5 * Written by Jay Monkman <jtm@lopingdog.com>
6 *     
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 *  $Id$
13 */
14
15#include <rtems.h>
16#include <stdlib.h>
17#include <libcpu/au1x00.h>
18
19void mips_default_isr( int vector );
[bc7bb65]20static void call_vectored_isr(CPU_Interrupt_frame *, uint32_t , void *);
[74fb4e1f]21
22#define CALL_ISR(_vector,_frame) \
23  do { \
24    if ( _ISR_Vector_table[_vector] ) \
25      (_ISR_Vector_table[_vector])(_vector,_frame); \
26    else \
27      mips_default_isr(_vector); \
28  } while (0)
29
30#include <rtems/bspIo.h>  /* for printk */
31
32void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
33{
34  unsigned int sr;
35  unsigned int cause;
36
37  mips_get_sr( sr );
38  mips_get_cause( cause );
39
40  cause &= (sr & SR_IMASK);
41  cause >>= CAUSE_IPSHIFT;
42
43  /* count/compare interrupt */
44  if ( cause & 0x80 ) {
45      unsigned long zero = 0;
46      /*
47       * I don't see a good way to disable the compare
48       * interrupt, so let's just ignore it.
49       */
50      asm volatile ("mtc0 %0, $11\n" :: "r" (zero));
51
52/*      CALL_ISR( AU1X00_IRQ_CNT, frame );  */
53  }
54
55  /* Performance counter */
56  if ( cause & 0x40 ) {
57      CALL_ISR( AU1X00_IRQ_PERF, frame );
58  }
59 
60  /* Interrupt controller 0 */
61  if ( cause & 0x0c ) {
62      call_vectored_isr(frame, cause, (void *)AU1X00_IC0_ADDR);
63  }
64 
65  /* Interrupt controller 1 */
66  if ( cause & 0x30 ) {
67      call_vectored_isr(frame, cause, (void *)AU1X00_IC1_ADDR);
68  }
69 
70  /* SW[0] */
71  if ( cause & 0x01 )
72      CALL_ISR( AU1X00_IRQ_SW0, frame );
73 
74  /* SW[1] */
75  if ( cause & 0x02 )
76      CALL_ISR( AU1X00_IRQ_SW1, frame );
77}
78
79void mips_default_isr( int vector )
80{
81  unsigned int sr;
82  unsigned int cause;
83
84  mips_get_sr( sr );
85  mips_get_cause( cause );
86
87  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
88      vector, cause, sr );
89  rtems_fatal_error_occurred(1);
90}
91
92static void call_vectored_isr(
93    CPU_Interrupt_frame *frame,
[bc7bb65]94    uint32_t cause,
[74fb4e1f]95    void *ctrlr
96    )
97{
[bc7bb65]98    uint32_t src;
99    uint32_t mask;
[74fb4e1f]100    int index;
101
102    /* get mask register */
103    mask = AU1X00_IC_MASKRD(ctrlr);
104
105    /* check request 0 */
106    src = AU1X00_IC_REQ0INT(ctrlr);
107    src = src & mask;
108    index = 0;
109    while (src) {
110        /* check LSB */
111        if (src & 1) {
112            /* clear rising/falling edge detects */
113            AU1X00_IC_RISINGCLR(ctrlr) = (1 << index);
114            AU1X00_IC_FALLINGCLR(ctrlr) = (1 << index);
115            au_sync();
116            CALL_ISR(AU1X00_IRQ_IC0_BASE + index, frame);
117        }
118        index ++;
119
120        /* shift, and make sure MSB is clear */
121        src = (src >> 1) & 0x7fffffff;
122    }
123
124    /* check request 1 */
125    src = AU1X00_IC_REQ1INT(ctrlr);
126    src = src & mask;
127    index = 0;
128    while (src) {
129        /* check LSB */
130        if (src & 1) {
131            /* clear rising/falling edge detects */
132            AU1X00_IC_RISINGCLR(ctrlr) = (1 << index);
133            AU1X00_IC_FALLINGCLR(ctrlr) = (1 << index);
134            au_sync();
135            CALL_ISR(AU1X00_IRQ_IC0_BASE + index, frame);
136        }
137        index ++;
138
139        /* shift, and make sure MSB is clear */
140        src = (src >> 1) & 0x7fffffff;
141    }
142}
143
144/* Generate a software interrupt */
[bc7bb65]145int assert_sw_irq(uint32_t irqnum)
[74fb4e1f]146{
[bc7bb65]147    uint32_t cause;
[74fb4e1f]148
149    if (irqnum <= 1) {
150        mips_get_cause(cause);
151        cause = cause | ((irqnum + 1) << CAUSE_IPSHIFT);
152        mips_set_cause(cause);
153
154        return irqnum;
155    } else {
156        return -1;
157    }
158}
159
160/* Clear a software interrupt */
[bc7bb65]161int negate_sw_irq(uint32_t irqnum)
[74fb4e1f]162{
[bc7bb65]163    uint32_t cause;
[74fb4e1f]164
165    if (irqnum <= 1) {
166        mips_get_cause(cause);
167        cause = cause & ~((irqnum + 1) << CAUSE_IPSHIFT);
168        mips_set_cause(cause);
169
170        return irqnum;
171    } else {
172        return -1;
173    }
174}
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