[74fb4e1f] | 1 | /* |
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| 2 | * Au1x00 Interrupt Vectoring |
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| 3 | * |
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| 4 | * Copyright (c) 2005 by Cogent Computer Systems |
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| 5 | * Written by Jay Monkman <jtm@lopingdog.com> |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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| 9 | * |
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| 10 | * http://www.OARcorp.com/rtems/license.html. |
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| 11 | * |
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| 12 | * $Id$ |
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| 13 | */ |
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| 14 | |
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| 15 | #include <rtems.h> |
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| 16 | #include <stdlib.h> |
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| 17 | #include <libcpu/au1x00.h> |
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| 18 | |
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| 19 | void mips_default_isr( int vector ); |
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[bc7bb65] | 20 | static void call_vectored_isr(CPU_Interrupt_frame *, uint32_t , void *); |
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[74fb4e1f] | 21 | |
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| 22 | #define CALL_ISR(_vector,_frame) \ |
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| 23 | do { \ |
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| 24 | if ( _ISR_Vector_table[_vector] ) \ |
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| 25 | (_ISR_Vector_table[_vector])(_vector,_frame); \ |
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| 26 | else \ |
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| 27 | mips_default_isr(_vector); \ |
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| 28 | } while (0) |
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| 29 | |
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| 30 | #include <rtems/bspIo.h> /* for printk */ |
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| 31 | |
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| 32 | void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) |
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| 33 | { |
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| 34 | unsigned int sr; |
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| 35 | unsigned int cause; |
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| 36 | |
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| 37 | mips_get_sr( sr ); |
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| 38 | mips_get_cause( cause ); |
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| 39 | |
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| 40 | cause &= (sr & SR_IMASK); |
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| 41 | cause >>= CAUSE_IPSHIFT; |
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| 42 | |
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| 43 | /* count/compare interrupt */ |
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| 44 | if ( cause & 0x80 ) { |
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| 45 | unsigned long zero = 0; |
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| 46 | /* |
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| 47 | * I don't see a good way to disable the compare |
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| 48 | * interrupt, so let's just ignore it. |
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| 49 | */ |
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| 50 | asm volatile ("mtc0 %0, $11\n" :: "r" (zero)); |
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| 51 | |
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| 52 | /* CALL_ISR( AU1X00_IRQ_CNT, frame ); */ |
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| 53 | } |
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| 54 | |
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| 55 | /* Performance counter */ |
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| 56 | if ( cause & 0x40 ) { |
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| 57 | CALL_ISR( AU1X00_IRQ_PERF, frame ); |
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| 58 | } |
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| 59 | |
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| 60 | /* Interrupt controller 0 */ |
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| 61 | if ( cause & 0x0c ) { |
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| 62 | call_vectored_isr(frame, cause, (void *)AU1X00_IC0_ADDR); |
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| 63 | } |
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| 64 | |
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| 65 | /* Interrupt controller 1 */ |
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| 66 | if ( cause & 0x30 ) { |
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| 67 | call_vectored_isr(frame, cause, (void *)AU1X00_IC1_ADDR); |
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| 68 | } |
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| 69 | |
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| 70 | /* SW[0] */ |
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| 71 | if ( cause & 0x01 ) |
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| 72 | CALL_ISR( AU1X00_IRQ_SW0, frame ); |
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| 73 | |
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| 74 | /* SW[1] */ |
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| 75 | if ( cause & 0x02 ) |
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| 76 | CALL_ISR( AU1X00_IRQ_SW1, frame ); |
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| 77 | } |
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| 78 | |
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| 79 | void mips_default_isr( int vector ) |
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| 80 | { |
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| 81 | unsigned int sr; |
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| 82 | unsigned int cause; |
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| 83 | |
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| 84 | mips_get_sr( sr ); |
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| 85 | mips_get_cause( cause ); |
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| 86 | |
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| 87 | printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n", |
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| 88 | vector, cause, sr ); |
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| 89 | rtems_fatal_error_occurred(1); |
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| 90 | } |
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| 91 | |
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| 92 | static void call_vectored_isr( |
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| 93 | CPU_Interrupt_frame *frame, |
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[bc7bb65] | 94 | uint32_t cause, |
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[74fb4e1f] | 95 | void *ctrlr |
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| 96 | ) |
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| 97 | { |
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[bc7bb65] | 98 | uint32_t src; |
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| 99 | uint32_t mask; |
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[74fb4e1f] | 100 | int index; |
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| 101 | |
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| 102 | /* get mask register */ |
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| 103 | mask = AU1X00_IC_MASKRD(ctrlr); |
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| 104 | |
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| 105 | /* check request 0 */ |
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| 106 | src = AU1X00_IC_REQ0INT(ctrlr); |
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| 107 | src = src & mask; |
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| 108 | index = 0; |
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| 109 | while (src) { |
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| 110 | /* check LSB */ |
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| 111 | if (src & 1) { |
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| 112 | /* clear rising/falling edge detects */ |
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| 113 | AU1X00_IC_RISINGCLR(ctrlr) = (1 << index); |
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| 114 | AU1X00_IC_FALLINGCLR(ctrlr) = (1 << index); |
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| 115 | au_sync(); |
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| 116 | CALL_ISR(AU1X00_IRQ_IC0_BASE + index, frame); |
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| 117 | } |
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| 118 | index ++; |
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| 119 | |
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| 120 | /* shift, and make sure MSB is clear */ |
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| 121 | src = (src >> 1) & 0x7fffffff; |
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| 122 | } |
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| 123 | |
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| 124 | /* check request 1 */ |
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| 125 | src = AU1X00_IC_REQ1INT(ctrlr); |
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| 126 | src = src & mask; |
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| 127 | index = 0; |
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| 128 | while (src) { |
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| 129 | /* check LSB */ |
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| 130 | if (src & 1) { |
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| 131 | /* clear rising/falling edge detects */ |
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| 132 | AU1X00_IC_RISINGCLR(ctrlr) = (1 << index); |
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| 133 | AU1X00_IC_FALLINGCLR(ctrlr) = (1 << index); |
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| 134 | au_sync(); |
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| 135 | CALL_ISR(AU1X00_IRQ_IC0_BASE + index, frame); |
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| 136 | } |
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| 137 | index ++; |
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| 138 | |
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| 139 | /* shift, and make sure MSB is clear */ |
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| 140 | src = (src >> 1) & 0x7fffffff; |
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| 141 | } |
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| 142 | } |
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| 143 | |
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| 144 | /* Generate a software interrupt */ |
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[bc7bb65] | 145 | int assert_sw_irq(uint32_t irqnum) |
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[74fb4e1f] | 146 | { |
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[bc7bb65] | 147 | uint32_t cause; |
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[74fb4e1f] | 148 | |
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| 149 | if (irqnum <= 1) { |
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| 150 | mips_get_cause(cause); |
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| 151 | cause = cause | ((irqnum + 1) << CAUSE_IPSHIFT); |
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| 152 | mips_set_cause(cause); |
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| 153 | |
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| 154 | return irqnum; |
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| 155 | } else { |
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| 156 | return -1; |
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| 157 | } |
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| 158 | } |
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| 159 | |
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| 160 | /* Clear a software interrupt */ |
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[bc7bb65] | 161 | int negate_sw_irq(uint32_t irqnum) |
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[74fb4e1f] | 162 | { |
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[bc7bb65] | 163 | uint32_t cause; |
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[74fb4e1f] | 164 | |
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| 165 | if (irqnum <= 1) { |
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| 166 | mips_get_cause(cause); |
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| 167 | cause = cause & ~((irqnum + 1) << CAUSE_IPSHIFT); |
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| 168 | mips_set_cause(cause); |
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| 169 | |
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| 170 | return irqnum; |
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| 171 | } else { |
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| 172 | return -1; |
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| 173 | } |
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| 174 | } |
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