source: rtems/c/src/lib/libcpu/mips/au1x00/include/au1x00.h @ c499856

4.115
Last change on this file since c499856 was c499856, checked in by Chris Johns <chrisj@…>, on 03/20/14 at 21:10:47

Change all references of rtems.com to rtems.org.
  • Property mode set to 100644
File size: 15.7 KB
Line 
1/**
2 *  @file
3 * 
4 *  AMD AU1X00 specific information
5 */
6
7/*
8 *  Copyright (c) 2005 by Cogent Computer Systems
9 *  Written by Jay Monkman <jtm@lopingdog.com>
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.org/license/LICENSE.
14 */
15
16#ifndef __AU1X00_H__
17#define __AU1X00_H__
18
19#define bit(x)         (1 << (x))
20
21/* Au1x00 CP0 registers
22 */
23#define CP0_Index               $0
24#define CP0_Random              $1
25#define CP0_EntryLo0    $2
26#define CP0_EntryLo1    $3
27#define CP0_Context             $4
28#define CP0_PageMask    $5
29#define CP0_Wired               $6
30#define CP0_BadVAddr    $8
31#define CP0_Count               $9
32#define CP0_EntryHi             $10
33#define CP0_Compare             $11
34#define CP0_Status              $12
35#define CP0_Cause               $13
36#define CP0_EPC                 $14
37#define CP0_PRId                $15
38#define CP0_Config              $16
39#define CP0_Config0             $16
40#define CP0_Config1             $16,1
41#define CP0_LLAddr              $17
42#define CP0_WatchLo             $18
43#define CP0_IWatchLo    $18,1
44#define CP0_WatchHi             $19
45#define CP0_IWatchHi    $19,1
46#define CP0_Scratch             $22
47#define CP0_Debug               $23
48#define CP0_DEPC                $24
49#define CP0_PerfCnt             $25
50#define CP0_PerfCtrl    $25,1
51#define CP0_DTag                $28
52#define CP0_DData               $28,1
53#define CP0_ITag                $29
54#define CP0_IData               $29,1
55#define CP0_ErrorEPC    $30
56#define CP0_DESave              $31
57
58/* Addresses common to all AU1x00 CPUs */
59#define AU1X00_MEM_ADDR         0xB4000000
60#define AU1X00_AC97_ADDR        0xB0000000
61#define AU1X00_USBH_ADDR        0xB0100000
62#define AU1X00_USBD_ADDR        0xB0200000
63#define AU1X00_MACDMA0_ADDR     0xB4004000
64#define AU1X00_MACDMA1_ADDR     0xB4004200
65#define AU1X00_UART0_ADDR       0xB1100000
66#define AU1X00_UART3_ADDR       0xB1400000
67#define AU1X00_SYS_ADDR         0xB1900000
68#define AU1X00_GPIO2_ADDR       0xB1700000
69#define AU1X00_IC0_ADDR         0xB0400000
70#define AU1X00_IC1_ADDR         0xB1800000
71
72/* Au1100 base addresses (in KSEG1 region) */
73#define AU1100_MAC0_ADDR        0xB0500000
74#define AU1100_MACEN_ADDR       0xB0520000
75
76/* Au1500 base addresses (in KSEG1 region) */
77#define AU1500_MAC0_ADDR        0xB1500000
78#define AU1500_MAC1_ADDR        0xB1510000
79#define AU1500_MACEN_ADDR       0xB1520000
80#define AU1500_PCI_ADDR         0xB4005000
81
82/* Au1x00 gpio2 register offsets
83 */
84#define gpio2_dir               0x0000
85#define gpio2_output    0x0008
86#define gpio2_pinstate  0x000c
87#define gpio2_inten             0x0010
88#define gpio2_enable    0x0014
89
90/* Au1x00 memory controller register offsets
91 */
92#define mem_sdmode0             0x0000
93#define mem_sdmode1             0x0004
94#define mem_sdmode2             0x0008
95#define mem_sdaddr0             0x000C
96#define mem_sdaddr1             0x0010
97#define mem_sdaddr2             0x0014
98#define mem_sdrefcfg    0x0018
99#define mem_sdprecmd    0x001C
100#define mem_sdautoref   0x0020
101#define mem_sdwrmd0             0x0024
102#define mem_sdwrmd1             0x0028
103#define mem_sdwrmd2             0x002C
104#define mem_sdsleep             0x0030
105#define mem_sdsmcke             0x0034
106
107#define mem_stcfg0              0x1000
108#define mem_sttime0             0x1004
109#define mem_staddr0             0x1008
110#define mem_stcfg1              0x1010
111#define mem_sttime1             0x1014
112#define mem_staddr1             0x1018
113#define mem_stcfg2              0x1020
114#define mem_sttime2             0x1024
115#define mem_staddr2             0x1028
116#define mem_stcfg3              0x1030
117#define mem_sttime3             0x1034
118#define mem_staddr3             0x1038
119
120/*
121 * Au1x00 peripheral register offsets
122 */
123#define ac97_enable             0x0010
124#define usbh_enable             0x0007FFFC
125#define usbd_enable             0x0058
126#define irda_enable             0x0040
127#define macen_mac0              0x0000
128#define macen_mac1              0x0004
129#define i2s_enable              0x0008
130#define uart_enable             0x0100
131#define ssi_enable              0x0100
132
133#define sys_scratch0    0x0018
134#define sys_scratch1    0x001c
135#define sys_cntctrl             0x0014
136#define sys_freqctrl0   0x0020
137#define sys_freqctrl1   0x0024
138#define sys_clksrc              0x0028
139#define sys_pinfunc             0x002C
140#define sys_powerctrl   0x003C
141#define sys_endian              0x0038
142#define sys_wakesrc             0x005C
143#define sys_cpupll              0x0060
144#define sys_auxpll              0x0064
145#define sys_pininputen  0x0110
146
147#define pci_cmem                        0x0000
148#define pci_config                      0x0004
149#define pci_b2bmask_cch         0x0008
150#define pci_b2bbase0_venid      0x000C
151#define pci_b2bbase1_id         0x0010
152#define pci_mwmask_dev          0x0014
153#define pci_mwbase_rev_ccl      0x0018
154#define pci_err_addr            0x001C
155#define pci_spec_intack         0x0020
156#define pci_id                          0x0100
157#define pci_statcmd                     0x0104
158#define pci_classrev            0x0108
159#define pci_hdrtype                     0x010C
160#define pci_mbar                        0x0110
161
162/*
163 * CSB250-specific values
164 */
165
166#define SYS_CPUPLL              33
167#define SYS_POWERCTRL   1
168#define SYS_AUXPLL              8
169#define SYS_CNTCTRL             256
170
171/* RCE0: */
172#define MEM_STCFG0      0x00000203
173#define MEM_STTIME0     0x22080b20
174#define MEM_STADDR0     0x11f03fc0
175
176/* RCE1: */
177#define MEM_STCFG1      0x00000203
178#define MEM_STTIME1     0x22080b20
179#define MEM_STADDR1     0x11e03fc0
180
181/* RCE2: */
182#define MEM_STCFG2      0x00000244
183#define MEM_STTIME2     0x22080a20
184#define MEM_STADDR2     0x11803f00
185
186/* RCE3: */
187#define MEM_STCFG3      0x00000201
188#define MEM_STTIME3     0x22080b20
189#define MEM_STADDR3     0x11003f00
190
191/*
192 * SDCS0 -
193 * SDCS1 -
194 * SDCS2 -
195 */
196#define MEM_SDMODE0             0x00552229
197#define MEM_SDMODE1             0x00552229
198#define MEM_SDMODE2             0x00552229
199
200#define MEM_SDADDR0             0x001003F8
201#define MEM_SDADDR1             0x001023F8
202#define MEM_SDADDR2             0x001043F8
203
204#define MEM_SDREFCFG_D  0x74000c30      /* disable */
205#define MEM_SDREFCFG_E  0x76000c30      /* enable */
206#define MEM_SDWRMD0             0x00000023
207#define MEM_SDWRMD1             0x00000023
208#define MEM_SDWRMD2             0x00000023
209
210#define MEM_1MS                 ((396000000/1000000) * 1000)
211
212#define AU1X00_IC_CFG0RD(x)       (*(volatile uint32_t*)(x + 0x40))
213#define AU1X00_IC_CFG0SET(x)      (*(volatile uint32_t*)(x + 0x40))
214#define AU1X00_IC_CFG0CLR(x)      (*(volatile uint32_t*)(x + 0x44))
215#define AU1X00_IC_CFG1RD(x)       (*(volatile uint32_t*)(x + 0x48))
216#define AU1X00_IC_CFG1SET(x)      (*(volatile uint32_t*)(x + 0x48))
217#define AU1X00_IC_CFG1CLR(x)      (*(volatile uint32_t*)(x + 0x4c))
218#define AU1X00_IC_CFG2RD(x)       (*(volatile uint32_t*)(x + 0x50))
219#define AU1X00_IC_CFG2SET(x)      (*(volatile uint32_t*)(x + 0x50))
220#define AU1X00_IC_CFG2CLR(x)      (*(volatile uint32_t*)(x + 0x54))
221#define AU1X00_IC_REQ0INT(x)      (*(volatile uint32_t*)(x + 0x54))
222#define AU1X00_IC_SRCRD(x)        (*(volatile uint32_t*)(x + 0x58))
223#define AU1X00_IC_SRCSET(x)       (*(volatile uint32_t*)(x + 0x58))
224#define AU1X00_IC_SRCCLR(x)       (*(volatile uint32_t*)(x + 0x5c))
225#define AU1X00_IC_REQ1INT(x)      (*(volatile uint32_t*)(x + 0x5c))
226#define AU1X00_IC_ASSIGNRD(x)     (*(volatile uint32_t*)(x + 0x60))
227#define AU1X00_IC_ASSIGNSET(x)    (*(volatile uint32_t*)(x + 0x60))
228#define AU1X00_IC_ASSIGNCLR(x)    (*(volatile uint32_t*)(x + 0x64))
229#define AU1X00_IC_WAKERD(x)       (*(volatile uint32_t*)(x + 0x68))
230#define AU1X00_IC_WAKESET(x)      (*(volatile uint32_t*)(x + 0x68))
231#define AU1X00_IC_WAKECLR(x)      (*(volatile uint32_t*)(x + 0x6c))
232#define AU1X00_IC_MASKRD(x)       (*(volatile uint32_t*)(x + 0x70))
233#define AU1X00_IC_MASKSET(x)      (*(volatile uint32_t*)(x + 0x70))
234#define AU1X00_IC_MASKCLR(x)      (*(volatile uint32_t*)(x + 0x74))
235#define AU1X00_IC_RISINGRD(x)     (*(volatile uint32_t*)(x + 0x78))
236#define AU1X00_IC_RISINGCLR(x)    (*(volatile uint32_t*)(x + 0x78))
237#define AU1X00_IC_FALLINGRD(x)    (*(volatile uint32_t*)(x + 0x7c))
238#define AU1X00_IC_FALLINGCLR(x)   (*(volatile uint32_t*)(x + 0x7c))
239#define AU1X00_IC_TESTBIT(x)      (*(volatile uint32_t*)(x + 0x80))
240#define AU1X00_IC_IRQ_MAC0        (bit(28))
241#define AU1X00_IC_IRQ_MAC1        (bit(29))
242#define AU1X00_IC_IRQ_TOY_MATCH0  (bit(15))
243#define AU1X00_IC_IRQ_TOY_MATCH1  (bit(16))
244#define AU1X00_IC_IRQ_TOY_MATCH2  (bit(17))
245
246
247
248#define AU1X00_SYS_TOYTRIM(x)    (*(volatile uint32_t*)(x + 0x00))
249#define AU1X00_SYS_TOYWRITE(x)   (*(volatile uint32_t*)(x + 0x04))
250#define AU1X00_SYS_TOYMATCH0(x)  (*(volatile uint32_t*)(x + 0x08))
251#define AU1X00_SYS_TOYMATCH1(x)  (*(volatile uint32_t*)(x + 0x0c))
252#define AU1X00_SYS_TOYMATCH2(x)  (*(volatile uint32_t*)(x + 0x10))
253#define AU1X00_SYS_CNTCTRL(x)    (*(volatile uint32_t*)(x + 0x14))
254#define AU1X00_SYS_SCRATCH0(x)   (*(volatile uint32_t*)(x + 0x18))
255#define AU1X00_SYS_SCRATCH1(x)   (*(volatile uint32_t*)(x + 0x1c))
256#define AU1X00_SYS_WAKEMSK(x)   (*(volatile uint32_t*)(x + 0x34))
257#define AU1X00_SYS_ENDIAN(x)     (*(volatile uint32_t*)(x + 0x38))
258#define AU1X00_SYS_POWERCTRL(x)  (*(volatile uint32_t*)(x + 0x3c))
259#define AU1X00_SYS_TOYREAD(x)    (*(volatile uint32_t*)(x + 0x40))
260#define AU1X00_SYS_RTCTRIM(x)    (*(volatile uint32_t*)(x + 0x44))
261#define AU1X00_SYS_RTCWRITE(x)   (*(volatile uint32_t*)(x + 0x48))
262#define AU1X00_SYS_RTCMATCH0(x)  (*(volatile uint32_t*)(x + 0x4c))
263#define AU1X00_SYS_RTCMATCH1(x)  (*(volatile uint32_t*)(x + 0x50))
264#define AU1X00_SYS_RTCMATCH2(x)  (*(volatile uint32_t*)(x + 0x54))
265#define AU1X00_SYS_RTCREAD(x)    (*(volatile uint32_t*)(x + 0x58))
266#define AU1X00_SYS_WAKESRC(x)    (*(volatile uint32_t*)(x + 0x5c))
267#define AU1X00_SYS_SLPPWR(x)     (*(volatile uint32_t*)(x + 0x78))
268#define AU1X00_SYS_SLEEP(x)      (*(volatile uint32_t*)(x + 0x7c))
269
270#define AU1X00_SYS_CNTCTRL_ERS   (bit(23))
271#define AU1X00_SYS_CNTCTRL_RTS   (bit(20))
272#define AU1X00_SYS_CNTCTRL_RM2   (bit(19))
273#define AU1X00_SYS_CNTCTRL_RM1   (bit(18))
274#define AU1X00_SYS_CNTCTRL_RM0   (bit(17))
275#define AU1X00_SYS_CNTCTRL_RS    (bit(16))
276#define AU1X00_SYS_CNTCTRL_BP    (bit(14))
277#define AU1X00_SYS_CNTCTRL_REN   (bit(13))
278#define AU1X00_SYS_CNTCTRL_BRT   (bit(12))
279#define AU1X00_SYS_CNTCTRL_TEN   (bit(11))
280#define AU1X00_SYS_CNTCTRL_BTT   (bit(10))
281#define AU1X00_SYS_CNTCTRL_E0    (bit(8))
282#define AU1X00_SYS_CNTCTRL_ETS   (bit(7))
283#define AU1X00_SYS_CNTCTRL_32S   (bit(5))
284#define AU1X00_SYS_CNTCTRL_TTS   (bit(4))
285#define AU1X00_SYS_CNTCTRL_TM2   (bit(3))
286#define AU1X00_SYS_CNTCTRL_TM1   (bit(2))
287#define AU1X00_SYS_CNTCTRL_TM0   (bit(1))
288#define AU1X00_SYS_CNTCTRL_TS    (bit(0))
289#define AU1X00_SYS_WAKEMSK_M20   (bit(8))
290
291#define AU1X00_MAC_CONTROL(x)         (*(volatile uint32_t*)(x + 0x00))
292#define AU1X00_MAC_ADDRHIGH(x)        (*(volatile uint32_t*)(x + 0x04))
293#define AU1X00_MAC_ADDRLOW(x)         (*(volatile uint32_t*)(x + 0x08))
294#define AU1X00_MAC_HASHHIGH(x)        (*(volatile uint32_t*)(x + 0x0c))
295#define AU1X00_MAC_HASHLOW(x)         (*(volatile uint32_t*)(x + 0x10))
296#define AU1X00_MAC_MIICTRL(x)         (*(volatile uint32_t*)(x + 0x14))
297#define AU1X00_MAC_MIIDATA(x)         (*(volatile uint32_t*)(x + 0x18))
298#define AU1X00_MAC_FLOWCTRL(x)        (*(volatile uint32_t*)(x + 0x1c))
299#define AU1X00_MAC_VLAN1(x)           (*(volatile uint32_t*)(x + 0x20))
300#define AU1X00_MAC_VLAN2(x)           (*(volatile uint32_t*)(x + 0x24))
301#define AU1X00_MAC_EN0                (*(volatile uint32_t*)(AU1X00_MACEN_ADDR + 0x0))
302#define AU1X00_MAC_EN1                (*(volatile uint32_t*)(AU1X00_MACEN_ADDR + 0x4))
303#define AU1X00_MAC_DMA_TX0_ADDR(x)    (*(volatile uint32_t*)(x + 0x000))
304#define AU1X00_MAC_DMA_TX1_ADDR(x)    (*(volatile uint32_t*)(x + 0x010))
305#define AU1X00_MAC_DMA_TX2_ADDR(x)    (*(volatile uint32_t*)(x + 0x020))
306#define AU1X00_MAC_DMA_TX3_ADDR(x)    (*(volatile uint32_t*)(x + 0x030))
307#define AU1X00_MAC_DMA_RX0_ADDR(x)    (*(volatile uint32_t*)(x + 0x100))
308#define AU1X00_MAC_DMA_RX1_ADDR(x)    (*(volatile uint32_t*)(x + 0x110))
309#define AU1X00_MAC_DMA_RX2_ADDR(x)    (*(volatile uint32_t*)(x + 0x120))
310#define AU1X00_MAC_DMA_RX3_ADDR(x)    (*(volatile uint32_t*)(x + 0x130))
311
312typedef struct {
313    volatile uint32_t stat;
314    volatile uint32_t addr;
315    uint32_t _rsv0;
316    uint32_t _rsv1;
317} au1x00_macdma_rx_t;
318
319
320typedef struct {
321    volatile uint32_t stat;
322    volatile uint32_t addr;
323    volatile uint32_t len;
324    uint32_t _rsv0;
325} au1x00_macdma_tx_t;
326
327#define AU1X00_MAC_CTRL_RA                (bit(31))
328#define AU1X00_MAC_CTRL_EM                (bit(30))
329#define AU1X00_MAC_CTRL_DO                (bit(23))
330#define AU1X00_MAC_CTRL_LM(x)             ((x) << 21)
331#define AU1X00_MAC_CTRL_LM_NORMAL         ((0) << 21)
332#define AU1X00_MAC_CTRL_LM_INTERNAL       ((1) << 21)
333#define AU1X00_MAC_CTRL_LM_EXTERNAL       ((2) << 21)
334#define AU1X00_MAC_CTRL_F                 (bit(20))
335#define AU1X00_MAC_CTRL_PM                (bit(19))
336#define AU1X00_MAC_CTRL_PR                (bit(18))
337#define AU1X00_MAC_CTRL_IF                (bit(17))
338#define AU1X00_MAC_CTRL_PB                (bit(16))
339#define AU1X00_MAC_CTRL_HO                (bit(15))
340#define AU1X00_MAC_CTRL_HP                (bit(13))
341#define AU1X00_MAC_CTRL_LC                (bit(12))
342#define AU1X00_MAC_CTRL_DB                (bit(11))
343#define AU1X00_MAC_CTRL_DR                (bit(10))
344#define AU1X00_MAC_CTRL_AP                (bit(8))
345#define AU1X00_MAC_CTRL_BL(x)             ((x) << 6)
346#define AU1X00_MAC_CTRL_DC                (bit(5))
347#define AU1X00_MAC_CTRL_TE                (bit(3))
348#define AU1X00_MAC_CTRL_RE                (bit(2))
349
350#define AU1X00_MAC_EN_JP                  (bit(6))
351#define AU1X00_MAC_EN_E2                  (bit(5))
352#define AU1X00_MAC_EN_E1                  (bit(4))
353#define AU1X00_MAC_EN_C                   (bit(3))
354#define AU1X00_MAC_EN_TS                  (bit(2))
355#define AU1X00_MAC_EN_E0                  (bit(1))
356#define AU1X00_MAC_EN_CE                  (bit(0))
357
358#define AU1X00_MAC_ADDRHIGH_MASK          (0xffff)_
359#define AU1X00_MAC_MIICTRL_PHYADDR(x)     ((x & 0x1f) << 11)
360#define AU1X00_MAC_MIICTRL_MIIREG(x)      ((x & 0x1f) << 6)
361#define AU1X00_MAC_MIICTRL_MW             (bit(1))
362#define AU1X00_MAC_MIICTRL_MB             (bit(0))
363#define AU1X00_MAC_MIIDATA_MASK           (0xffff)
364#define AU1X00_MAC_FLOWCTRL_PT(x)         (((x) & 0xffff) << 16)
365#define AU1X00_MAC_FLOWCTRL_PC            (bit(2))
366#define AU1X00_MAC_FLOWCTRL_FE            (bit(1))
367#define AU1X00_MAC_FLOWCTRL_FB            (bit(0))
368
369#define AU1X00_MAC_DMA_RXSTAT_MI          (bit(31))
370#define AU1X00_MAC_DMA_RXSTAT_PF          (bit(30))
371#define AU1X00_MAC_DMA_RXSTAT_FF          (bit(29))
372#define AU1X00_MAC_DMA_RXSTAT_BF          (bit(28))
373#define AU1X00_MAC_DMA_RXSTAT_MF          (bit(27))
374#define AU1X00_MAC_DMA_RXSTAT_UC          (bit(26))
375#define AU1X00_MAC_DMA_RXSTAT_CF          (bit(25))
376#define AU1X00_MAC_DMA_RXSTAT_LE          (bit(24))
377#define AU1X00_MAC_DMA_RXSTAT_V2          (bit(23))
378#define AU1X00_MAC_DMA_RXSTAT_V1          (bit(22))
379#define AU1X00_MAC_DMA_RXSTAT_CR          (bit(21))
380#define AU1X00_MAC_DMA_RXSTAT_DB          (bit(20))
381#define AU1X00_MAC_DMA_RXSTAT_ME          (bit(19))
382#define AU1X00_MAC_DMA_RXSTAT_FT          (bit(18))
383#define AU1X00_MAC_DMA_RXSTAT_CS          (bit(17))
384#define AU1X00_MAC_DMA_RXSTAT_FL          (bit(16))
385#define AU1X00_MAC_DMA_RXSTAT_RF          (bit(15))
386#define AU1X00_MAC_DMA_RXSTAT_WT          (bit(14))
387#define AU1X00_MAC_DMA_RXSTAT_LEN(x)      ((x) & 0x3fff)
388#define AU1X00_MAC_DMA_RXADDR_ADDR(x)     ((x) & ~0x1f)
389#define AU1X00_MAC_DMA_RXADDR_CB_MASK     (0x3 << 0x2)
390#define AU1X00_MAC_DMA_RXADDR_DN          (bit(1))
391#define AU1X00_MAC_DMA_RXADDR_EN          (bit(0))
392
393
394#define AU1X00_MAC_DMA_TXSTAT_PR          (bit(31))
395#define AU1X00_MAC_DMA_TXSTAT_CC_MASK     (0xf << 10)
396#define AU1X00_MAC_DMA_TXSTAT_LO          (bit(9))
397#define AU1X00_MAC_DMA_TXSTAT_DF          (bit(8))
398#define AU1X00_MAC_DMA_TXSTAT_UR          (bit(7))
399#define AU1X00_MAC_DMA_TXSTAT_EC          (bit(6))
400#define AU1X00_MAC_DMA_TXSTAT_LC          (bit(5))
401#define AU1X00_MAC_DMA_TXSTAT_ED          (bit(4))
402#define AU1X00_MAC_DMA_TXSTAT_LS          (bit(3))
403#define AU1X00_MAC_DMA_TXSTAT_NC          (bit(2))
404#define AU1X00_MAC_DMA_TXSTAT_JT          (bit(1))
405#define AU1X00_MAC_DMA_TXSTAT_FA          (bit(0))
406#define AU1X00_MAC_DMA_TXADDR_ADDR(x)     ((x) & ~0x1f)
407#define AU1X00_MAC_DMA_TXADDR_CB_MASK     (0x3 << 0x2)
408#define AU1X00_MAC_DMA_TXADDR_DN          (bit(1))
409#define AU1X00_MAC_DMA_TXADDR_EN          (bit(0))
410
411
412
413typedef struct {
414    volatile uint32_t rxdata;
415    volatile uint32_t txdata;
416    volatile uint32_t inten;
417    volatile uint32_t intcause;
418    volatile uint32_t fifoctrl;
419    volatile uint32_t linectrl;
420    volatile uint32_t mdmctrl;
421    volatile uint32_t linestat;
422    volatile uint32_t mdmstat;
423    volatile uint32_t clkdiv;
424    volatile uint32_t _resv[54];
425    volatile uint32_t enable;
426} au1x00_uart_t;
427
428extern au1x00_uart_t *uart0;
429extern au1x00_uart_t *uart3;
430
431void static inline au_sync(void)
432{
433        __asm__ volatile ("sync");
434}
435
436
437extern void mips_default_isr( int vector );
438
439/* Generate a software interrupt */
440extern int assert_sw_irq(uint32_t irqnum);
441
442/* Clear a software interrupt */
443extern int negate_sw_irq(uint32_t irqnum);
444
445#endif
Note: See TracBrowser for help on using the repository browser.