1 | /* |
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2 | * AMD AU1X00 specific information |
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3 | * |
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4 | * Copyright (c) 2005 by Cogent Computer Systems |
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5 | * Written by Jay Monkman <jtm@lopingdog.com> |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * |
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10 | * http://www.OARcorp.com/rtems/license.html. |
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11 | * |
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12 | * $Id$ |
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13 | * |
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14 | */ |
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15 | |
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16 | #ifndef __AU1X00_H__ |
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17 | #define __AU1X00_H__ |
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18 | |
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19 | #define bit(x) (1 << (x)) |
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20 | |
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21 | /* Au1x00 CP0 registers |
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22 | */ |
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23 | #define CP0_Index $0 |
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24 | #define CP0_Random $1 |
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25 | #define CP0_EntryLo0 $2 |
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26 | #define CP0_EntryLo1 $3 |
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27 | #define CP0_Context $4 |
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28 | #define CP0_PageMask $5 |
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29 | #define CP0_Wired $6 |
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30 | #define CP0_BadVAddr $8 |
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31 | #define CP0_Count $9 |
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32 | #define CP0_EntryHi $10 |
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33 | #define CP0_Compare $11 |
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34 | #define CP0_Status $12 |
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35 | #define CP0_Cause $13 |
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36 | #define CP0_EPC $14 |
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37 | #define CP0_PRId $15 |
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38 | #define CP0_Config $16 |
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39 | #define CP0_Config0 $16 |
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40 | #define CP0_Config1 $16,1 |
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41 | #define CP0_LLAddr $17 |
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42 | #define CP0_WatchLo $18 |
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43 | #define CP0_IWatchLo $18,1 |
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44 | #define CP0_WatchHi $19 |
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45 | #define CP0_IWatchHi $19,1 |
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46 | #define CP0_Scratch $22 |
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47 | #define CP0_Debug $23 |
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48 | #define CP0_DEPC $24 |
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49 | #define CP0_PerfCnt $25 |
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50 | #define CP0_PerfCtrl $25,1 |
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51 | #define CP0_DTag $28 |
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52 | #define CP0_DData $28,1 |
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53 | #define CP0_ITag $29 |
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54 | #define CP0_IData $29,1 |
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55 | #define CP0_ErrorEPC $30 |
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56 | #define CP0_DESave $31 |
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57 | |
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58 | /* Addresses common to all AU1x00 CPUs */ |
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59 | #define AU1X00_MEM_ADDR 0xB4000000 |
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60 | #define AU1X00_AC97_ADDR 0xB0000000 |
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61 | #define AU1X00_USBH_ADDR 0xB0100000 |
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62 | #define AU1X00_USBD_ADDR 0xB0200000 |
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63 | #define AU1X00_MACDMA0_ADDR 0xB4004000 |
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64 | #define AU1X00_MACDMA1_ADDR 0xB4004200 |
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65 | #define AU1X00_UART0_ADDR 0xB1100000 |
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66 | #define AU1X00_UART3_ADDR 0xB1400000 |
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67 | #define AU1X00_SYS_ADDR 0xB1900000 |
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68 | #define AU1X00_GPIO2_ADDR 0xB1700000 |
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69 | #define AU1X00_IC0_ADDR 0xB0400000 |
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70 | #define AU1X00_IC1_ADDR 0xB1800000 |
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71 | |
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72 | /* Au1100 base addresses (in KSEG1 region) */ |
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73 | #define AU1100_MAC0_ADDR 0xB0500000 |
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74 | #define AU1100_MACEN_ADDR 0xB0520000 |
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75 | |
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76 | /* Au1500 base addresses (in KSEG1 region) */ |
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77 | #define AU1500_MAC0_ADDR 0xB1500000 |
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78 | #define AU1500_MAC1_ADDR 0xB1510000 |
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79 | #define AU1500_MACEN_ADDR 0xB1520000 |
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80 | #define AU1500_PCI_ADDR 0xB4005000 |
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81 | |
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82 | /* Au1x00 gpio2 register offsets |
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83 | */ |
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84 | #define gpio2_dir 0x0000 |
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85 | #define gpio2_output 0x0008 |
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86 | #define gpio2_pinstate 0x000c |
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87 | #define gpio2_inten 0x0010 |
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88 | #define gpio2_enable 0x0014 |
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89 | |
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90 | /* Au1x00 memory controller register offsets |
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91 | */ |
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92 | #define mem_sdmode0 0x0000 |
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93 | #define mem_sdmode1 0x0004 |
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94 | #define mem_sdmode2 0x0008 |
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95 | #define mem_sdaddr0 0x000C |
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96 | #define mem_sdaddr1 0x0010 |
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97 | #define mem_sdaddr2 0x0014 |
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98 | #define mem_sdrefcfg 0x0018 |
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99 | #define mem_sdprecmd 0x001C |
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100 | #define mem_sdautoref 0x0020 |
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101 | #define mem_sdwrmd0 0x0024 |
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102 | #define mem_sdwrmd1 0x0028 |
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103 | #define mem_sdwrmd2 0x002C |
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104 | #define mem_sdsleep 0x0030 |
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105 | #define mem_sdsmcke 0x0034 |
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106 | |
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107 | #define mem_stcfg0 0x1000 |
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108 | #define mem_sttime0 0x1004 |
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109 | #define mem_staddr0 0x1008 |
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110 | #define mem_stcfg1 0x1010 |
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111 | #define mem_sttime1 0x1014 |
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112 | #define mem_staddr1 0x1018 |
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113 | #define mem_stcfg2 0x1020 |
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114 | #define mem_sttime2 0x1024 |
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115 | #define mem_staddr2 0x1028 |
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116 | #define mem_stcfg3 0x1030 |
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117 | #define mem_sttime3 0x1034 |
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118 | #define mem_staddr3 0x1038 |
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119 | |
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120 | /* |
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121 | * Au1x00 peripheral register offsets |
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122 | */ |
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123 | #define ac97_enable 0x0010 |
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124 | #define usbh_enable 0x0007FFFC |
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125 | #define usbd_enable 0x0058 |
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126 | #define irda_enable 0x0040 |
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127 | #define macen_mac0 0x0000 |
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128 | #define macen_mac1 0x0004 |
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129 | #define i2s_enable 0x0008 |
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130 | #define uart_enable 0x0100 |
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131 | #define ssi_enable 0x0100 |
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132 | |
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133 | #define sys_scratch0 0x0018 |
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134 | #define sys_scratch1 0x001c |
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135 | #define sys_cntctrl 0x0014 |
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136 | #define sys_freqctrl0 0x0020 |
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137 | #define sys_freqctrl1 0x0024 |
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138 | #define sys_clksrc 0x0028 |
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139 | #define sys_pinfunc 0x002C |
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140 | #define sys_powerctrl 0x003C |
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141 | #define sys_endian 0x0038 |
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142 | #define sys_wakesrc 0x005C |
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143 | #define sys_cpupll 0x0060 |
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144 | #define sys_auxpll 0x0064 |
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145 | #define sys_pininputen 0x0110 |
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146 | |
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147 | #define pci_cmem 0x0000 |
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148 | #define pci_config 0x0004 |
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149 | #define pci_b2bmask_cch 0x0008 |
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150 | #define pci_b2bbase0_venid 0x000C |
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151 | #define pci_b2bbase1_id 0x0010 |
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152 | #define pci_mwmask_dev 0x0014 |
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153 | #define pci_mwbase_rev_ccl 0x0018 |
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154 | #define pci_err_addr 0x001C |
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155 | #define pci_spec_intack 0x0020 |
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156 | #define pci_id 0x0100 |
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157 | #define pci_statcmd 0x0104 |
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158 | #define pci_classrev 0x0108 |
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159 | #define pci_hdrtype 0x010C |
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160 | #define pci_mbar 0x0110 |
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161 | |
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162 | /* |
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163 | * CSB250-specific values |
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164 | */ |
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165 | |
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166 | #define SYS_CPUPLL 33 |
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167 | #define SYS_POWERCTRL 1 |
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168 | #define SYS_AUXPLL 8 |
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169 | #define SYS_CNTCTRL 256 |
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170 | |
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171 | /* RCE0: */ |
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172 | #define MEM_STCFG0 0x00000203 |
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173 | #define MEM_STTIME0 0x22080b20 |
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174 | #define MEM_STADDR0 0x11f03fc0 |
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175 | |
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176 | /* RCE1: */ |
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177 | #define MEM_STCFG1 0x00000203 |
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178 | #define MEM_STTIME1 0x22080b20 |
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179 | #define MEM_STADDR1 0x11e03fc0 |
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180 | |
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181 | /* RCE2: */ |
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182 | #define MEM_STCFG2 0x00000244 |
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183 | #define MEM_STTIME2 0x22080a20 |
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184 | #define MEM_STADDR2 0x11803f00 |
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185 | |
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186 | /* RCE3: */ |
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187 | #define MEM_STCFG3 0x00000201 |
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188 | #define MEM_STTIME3 0x22080b20 |
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189 | #define MEM_STADDR3 0x11003f00 |
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190 | |
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191 | /* |
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192 | * SDCS0 - |
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193 | * SDCS1 - |
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194 | * SDCS2 - |
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195 | */ |
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196 | #define MEM_SDMODE0 0x00552229 |
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197 | #define MEM_SDMODE1 0x00552229 |
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198 | #define MEM_SDMODE2 0x00552229 |
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199 | |
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200 | #define MEM_SDADDR0 0x001003F8 |
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201 | #define MEM_SDADDR1 0x001023F8 |
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202 | #define MEM_SDADDR2 0x001043F8 |
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203 | |
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204 | #define MEM_SDREFCFG_D 0x74000c30 /* disable */ |
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205 | #define MEM_SDREFCFG_E 0x76000c30 /* enable */ |
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206 | #define MEM_SDWRMD0 0x00000023 |
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207 | #define MEM_SDWRMD1 0x00000023 |
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208 | #define MEM_SDWRMD2 0x00000023 |
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209 | |
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210 | #define MEM_1MS ((396000000/1000000) * 1000) |
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211 | |
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212 | #define AU1X00_IC_CFG0RD(x) (*(volatile unsigned32*)(x + 0x40)) |
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213 | #define AU1X00_IC_CFG0SET(x) (*(volatile unsigned32*)(x + 0x40)) |
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214 | #define AU1X00_IC_CFG0CLR(x) (*(volatile unsigned32*)(x + 0x44)) |
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215 | #define AU1X00_IC_CFG1RD(x) (*(volatile unsigned32*)(x + 0x48)) |
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216 | #define AU1X00_IC_CFG1SET(x) (*(volatile unsigned32*)(x + 0x48)) |
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217 | #define AU1X00_IC_CFG1CLR(x) (*(volatile unsigned32*)(x + 0x4c)) |
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218 | #define AU1X00_IC_CFG2RD(x) (*(volatile unsigned32*)(x + 0x50)) |
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219 | #define AU1X00_IC_CFG2SET(x) (*(volatile unsigned32*)(x + 0x50)) |
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220 | #define AU1X00_IC_CFG2CLR(x) (*(volatile unsigned32*)(x + 0x54)) |
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221 | #define AU1X00_IC_REQ0INT(x) (*(volatile unsigned32*)(x + 0x54)) |
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222 | #define AU1X00_IC_SRCRD(x) (*(volatile unsigned32*)(x + 0x58)) |
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223 | #define AU1X00_IC_SRCSET(x) (*(volatile unsigned32*)(x + 0x58)) |
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224 | #define AU1X00_IC_SRCCLR(x) (*(volatile unsigned32*)(x + 0x5c)) |
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225 | #define AU1X00_IC_REQ1INT(x) (*(volatile unsigned32*)(x + 0x5c)) |
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226 | #define AU1X00_IC_ASSIGNRD(x) (*(volatile unsigned32*)(x + 0x60)) |
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227 | #define AU1X00_IC_ASSIGNSET(x) (*(volatile unsigned32*)(x + 0x60)) |
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228 | #define AU1X00_IC_ASSIGNCLR(x) (*(volatile unsigned32*)(x + 0x64)) |
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229 | #define AU1X00_IC_WAKERD(x) (*(volatile unsigned32*)(x + 0x68)) |
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230 | #define AU1X00_IC_WAKESET(x) (*(volatile unsigned32*)(x + 0x68)) |
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231 | #define AU1X00_IC_WAKECLR(x) (*(volatile unsigned32*)(x + 0x6c)) |
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232 | #define AU1X00_IC_MASKRD(x) (*(volatile unsigned32*)(x + 0x70)) |
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233 | #define AU1X00_IC_MASKSET(x) (*(volatile unsigned32*)(x + 0x70)) |
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234 | #define AU1X00_IC_MASKCLR(x) (*(volatile unsigned32*)(x + 0x74)) |
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235 | #define AU1X00_IC_RISINGRD(x) (*(volatile unsigned32*)(x + 0x78)) |
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236 | #define AU1X00_IC_RISINGCLR(x) (*(volatile unsigned32*)(x + 0x78)) |
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237 | #define AU1X00_IC_FALLINGRD(x) (*(volatile unsigned32*)(x + 0x7c)) |
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238 | #define AU1X00_IC_FALLINGCLR(x) (*(volatile unsigned32*)(x + 0x7c)) |
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239 | #define AU1X00_IC_TESTBIT(x) (*(volatile unsigned32*)(x + 0x80)) |
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240 | #define AU1X00_IC_IRQ_MAC0 (bit(28)) |
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241 | #define AU1X00_IC_IRQ_MAC1 (bit(29)) |
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242 | #define AU1X00_IC_IRQ_TOY_MATCH0 (bit(15)) |
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243 | #define AU1X00_IC_IRQ_TOY_MATCH1 (bit(16)) |
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244 | #define AU1X00_IC_IRQ_TOY_MATCH2 (bit(17)) |
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245 | |
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246 | |
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247 | |
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248 | #define AU1X00_SYS_TOYTRIM(x) (*(volatile unsigned32*)(x + 0x00)) |
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249 | #define AU1X00_SYS_TOYWRITE(x) (*(volatile unsigned32*)(x + 0x04)) |
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250 | #define AU1X00_SYS_TOYMATCH0(x) (*(volatile unsigned32*)(x + 0x08)) |
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251 | #define AU1X00_SYS_TOYMATCH1(x) (*(volatile unsigned32*)(x + 0x0c)) |
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252 | #define AU1X00_SYS_TOYMATCH2(x) (*(volatile unsigned32*)(x + 0x10)) |
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253 | #define AU1X00_SYS_CNTCTRL(x) (*(volatile unsigned32*)(x + 0x14)) |
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254 | #define AU1X00_SYS_SCRATCH0(x) (*(volatile unsigned32*)(x + 0x18)) |
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255 | #define AU1X00_SYS_SCRATCH1(x) (*(volatile unsigned32*)(x + 0x1c)) |
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256 | #define AU1X00_SYS_WAKEMSK(x) (*(volatile unsigned32*)(x + 0x34)) |
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257 | #define AU1X00_SYS_ENDIAN(x) (*(volatile unsigned32*)(x + 0x38)) |
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258 | #define AU1X00_SYS_POWERCTRL(x) (*(volatile unsigned32*)(x + 0x3c)) |
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259 | #define AU1X00_SYS_TOYREAD(x) (*(volatile unsigned32*)(x + 0x40)) |
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260 | #define AU1X00_SYS_RTCTRIM(x) (*(volatile unsigned32*)(x + 0x44)) |
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261 | #define AU1X00_SYS_RTCWRITE(x) (*(volatile unsigned32*)(x + 0x48)) |
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262 | #define AU1X00_SYS_RTCMATCH0(x) (*(volatile unsigned32*)(x + 0x4c)) |
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263 | #define AU1X00_SYS_RTCMATCH1(x) (*(volatile unsigned32*)(x + 0x50)) |
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264 | #define AU1X00_SYS_RTCMATCH2(x) (*(volatile unsigned32*)(x + 0x54)) |
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265 | #define AU1X00_SYS_RTCREAD(x) (*(volatile unsigned32*)(x + 0x58)) |
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266 | #define AU1X00_SYS_WAKESRC(x) (*(volatile unsigned32*)(x + 0x5c)) |
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267 | #define AU1X00_SYS_SLPPWR(x) (*(volatile unsigned32*)(x + 0x78)) |
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268 | #define AU1X00_SYS_SLEEP(x) (*(volatile unsigned32*)(x + 0x7c)) |
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269 | |
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270 | #define AU1X00_SYS_CNTCTRL_ERS (bit(23)) |
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271 | #define AU1X00_SYS_CNTCTRL_RTS (bit(20)) |
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272 | #define AU1X00_SYS_CNTCTRL_RM2 (bit(19)) |
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273 | #define AU1X00_SYS_CNTCTRL_RM1 (bit(18)) |
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274 | #define AU1X00_SYS_CNTCTRL_RM0 (bit(17)) |
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275 | #define AU1X00_SYS_CNTCTRL_RS (bit(16)) |
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276 | #define AU1X00_SYS_CNTCTRL_BP (bit(14)) |
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277 | #define AU1X00_SYS_CNTCTRL_REN (bit(13)) |
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278 | #define AU1X00_SYS_CNTCTRL_BRT (bit(12)) |
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279 | #define AU1X00_SYS_CNTCTRL_TEN (bit(11)) |
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280 | #define AU1X00_SYS_CNTCTRL_BTT (bit(10)) |
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281 | #define AU1X00_SYS_CNTCTRL_E0 (bit(8)) |
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282 | #define AU1X00_SYS_CNTCTRL_ETS (bit(7)) |
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283 | #define AU1X00_SYS_CNTCTRL_32S (bit(5)) |
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284 | #define AU1X00_SYS_CNTCTRL_TTS (bit(4)) |
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285 | #define AU1X00_SYS_CNTCTRL_TM2 (bit(3)) |
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286 | #define AU1X00_SYS_CNTCTRL_TM1 (bit(2)) |
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287 | #define AU1X00_SYS_CNTCTRL_TM0 (bit(1)) |
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288 | #define AU1X00_SYS_CNTCTRL_TS (bit(0)) |
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289 | #define AU1X00_SYS_WAKEMSK_M20 (bit(8)) |
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290 | |
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291 | #define AU1X00_MAC_CONTROL(x) (*(volatile unsigned32*)(x + 0x00)) |
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292 | #define AU1X00_MAC_ADDRHIGH(x) (*(volatile unsigned32*)(x + 0x04)) |
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293 | #define AU1X00_MAC_ADDRLOW(x) (*(volatile unsigned32*)(x + 0x08)) |
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294 | #define AU1X00_MAC_HASHHIGH(x) (*(volatile unsigned32*)(x + 0x0c)) |
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295 | #define AU1X00_MAC_HASHLOW(x) (*(volatile unsigned32*)(x + 0x10)) |
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296 | #define AU1X00_MAC_MIICTRL(x) (*(volatile unsigned32*)(x + 0x14)) |
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297 | #define AU1X00_MAC_MIIDATA(x) (*(volatile unsigned32*)(x + 0x18)) |
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298 | #define AU1X00_MAC_FLOWCTRL(x) (*(volatile unsigned32*)(x + 0x1c)) |
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299 | #define AU1X00_MAC_VLAN1(x) (*(volatile unsigned32*)(x + 0x20)) |
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300 | #define AU1X00_MAC_VLAN2(x) (*(volatile unsigned32*)(x + 0x24)) |
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301 | #define AU1X00_MAC_EN0 (*(volatile unsigned32*)(AU1X00_MACEN_ADDR + 0x0)) |
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302 | #define AU1X00_MAC_EN1 (*(volatile unsigned32*)(AU1X00_MACEN_ADDR + 0x4)) |
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303 | #define AU1X00_MAC_DMA_TX0_ADDR(x) (*(volatile unsigned32*)(x + 0x000)) |
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304 | #define AU1X00_MAC_DMA_TX1_ADDR(x) (*(volatile unsigned32*)(x + 0x010)) |
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305 | #define AU1X00_MAC_DMA_TX2_ADDR(x) (*(volatile unsigned32*)(x + 0x020)) |
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306 | #define AU1X00_MAC_DMA_TX3_ADDR(x) (*(volatile unsigned32*)(x + 0x030)) |
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307 | #define AU1X00_MAC_DMA_RX0_ADDR(x) (*(volatile unsigned32*)(x + 0x100)) |
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308 | #define AU1X00_MAC_DMA_RX0_ADDR(x) (*(volatile unsigned32*)(x + 0x110)) |
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309 | #define AU1X00_MAC_DMA_RX0_ADDR(x) (*(volatile unsigned32*)(x + 0x120)) |
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310 | #define AU1X00_MAC_DMA_RX0_ADDR(x) (*(volatile unsigned32*)(x + 0x130)) |
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311 | |
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312 | typedef struct { |
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313 | volatile unsigned32 stat; |
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314 | volatile unsigned32 addr; |
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315 | unsigned32 _rsv0; |
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316 | unsigned32 _rsv1; |
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317 | } au1x00_macdma_rx_t; |
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318 | |
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319 | |
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320 | typedef struct { |
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321 | volatile unsigned32 stat; |
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322 | volatile unsigned32 addr; |
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323 | volatile unsigned32 len; |
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324 | unsigned32 _rsv0; |
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325 | } au1x00_macdma_tx_t; |
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326 | |
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327 | #define AU1X00_MAC_CTRL_RA (bit(31)) |
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328 | #define AU1X00_MAC_CTRL_EM (bit(30)) |
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329 | #define AU1X00_MAC_CTRL_DO (bit(23)) |
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330 | #define AU1X00_MAC_CTRL_LM(x) ((x) << 21) |
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331 | #define AU1X00_MAC_CTRL_LM_NORMAL ((0) << 21) |
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332 | #define AU1X00_MAC_CTRL_LM_INTERNAL ((1) << 21) |
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333 | #define AU1X00_MAC_CTRL_LM_EXTERNAL ((2) << 21) |
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334 | #define AU1X00_MAC_CTRL_F (bit(20)) |
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335 | #define AU1X00_MAC_CTRL_PM (bit(19)) |
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336 | #define AU1X00_MAC_CTRL_PR (bit(18)) |
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337 | #define AU1X00_MAC_CTRL_IF (bit(17)) |
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338 | #define AU1X00_MAC_CTRL_PB (bit(16)) |
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339 | #define AU1X00_MAC_CTRL_HO (bit(15)) |
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340 | #define AU1X00_MAC_CTRL_HP (bit(13)) |
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341 | #define AU1X00_MAC_CTRL_LC (bit(12)) |
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342 | #define AU1X00_MAC_CTRL_DB (bit(11)) |
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343 | #define AU1X00_MAC_CTRL_DR (bit(10)) |
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344 | #define AU1X00_MAC_CTRL_AP (bit(8)) |
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345 | #define AU1X00_MAC_CTRL_BL(x) ((x) << 6) |
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346 | #define AU1X00_MAC_CTRL_DC (bit(5)) |
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347 | #define AU1X00_MAC_CTRL_TE (bit(3)) |
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348 | #define AU1X00_MAC_CTRL_RE (bit(2)) |
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349 | |
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350 | #define AU1X00_MAC_EN_JP (bit(6)) |
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351 | #define AU1X00_MAC_EN_E2 (bit(5)) |
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352 | #define AU1X00_MAC_EN_E1 (bit(4)) |
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353 | #define AU1X00_MAC_EN_C (bit(3)) |
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354 | #define AU1X00_MAC_EN_TS (bit(2)) |
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355 | #define AU1X00_MAC_EN_E0 (bit(1)) |
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356 | #define AU1X00_MAC_EN_CE (bit(0)) |
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357 | |
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358 | #define AU1X00_MAC_ADDRHIGH_MASK (0xffff)_ |
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359 | #define AU1X00_MAC_MIICTRL_PHYADDR(x) ((x & 0x1f) << 11) |
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360 | #define AU1X00_MAC_MIICTRL_MIIREG(x) ((x & 0x1f) << 6) |
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361 | #define AU1X00_MAC_MIICTRL_MW (bit(1)) |
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362 | #define AU1X00_MAC_MIICTRL_MB (bit(0)) |
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363 | #define AU1X00_MAC_MIIDATA_MASK (0xffff) |
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364 | #define AU1X00_MAC_FLOWCTRL_PT(x) (((x) & 0xffff) << 16) |
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365 | #define AU1X00_MAC_FLOWCTRL_PC (bit(2)) |
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366 | #define AU1X00_MAC_FLOWCTRL_FE (bit(1)) |
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367 | #define AU1X00_MAC_FLOWCTRL_FB (bit(0)) |
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368 | |
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369 | #define AU1X00_MAC_DMA_RXSTAT_MI (bit(31)) |
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370 | #define AU1X00_MAC_DMA_RXSTAT_PF (bit(30)) |
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371 | #define AU1X00_MAC_DMA_RXSTAT_FF (bit(29)) |
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372 | #define AU1X00_MAC_DMA_RXSTAT_BF (bit(28)) |
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373 | #define AU1X00_MAC_DMA_RXSTAT_MF (bit(27)) |
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374 | #define AU1X00_MAC_DMA_RXSTAT_UC (bit(26)) |
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375 | #define AU1X00_MAC_DMA_RXSTAT_CF (bit(25)) |
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376 | #define AU1X00_MAC_DMA_RXSTAT_LE (bit(24)) |
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377 | #define AU1X00_MAC_DMA_RXSTAT_V2 (bit(23)) |
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378 | #define AU1X00_MAC_DMA_RXSTAT_V1 (bit(22)) |
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379 | #define AU1X00_MAC_DMA_RXSTAT_CR (bit(21)) |
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380 | #define AU1X00_MAC_DMA_RXSTAT_DB (bit(20)) |
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381 | #define AU1X00_MAC_DMA_RXSTAT_ME (bit(19)) |
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382 | #define AU1X00_MAC_DMA_RXSTAT_FT (bit(18)) |
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383 | #define AU1X00_MAC_DMA_RXSTAT_CS (bit(17)) |
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384 | #define AU1X00_MAC_DMA_RXSTAT_FL (bit(16)) |
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385 | #define AU1X00_MAC_DMA_RXSTAT_RF (bit(15)) |
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386 | #define AU1X00_MAC_DMA_RXSTAT_WT (bit(14)) |
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387 | #define AU1X00_MAC_DMA_RXSTAT_LEN(x) ((x) & 0x3fff) |
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388 | #define AU1X00_MAC_DMA_RXADDR_ADDR(x) ((x) & ~0x1f) |
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389 | #define AU1X00_MAC_DMA_RXADDR_CB_MASK (0x3 << 0x2) |
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390 | #define AU1X00_MAC_DMA_RXADDR_DN (bit(1)) |
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391 | #define AU1X00_MAC_DMA_RXADDR_EN (bit(0)) |
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392 | |
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393 | |
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394 | #define AU1X00_MAC_DMA_TXSTAT_PR (bit(31)) |
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395 | #define AU1X00_MAC_DMA_TXSTAT_CC_MASK (0xf << 10) |
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396 | #define AU1X00_MAC_DMA_TXSTAT_LO (bit(9)) |
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397 | #define AU1X00_MAC_DMA_TXSTAT_DF (bit(8)) |
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398 | #define AU1X00_MAC_DMA_TXSTAT_UR (bit(7)) |
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399 | #define AU1X00_MAC_DMA_TXSTAT_EC (bit(6)) |
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400 | #define AU1X00_MAC_DMA_TXSTAT_LC (bit(5)) |
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401 | #define AU1X00_MAC_DMA_TXSTAT_ED (bit(4)) |
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402 | #define AU1X00_MAC_DMA_TXSTAT_LS (bit(3)) |
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403 | #define AU1X00_MAC_DMA_TXSTAT_NC (bit(2)) |
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404 | #define AU1X00_MAC_DMA_TXSTAT_JT (bit(1)) |
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405 | #define AU1X00_MAC_DMA_TXSTAT_FA (bit(0)) |
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406 | #define AU1X00_MAC_DMA_TXADDR_ADDR(x) ((x) & ~0x1f) |
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407 | #define AU1X00_MAC_DMA_TXADDR_CB_MASK (0x3 << 0x2) |
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408 | #define AU1X00_MAC_DMA_TXADDR_DN (bit(1)) |
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409 | #define AU1X00_MAC_DMA_TXADDR_EN (bit(0)) |
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410 | |
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411 | |
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412 | |
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413 | typedef struct { |
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414 | volatile unsigned long rxdata; |
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415 | volatile unsigned long txdata; |
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416 | volatile unsigned long inten; |
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417 | volatile unsigned long intcause; |
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418 | volatile unsigned long fifoctrl; |
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419 | volatile unsigned long linectrl; |
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420 | volatile unsigned long mdmctrl; |
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421 | volatile unsigned long linestat; |
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422 | volatile unsigned long mdmstat; |
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423 | volatile unsigned long clkdiv; |
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424 | volatile unsigned long _resv[54]; |
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425 | volatile unsigned long enable; |
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426 | } au1x00_uart_t; |
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427 | |
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428 | extern au1x00_uart_t *uart0; |
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429 | extern au1x00_uart_t *uart3; |
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430 | |
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431 | /* |
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432 | * Interrupt Vector Numbers |
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433 | * |
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434 | */ |
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435 | /* MIPS_INTERRUPT_BASE should be 32 (0x20) */ |
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436 | #define AU1X00_IRQ_SW0 (MIPS_INTERRUPT_BASE + 0) |
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437 | #define AU1X00_IRQ_SW1 (MIPS_INTERRUPT_BASE + 1) |
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438 | #define AU1X00_IRQ_IC0_REQ0 (MIPS_INTERRUPT_BASE + 2) |
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439 | #define AU1X00_IRQ_IC0_REQ1 (MIPS_INTERRUPT_BASE + 3) |
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440 | #define AU1X00_IRQ_IC1_REQ0 (MIPS_INTERRUPT_BASE + 4) |
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441 | #define AU1X00_IRQ_IC1_REQ1 (MIPS_INTERRUPT_BASE + 5) |
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442 | #define AU1X00_IRQ_PERF (MIPS_INTERRUPT_BASE + 6) |
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443 | #define AU1X00_IRQ_CNT (MIPS_INTERRUPT_BASE + 7) |
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444 | |
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445 | #define AU1X00_IRQ_IC0_BASE (MIPS_INTERRUPT_BASE + 8) |
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446 | #define AU1X00_IRQ_UART0 (MIPS_INTERRUPT_BASE + 8) |
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447 | #define AU1X00_IRQ_INTA (MIPS_INTERRUPT_BASE + 9) |
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448 | #define AU1X00_IRQ_INTB (MIPS_INTERRUPT_BASE + 10) |
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449 | #define AU1X00_IRQ_UART3 (MIPS_INTERRUPT_BASE + 11) |
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450 | #define AU1X00_IRQ_INTC (MIPS_INTERRUPT_BASE + 12) |
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451 | #define AU1X00_IRQ_INTD (MIPS_INTERRUPT_BASE + 13) |
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452 | #define AU1X00_IRQ_DMA0 (MIPS_INTERRUPT_BASE + 14) |
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453 | #define AU1X00_IRQ_DMA1 (MIPS_INTERRUPT_BASE + 15) |
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454 | #define AU1X00_IRQ_DMA2 (MIPS_INTERRUPT_BASE + 16) |
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455 | #define AU1X00_IRQ_DMA3 (MIPS_INTERRUPT_BASE + 17) |
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456 | #define AU1X00_IRQ_DMA4 (MIPS_INTERRUPT_BASE + 18) |
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457 | #define AU1X00_IRQ_DMA5 (MIPS_INTERRUPT_BASE + 19) |
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458 | #define AU1X00_IRQ_DMA6 (MIPS_INTERRUPT_BASE + 20) |
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459 | #define AU1X00_IRQ_DMA7 (MIPS_INTERRUPT_BASE + 21) |
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460 | #define AU1X00_IRQ_TOY_TICK (MIPS_INTERRUPT_BASE + 22) |
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461 | #define AU1X00_IRQ_TOY_MATCH0 (MIPS_INTERRUPT_BASE + 23) |
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462 | #define AU1X00_IRQ_TOY_MATCH1 (MIPS_INTERRUPT_BASE + 24) |
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463 | #define AU1X00_IRQ_TOY_MATCH2 (MIPS_INTERRUPT_BASE + 25) |
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464 | #define AU1X00_IRQ_RTC_TICK (MIPS_INTERRUPT_BASE + 26) |
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465 | #define AU1X00_IRQ_RTC_MATCH0 (MIPS_INTERRUPT_BASE + 27) |
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466 | #define AU1X00_IRQ_RTC_MATCH1 (MIPS_INTERRUPT_BASE + 28) |
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467 | #define AU1X00_IRQ_RTC_MATCH2 (MIPS_INTERRUPT_BASE + 29) |
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468 | #define AU1X00_IRQ_PCI_ERR (MIPS_INTERRUPT_BASE + 30) |
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469 | #define AU1X00_IRQ_RSV0 (MIPS_INTERRUPT_BASE + 31) |
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470 | #define AU1X00_IRQ_USB_DEV (MIPS_INTERRUPT_BASE + 32) |
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471 | #define AU1X00_IRQ_USB_SUSPEND (MIPS_INTERRUPT_BASE + 33) |
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472 | #define AU1X00_IRQ_USB_HOST (MIPS_INTERRUPT_BASE + 34) |
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473 | #define AU1X00_IRQ_AC97_ACSYNC (MIPS_INTERRUPT_BASE + 35) |
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474 | #define AU1X00_IRQ_MAC0 (MIPS_INTERRUPT_BASE + 36) |
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475 | #define AU1X00_IRQ_MAC1 (MIPS_INTERRUPT_BASE + 37) |
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476 | #define AU1X00_IRQ_RSV1 (MIPS_INTERRUPT_BASE + 38) |
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477 | #define AU1X00_IRQ_AC97_CMD (MIPS_INTERRUPT_BASE + 39) |
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478 | |
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479 | #define AU1X00_IRQ_IC1_BASE (MIPS_INTERRUPT_BASE + 40) |
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480 | #define AU1X00_IRQ_GPIO0 (MIPS_INTERRUPT_BASE + 40) |
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481 | #define AU1X00_IRQ_GPIO1 (MIPS_INTERRUPT_BASE + 41) |
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482 | #define AU1X00_IRQ_GPIO2 (MIPS_INTERRUPT_BASE + 42) |
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483 | #define AU1X00_IRQ_GPIO3 (MIPS_INTERRUPT_BASE + 43) |
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484 | #define AU1X00_IRQ_GPIO4 (MIPS_INTERRUPT_BASE + 44) |
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485 | #define AU1X00_IRQ_GPIO5 (MIPS_INTERRUPT_BASE + 45) |
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486 | #define AU1X00_IRQ_GPIO6 (MIPS_INTERRUPT_BASE + 46) |
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487 | #define AU1X00_IRQ_GPIO7 (MIPS_INTERRUPT_BASE + 47) |
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488 | #define AU1X00_IRQ_GPIO8 (MIPS_INTERRUPT_BASE + 48) |
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489 | #define AU1X00_IRQ_GPIO9 (MIPS_INTERRUPT_BASE + 49) |
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490 | #define AU1X00_IRQ_GPIO10 (MIPS_INTERRUPT_BASE + 50) |
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491 | #define AU1X00_IRQ_GPIO11 (MIPS_INTERRUPT_BASE + 51) |
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492 | #define AU1X00_IRQ_GPIO12 (MIPS_INTERRUPT_BASE + 52) |
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493 | #define AU1X00_IRQ_GPIO13 (MIPS_INTERRUPT_BASE + 53) |
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494 | #define AU1X00_IRQ_GPIO14 (MIPS_INTERRUPT_BASE + 54) |
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495 | #define AU1X00_IRQ_GPIO15 (MIPS_INTERRUPT_BASE + 55) |
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496 | #define AU1X00_IRQ_GPIO200 (MIPS_INTERRUPT_BASE + 56) |
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497 | #define AU1X00_IRQ_GPIO201 (MIPS_INTERRUPT_BASE + 57) |
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498 | #define AU1X00_IRQ_GPIO202 (MIPS_INTERRUPT_BASE + 58) |
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499 | #define AU1X00_IRQ_GPIO203 (MIPS_INTERRUPT_BASE + 59) |
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500 | #define AU1X00_IRQ_GPIO20 (MIPS_INTERRUPT_BASE + 60) |
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501 | #define AU1X00_IRQ_GPIO204 (MIPS_INTERRUPT_BASE + 61) |
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502 | #define AU1X00_IRQ_GPIO205 (MIPS_INTERRUPT_BASE + 62) |
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503 | #define AU1X00_IRQ_GPIO23 (MIPS_INTERRUPT_BASE + 63) |
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504 | #define AU1X00_IRQ_GPIO24 (MIPS_INTERRUPT_BASE + 64) |
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505 | #define AU1X00_IRQ_GPIO25 (MIPS_INTERRUPT_BASE + 65) |
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506 | #define AU1X00_IRQ_GPIO26 (MIPS_INTERRUPT_BASE + 66) |
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507 | #define AU1X00_IRQ_GPIO27 (MIPS_INTERRUPT_BASE + 67) |
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508 | #define AU1X00_IRQ_GPIO28 (MIPS_INTERRUPT_BASE + 68) |
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509 | #define AU1X00_IRQ_GPIO206 (MIPS_INTERRUPT_BASE + 69) |
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510 | #define AU1X00_IRQ_GPIO207 (MIPS_INTERRUPT_BASE + 70) |
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511 | #define AU1X00_IRQ_GPIO208_215 (MIPS_INTERRUPT_BASE + 71) |
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512 | |
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513 | #define AU1X00_MAXIMUM_VECTORS (MIPS_INTERRUPT_BASE + 72) |
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514 | |
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515 | void static inline au_sync(void) |
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516 | { |
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517 | __asm__ volatile ("sync"); |
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518 | } |
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519 | |
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520 | #endif |
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