source: rtems/c/src/lib/libcpu/m68k/shared/cache/cache.c @ 9b4422a2

4.115
Last change on this file since 9b4422a2 was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on May 3, 2012 at 3:09:24 PM

Remove All CVS Id Strings Possible Using a Script

Script does what is expected and tries to do it as
smartly as possible.

+ remove occurrences of two blank comment lines

next to each other after Id string line removed.

+ remove entire comment blocks which only exited to

contain CVS Ids

+ If the processing left a blank line at the top of

a file, it was removed.

  • Property mode set to 100644
File size: 4.6 KB
Line 
1/*
2 *  Cache Management Support Routines for the MC68040
3 */
4
5#include <rtems.h>
6#include "cache_.h"
7
8/*
9 *  Since the cacr is common to all mc680x0, provide macros
10 *  for masking values in that register.
11 */
12
13/*
14 *  Used to clear bits in the cacr.
15 */
16#define _CPU_CACR_AND(mask)                                        \
17  {                                                                \
18  register unsigned long _value = mask;                            \
19  register unsigned long _ctl = 0;                                 \
20  __asm__ volatile ( "movec %%cacr, %0;           /* read the cacr */  \
21                  andl %2, %0;                /* and with _val */  \
22                  movec %1, %%cacr"           /* write the cacr */ \
23   : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" );            \
24  }
25
26
27/*
28 *  Used to set bits in the cacr.
29 */
30#define _CPU_CACR_OR(mask)                                         \
31        {                                                                \
32  register unsigned long _value = mask;                            \
33  register unsigned long _ctl = 0;                                 \
34  __asm__ volatile ( "movec %%cacr, %0;           /* read the cacr */  \
35                  orl %2, %0;                 /* or with _val */   \
36                  movec %1, %%cacr"           /* write the cacr */ \
37   : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" );            \
38  }
39
40
41/*
42 * CACHE MANAGER: The following functions are CPU-specific.
43 * They provide the basic implementation for the rtems_* cache
44 * management routines. If a given function has no meaning for the CPU,
45 * it does nothing by default.
46 */
47#if ( (defined(__mc68020__) && !defined(__mcpu32__)) || defined(__mc68030__) )
48
49#if defined(__mc68030__)
50
51/* Only the mc68030 has a data cache; it is writethrough only. */
52
53void _CPU_cache_flush_1_data_line ( const void * d_addr ) {}
54void _CPU_cache_flush_entire_data ( void ) {}
55
56void _CPU_cache_invalidate_1_data_line (
57  const void * d_addr )
58{
59  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
60  __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) );      /* write caar */
61  _CPU_CACR_OR(0x00000400);
62}
63
64void _CPU_cache_invalidate_entire_data ( void )
65{
66  _CPU_CACR_OR( 0x00000800 );
67}
68
69void _CPU_cache_freeze_data ( void )
70{
71  _CPU_CACR_OR( 0x00000200 );
72}
73
74void _CPU_cache_unfreeze_data ( void )
75{
76  _CPU_CACR_AND( 0xFFFFFDFF );
77}
78
79void _CPU_cache_enable_data ( void )
80{
81  _CPU_CACR_OR( 0x00000100 );
82}
83void _CPU_cache_disable_data (  void )
84{
85  _CPU_CACR_AND( 0xFFFFFEFF );
86}
87#endif
88
89
90/* Both the 68020 and 68030 have instruction caches */
91
92void _CPU_cache_invalidate_1_instruction_line (
93  const void * d_addr )
94{
95  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
96  __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) );      /* write caar */
97  _CPU_CACR_OR( 0x00000004 );
98}
99
100void _CPU_cache_invalidate_entire_instruction ( void )
101{
102  _CPU_CACR_OR( 0x00000008 );
103}
104
105void _CPU_cache_freeze_instruction ( void )
106{
107  _CPU_CACR_OR( 0x00000002);
108}
109
110void _CPU_cache_unfreeze_instruction ( void )
111{
112  _CPU_CACR_AND( 0xFFFFFFFD );
113}
114
115void _CPU_cache_enable_instruction ( void )
116{
117  _CPU_CACR_OR( 0x00000001 );
118}
119
120void _CPU_cache_disable_instruction (   void )
121{
122  _CPU_CACR_AND( 0xFFFFFFFE );
123}
124
125
126#elif ( defined(__mc68040__) || defined (__mc68060__) )
127
128/* Cannot be frozen */
129void _CPU_cache_freeze_data ( void ) {}
130void _CPU_cache_unfreeze_data ( void ) {}
131void _CPU_cache_freeze_instruction ( void ) {}
132void _CPU_cache_unfreeze_instruction ( void ) {}
133
134void _CPU_cache_flush_1_data_line (
135  const void * d_addr )
136{
137  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
138  __asm__ volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) );
139}
140
141void _CPU_cache_invalidate_1_data_line (
142  const void * d_addr )
143{
144  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
145  __asm__ volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) );
146}
147
148void _CPU_cache_flush_entire_data ( void )
149{
150        asm volatile ( "cpusha %%dc" :: );
151}
152
153void _CPU_cache_invalidate_entire_data ( void )
154{
155        asm volatile ( "cinva %%dc" :: );
156}
157
158void _CPU_cache_enable_data ( void )
159{
160  _CPU_CACR_OR( 0x80000000 );
161}
162
163void _CPU_cache_disable_data ( void )
164{
165  _CPU_CACR_AND( 0x7FFFFFFF );
166}
167
168void _CPU_cache_invalidate_1_instruction_line (
169  const void * i_addr )
170{
171  void * p_address = (void *)  _CPU_virtual_to_physical( i_addr );
172  __asm__ volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) );
173}
174
175void _CPU_cache_invalidate_entire_instruction ( void )
176{
177                asm volatile ( "cinva %%ic" :: );
178}
179
180void _CPU_cache_enable_instruction ( void )
181{
182  _CPU_CACR_OR( 0x00008000 );
183}
184
185void _CPU_cache_disable_instruction ( void )
186{
187        _CPU_CACR_AND( 0xFFFF7FFF );
188}
189#endif
190/* end of file */
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