source: rtems/c/src/lib/libcpu/m68k/shared/cache/cache.c @ 5e77d129

4.104.114.84.95
Last change on this file since 5e77d129 was 5e77d129, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 14, 2000 at 8:32:44 PM

Patch from John Cotton <john.cotton@…> to correct cache
routine naming to follow RTEMS package/object.method rule.
This patch also eliminated calls to the obsolete routine
m68k_enable_caching.

  • Property mode set to 100644
File size: 4.6 KB
Line 
1/*
2 *  Cache Management Support Routines for the MC68040
3 *
4 *  $Id$
5 */
6
7#include <rtems.h>
8#include "cache_.h"
9
10/* 
11 *  Since the cacr is common to all mc680x0, provide macros
12 *  for masking values in that register.
13 */
14
15/*
16 *  Used to clear bits in the cacr.
17 */
18#define _CPU_CACR_AND(mask)                                        \
19  {                                                                \
20  register unsigned long _value = mask;                            \
21  register unsigned long _ctl = 0;                                 \
22  asm volatile ( "movec %%cacr, %0;           /* read the cacr */  \
23                  andl %2, %0;                /* and with _val */  \
24                  movec %1, %%cacr"           /* write the cacr */ \
25   : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" );            \
26  }
27
28
29/* 
30 *  Used to set bits in the cacr.
31 */
32#define _CPU_CACR_OR(mask)                                         \
33        {                                                                \
34  register unsigned long _value = mask;                            \
35  register unsigned long _ctl = 0;                                 \
36  asm volatile ( "movec %%cacr, %0;           /* read the cacr */  \
37                  orl %2, %0;                 /* or with _val */   \
38                  movec %1, %%cacr"           /* write the cacr */ \
39   : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" );            \
40  }
41
42   
43/*
44 * CACHE MANAGER: The following functions are CPU-specific.
45 * They provide the basic implementation for the rtems_* cache
46 * management routines. If a given function has no meaning for the CPU,
47 * it does nothing by default.
48 */
49#if ( defined(__mc68020__) || defined(__mc68030__) )
50
51#if defined(__mc68030__)
52
53/* Only the mc68030 has a data cache; it is writethrough only. */
54
55void _CPU_cache_flush_1_data_line ( const void * d_addr ) {}
56void _CPU_cache_flush_entire_data ( const void * d_addr ) {}
57
58void _CPU_cache_invalidate_1_data_line (
59  const void * d_addr )
60{
61  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
62  asm volatile ( "movec %0, %%caar" :: "a" (p_address) );      /* write caar */
63  _CPU_CACR_OR(0x00000400);
64}
65
66void _CPU_cache_invalidate_entire_data ( void )
67{
68  _CPU_CACR_OR( 0x00000800 );
69}
70
71void _CPU_cache_freeze_data ( void )
72{
73  _CPU_CACR_OR( 0x00000200 );
74}
75
76void _CPU_cache_unfreeze_data ( void )
77{
78  _CPU_CACR_AND( 0xFFFFFDFF );
79}
80
81void _CPU_cache_enable_data ( void )
82{
83  _CPU_CACR_OR( 0x00000100 );
84}
85void _CPU_cache_disable_data (  void )
86{
87  _CPU_CACR_AND( 0xFFFFFEFF );
88}
89#endif
90
91
92/* Both the 68020 and 68030 have instruction caches */
93
94void _CPU_cache_invalidate_1_instruction_line (
95  const void * d_addr )
96{
97  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
98  asm volatile ( "movec %0, %%caar" :: "a" (p_address) );      /* write caar */
99  _CPU_CACR_OR( 0x00000004 );
100}
101
102void _CPU_cache_invalidate_entire_instruction ( void )
103{
104  _CPU_CACR_OR( 0x00000008 );
105}
106
107void _CPU_cache_freeze_instruction ( void )
108{
109  _CPU_CACR_OR( 0x00000002);
110}
111
112void _CPU_cache_unfreeze_instruction ( void )
113{
114  _CPU_CACR_AND( 0xFFFFFFFD );
115}
116
117void _CPU_cache_enable_instruction ( void )
118{
119  _CPU_CACR_OR( 0x00000001 );
120}
121
122void _CPU_cache_disable_instruction (   void )
123{
124  _CPU_CACR_AND( 0xFFFFFFFE );
125}
126
127
128#elif ( defined(__mc68040__) || defined (__mc68060__) )
129
130/* Cannot be frozen */
131void _CPU_cache_freeze_data ( void ) {}
132void _CPU_cache_unfreeze_data ( void ) {}
133void _CPU_cache_freeze_instruction ( void ) {}
134void _CPU_cache_unfreeze_instruction ( void ) {}
135
136void _CPU_cache_flush_1_data_line (
137  const void * d_addr )
138{
139  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
140  asm volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) );
141}
142
143void _CPU_cache_invalidate_1_data_line (
144  const void * d_addr )
145{
146  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
147  asm volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) );
148}
149
150void _CPU_cache_flush_entire_data ( void )
151{
152        asm volatile ( "cpusha %%dc" :: );
153}
154
155void _CPU_cache_invalidate_entire_data ( void )
156{
157        asm volatile ( "cinva %%dc" :: );
158}
159
160void _CPU_cache_enable_data ( void )
161{
162  _CPU_CACR_OR( 0x80000000 );
163}
164
165void _CPU_cache_disable_data ( void )
166{
167  _CPU_CACR_AND( 0x7FFFFFFF );
168}
169
170void _CPU_cache_invalidate_1_instruction_line (
171  const void * i_addr )
172{
173  void * p_address = (void *)  _CPU_virtual_to_physical( i_addr );
174  asm volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) );
175}
176
177void _CPU_cache_invalidate_entire_instruction ( void )
178{
179                asm volatile ( "cinva %%ic" :: );
180}
181
182void _CPU_cache_enable_instruction ( void )
183{
184  _CPU_CACR_OR( 0x00008000 );
185}
186
187void _CPU_cache_disable_instruction ( void )
188{
189        _CPU_CACR_AND( 0xFFFF7FFF );
190}
191#endif
192/* end of file */
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