[cf1f72e] | 1 | /* |
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| 2 | * Cache Management Support Routines for the MC68040 |
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| 3 | */ |
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| 4 | |
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| 5 | #include <rtems.h> |
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| 6 | #include "cache_.h" |
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| 7 | |
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[c758a4ec] | 8 | /* |
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[cf1f72e] | 9 | * Since the cacr is common to all mc680x0, provide macros |
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| 10 | * for masking values in that register. |
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| 11 | */ |
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| 12 | |
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[c758a4ec] | 13 | /* |
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[cf1f72e] | 14 | * Used to clear bits in the cacr. |
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| 15 | */ |
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| 16 | #define _CPU_CACR_AND(mask) \ |
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| 17 | { \ |
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| 18 | register unsigned long _value = mask; \ |
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| 19 | register unsigned long _ctl = 0; \ |
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[8525cff] | 20 | __asm__ volatile ( "movec %%cacr, %0; /* read the cacr */ \ |
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[cf1f72e] | 21 | andl %2, %0; /* and with _val */ \ |
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| 22 | movec %1, %%cacr" /* write the cacr */ \ |
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| 23 | : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \ |
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| 24 | } |
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| 25 | |
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| 26 | |
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[c758a4ec] | 27 | /* |
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[cf1f72e] | 28 | * Used to set bits in the cacr. |
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| 29 | */ |
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| 30 | #define _CPU_CACR_OR(mask) \ |
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| 31 | { \ |
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| 32 | register unsigned long _value = mask; \ |
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| 33 | register unsigned long _ctl = 0; \ |
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[8525cff] | 34 | __asm__ volatile ( "movec %%cacr, %0; /* read the cacr */ \ |
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[cf1f72e] | 35 | orl %2, %0; /* or with _val */ \ |
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| 36 | movec %1, %%cacr" /* write the cacr */ \ |
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| 37 | : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \ |
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| 38 | } |
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| 39 | |
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[c758a4ec] | 40 | |
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[cf1f72e] | 41 | /* |
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| 42 | * CACHE MANAGER: The following functions are CPU-specific. |
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| 43 | * They provide the basic implementation for the rtems_* cache |
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| 44 | * management routines. If a given function has no meaning for the CPU, |
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| 45 | * it does nothing by default. |
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| 46 | */ |
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[0ee9cc1] | 47 | #if ( (defined(__mc68020__) && !defined(__mcpu32__)) || defined(__mc68030__) ) |
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[cf1f72e] | 48 | |
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| 49 | #if defined(__mc68030__) |
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| 50 | |
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| 51 | /* Only the mc68030 has a data cache; it is writethrough only. */ |
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| 52 | |
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[5e77d129] | 53 | void _CPU_cache_flush_1_data_line ( const void * d_addr ) {} |
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[baa6f32c] | 54 | void _CPU_cache_flush_entire_data ( void ) {} |
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[cf1f72e] | 55 | |
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[5e77d129] | 56 | void _CPU_cache_invalidate_1_data_line ( |
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[cf1f72e] | 57 | const void * d_addr ) |
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| 58 | { |
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| 59 | void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); |
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[8525cff] | 60 | __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */ |
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[cf1f72e] | 61 | _CPU_CACR_OR(0x00000400); |
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| 62 | } |
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| 63 | |
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[5e77d129] | 64 | void _CPU_cache_invalidate_entire_data ( void ) |
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[cf1f72e] | 65 | { |
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| 66 | _CPU_CACR_OR( 0x00000800 ); |
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| 67 | } |
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| 68 | |
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[5e77d129] | 69 | void _CPU_cache_freeze_data ( void ) |
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[cf1f72e] | 70 | { |
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| 71 | _CPU_CACR_OR( 0x00000200 ); |
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| 72 | } |
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| 73 | |
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[5e77d129] | 74 | void _CPU_cache_unfreeze_data ( void ) |
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[cf1f72e] | 75 | { |
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| 76 | _CPU_CACR_AND( 0xFFFFFDFF ); |
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| 77 | } |
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| 78 | |
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[5e77d129] | 79 | void _CPU_cache_enable_data ( void ) |
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[cf1f72e] | 80 | { |
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| 81 | _CPU_CACR_OR( 0x00000100 ); |
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| 82 | } |
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[5e77d129] | 83 | void _CPU_cache_disable_data ( void ) |
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[cf1f72e] | 84 | { |
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| 85 | _CPU_CACR_AND( 0xFFFFFEFF ); |
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| 86 | } |
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| 87 | #endif |
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| 88 | |
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| 89 | |
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| 90 | /* Both the 68020 and 68030 have instruction caches */ |
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| 91 | |
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[5e77d129] | 92 | void _CPU_cache_invalidate_1_instruction_line ( |
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[cf1f72e] | 93 | const void * d_addr ) |
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| 94 | { |
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| 95 | void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); |
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[8525cff] | 96 | __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */ |
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[cf1f72e] | 97 | _CPU_CACR_OR( 0x00000004 ); |
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| 98 | } |
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| 99 | |
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[5e77d129] | 100 | void _CPU_cache_invalidate_entire_instruction ( void ) |
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[cf1f72e] | 101 | { |
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| 102 | _CPU_CACR_OR( 0x00000008 ); |
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| 103 | } |
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| 104 | |
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[5e77d129] | 105 | void _CPU_cache_freeze_instruction ( void ) |
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[cf1f72e] | 106 | { |
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| 107 | _CPU_CACR_OR( 0x00000002); |
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| 108 | } |
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| 109 | |
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[5e77d129] | 110 | void _CPU_cache_unfreeze_instruction ( void ) |
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[cf1f72e] | 111 | { |
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| 112 | _CPU_CACR_AND( 0xFFFFFFFD ); |
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| 113 | } |
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| 114 | |
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[5e77d129] | 115 | void _CPU_cache_enable_instruction ( void ) |
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[cf1f72e] | 116 | { |
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| 117 | _CPU_CACR_OR( 0x00000001 ); |
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| 118 | } |
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| 119 | |
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[5e77d129] | 120 | void _CPU_cache_disable_instruction ( void ) |
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[cf1f72e] | 121 | { |
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| 122 | _CPU_CACR_AND( 0xFFFFFFFE ); |
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| 123 | } |
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| 124 | |
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| 125 | |
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| 126 | #elif ( defined(__mc68040__) || defined (__mc68060__) ) |
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| 127 | |
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| 128 | /* Cannot be frozen */ |
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[5e77d129] | 129 | void _CPU_cache_freeze_data ( void ) {} |
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| 130 | void _CPU_cache_unfreeze_data ( void ) {} |
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| 131 | void _CPU_cache_freeze_instruction ( void ) {} |
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| 132 | void _CPU_cache_unfreeze_instruction ( void ) {} |
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[cf1f72e] | 133 | |
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[5e77d129] | 134 | void _CPU_cache_flush_1_data_line ( |
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[cf1f72e] | 135 | const void * d_addr ) |
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| 136 | { |
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| 137 | void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); |
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[8525cff] | 138 | __asm__ volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) ); |
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[cf1f72e] | 139 | } |
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| 140 | |
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[5e77d129] | 141 | void _CPU_cache_invalidate_1_data_line ( |
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[cf1f72e] | 142 | const void * d_addr ) |
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| 143 | { |
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| 144 | void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); |
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[8525cff] | 145 | __asm__ volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) ); |
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[cf1f72e] | 146 | } |
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| 147 | |
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[5e77d129] | 148 | void _CPU_cache_flush_entire_data ( void ) |
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[cf1f72e] | 149 | { |
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| 150 | asm volatile ( "cpusha %%dc" :: ); |
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| 151 | } |
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| 152 | |
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[5e77d129] | 153 | void _CPU_cache_invalidate_entire_data ( void ) |
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[cf1f72e] | 154 | { |
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| 155 | asm volatile ( "cinva %%dc" :: ); |
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| 156 | } |
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| 157 | |
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[5e77d129] | 158 | void _CPU_cache_enable_data ( void ) |
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[cf1f72e] | 159 | { |
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| 160 | _CPU_CACR_OR( 0x80000000 ); |
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| 161 | } |
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| 162 | |
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[5e77d129] | 163 | void _CPU_cache_disable_data ( void ) |
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[cf1f72e] | 164 | { |
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| 165 | _CPU_CACR_AND( 0x7FFFFFFF ); |
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| 166 | } |
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| 167 | |
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[5e77d129] | 168 | void _CPU_cache_invalidate_1_instruction_line ( |
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[cf1f72e] | 169 | const void * i_addr ) |
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| 170 | { |
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| 171 | void * p_address = (void *) _CPU_virtual_to_physical( i_addr ); |
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[8525cff] | 172 | __asm__ volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) ); |
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[cf1f72e] | 173 | } |
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| 174 | |
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[5e77d129] | 175 | void _CPU_cache_invalidate_entire_instruction ( void ) |
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[cf1f72e] | 176 | { |
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| 177 | asm volatile ( "cinva %%ic" :: ); |
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| 178 | } |
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| 179 | |
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[5e77d129] | 180 | void _CPU_cache_enable_instruction ( void ) |
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[cf1f72e] | 181 | { |
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| 182 | _CPU_CACR_OR( 0x00008000 ); |
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| 183 | } |
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| 184 | |
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[5e77d129] | 185 | void _CPU_cache_disable_instruction ( void ) |
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[cf1f72e] | 186 | { |
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| 187 | _CPU_CACR_AND( 0xFFFF7FFF ); |
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| 188 | } |
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| 189 | #endif |
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| 190 | /* end of file */ |
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