[cf1f72e] | 1 | /* |
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| 2 | * Cache Management Support Routines for the MC68040 |
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| 3 | * |
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| 4 | * $Id$ |
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| 5 | */ |
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| 6 | |
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| 7 | #include <rtems.h> |
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| 8 | #include "cache_.h" |
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| 9 | |
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| 10 | /* |
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| 11 | * Since the cacr is common to all mc680x0, provide macros |
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| 12 | * for masking values in that register. |
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| 13 | */ |
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| 14 | |
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| 15 | /* |
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| 16 | * Used to clear bits in the cacr. |
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| 17 | */ |
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| 18 | #define _CPU_CACR_AND(mask) \ |
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| 19 | { \ |
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| 20 | register unsigned long _value = mask; \ |
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| 21 | register unsigned long _ctl = 0; \ |
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| 22 | asm volatile ( "movec %%cacr, %0; /* read the cacr */ \ |
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| 23 | andl %2, %0; /* and with _val */ \ |
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| 24 | movec %1, %%cacr" /* write the cacr */ \ |
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| 25 | : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \ |
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| 26 | } |
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| 27 | |
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| 28 | |
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| 29 | /* |
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| 30 | * Used to set bits in the cacr. |
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| 31 | */ |
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| 32 | #define _CPU_CACR_OR(mask) \ |
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| 33 | { \ |
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| 34 | register unsigned long _value = mask; \ |
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| 35 | register unsigned long _ctl = 0; \ |
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| 36 | asm volatile ( "movec %%cacr, %0; /* read the cacr */ \ |
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| 37 | orl %2, %0; /* or with _val */ \ |
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| 38 | movec %1, %%cacr" /* write the cacr */ \ |
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| 39 | : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \ |
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| 40 | } |
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| 41 | |
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| 42 | |
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| 43 | /* |
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| 44 | * CACHE MANAGER: The following functions are CPU-specific. |
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| 45 | * They provide the basic implementation for the rtems_* cache |
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| 46 | * management routines. If a given function has no meaning for the CPU, |
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| 47 | * it does nothing by default. |
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| 48 | */ |
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[0ee9cc1] | 49 | #if ( (defined(__mc68020__) && !defined(__mcpu32__)) || defined(__mc68030__) ) |
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[cf1f72e] | 50 | |
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| 51 | #if defined(__mc68030__) |
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| 52 | |
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| 53 | /* Only the mc68030 has a data cache; it is writethrough only. */ |
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| 54 | |
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[5e77d129] | 55 | void _CPU_cache_flush_1_data_line ( const void * d_addr ) {} |
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[baa6f32c] | 56 | void _CPU_cache_flush_entire_data ( void ) {} |
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[cf1f72e] | 57 | |
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[5e77d129] | 58 | void _CPU_cache_invalidate_1_data_line ( |
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[cf1f72e] | 59 | const void * d_addr ) |
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| 60 | { |
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| 61 | void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); |
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| 62 | asm volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */ |
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| 63 | _CPU_CACR_OR(0x00000400); |
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| 64 | } |
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| 65 | |
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[5e77d129] | 66 | void _CPU_cache_invalidate_entire_data ( void ) |
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[cf1f72e] | 67 | { |
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| 68 | _CPU_CACR_OR( 0x00000800 ); |
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| 69 | } |
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| 70 | |
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[5e77d129] | 71 | void _CPU_cache_freeze_data ( void ) |
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[cf1f72e] | 72 | { |
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| 73 | _CPU_CACR_OR( 0x00000200 ); |
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| 74 | } |
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| 75 | |
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[5e77d129] | 76 | void _CPU_cache_unfreeze_data ( void ) |
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[cf1f72e] | 77 | { |
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| 78 | _CPU_CACR_AND( 0xFFFFFDFF ); |
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| 79 | } |
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| 80 | |
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[5e77d129] | 81 | void _CPU_cache_enable_data ( void ) |
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[cf1f72e] | 82 | { |
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| 83 | _CPU_CACR_OR( 0x00000100 ); |
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| 84 | } |
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[5e77d129] | 85 | void _CPU_cache_disable_data ( void ) |
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[cf1f72e] | 86 | { |
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| 87 | _CPU_CACR_AND( 0xFFFFFEFF ); |
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| 88 | } |
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| 89 | #endif |
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| 90 | |
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| 91 | |
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| 92 | /* Both the 68020 and 68030 have instruction caches */ |
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| 93 | |
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[5e77d129] | 94 | void _CPU_cache_invalidate_1_instruction_line ( |
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[cf1f72e] | 95 | const void * d_addr ) |
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| 96 | { |
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| 97 | void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); |
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| 98 | asm volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */ |
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| 99 | _CPU_CACR_OR( 0x00000004 ); |
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| 100 | } |
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| 101 | |
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[5e77d129] | 102 | void _CPU_cache_invalidate_entire_instruction ( void ) |
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[cf1f72e] | 103 | { |
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| 104 | _CPU_CACR_OR( 0x00000008 ); |
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| 105 | } |
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| 106 | |
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[5e77d129] | 107 | void _CPU_cache_freeze_instruction ( void ) |
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[cf1f72e] | 108 | { |
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| 109 | _CPU_CACR_OR( 0x00000002); |
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| 110 | } |
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| 111 | |
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[5e77d129] | 112 | void _CPU_cache_unfreeze_instruction ( void ) |
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[cf1f72e] | 113 | { |
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| 114 | _CPU_CACR_AND( 0xFFFFFFFD ); |
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| 115 | } |
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| 116 | |
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[5e77d129] | 117 | void _CPU_cache_enable_instruction ( void ) |
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[cf1f72e] | 118 | { |
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| 119 | _CPU_CACR_OR( 0x00000001 ); |
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| 120 | } |
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| 121 | |
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[5e77d129] | 122 | void _CPU_cache_disable_instruction ( void ) |
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[cf1f72e] | 123 | { |
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| 124 | _CPU_CACR_AND( 0xFFFFFFFE ); |
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| 125 | } |
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| 126 | |
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| 127 | |
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| 128 | #elif ( defined(__mc68040__) || defined (__mc68060__) ) |
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| 129 | |
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| 130 | /* Cannot be frozen */ |
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[5e77d129] | 131 | void _CPU_cache_freeze_data ( void ) {} |
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| 132 | void _CPU_cache_unfreeze_data ( void ) {} |
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| 133 | void _CPU_cache_freeze_instruction ( void ) {} |
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| 134 | void _CPU_cache_unfreeze_instruction ( void ) {} |
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[cf1f72e] | 135 | |
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[5e77d129] | 136 | void _CPU_cache_flush_1_data_line ( |
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[cf1f72e] | 137 | const void * d_addr ) |
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| 138 | { |
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| 139 | void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); |
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| 140 | asm volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) ); |
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| 141 | } |
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| 142 | |
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[5e77d129] | 143 | void _CPU_cache_invalidate_1_data_line ( |
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[cf1f72e] | 144 | const void * d_addr ) |
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| 145 | { |
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| 146 | void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); |
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| 147 | asm volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) ); |
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| 148 | } |
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| 149 | |
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[5e77d129] | 150 | void _CPU_cache_flush_entire_data ( void ) |
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[cf1f72e] | 151 | { |
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| 152 | asm volatile ( "cpusha %%dc" :: ); |
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| 153 | } |
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| 154 | |
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[5e77d129] | 155 | void _CPU_cache_invalidate_entire_data ( void ) |
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[cf1f72e] | 156 | { |
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| 157 | asm volatile ( "cinva %%dc" :: ); |
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| 158 | } |
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| 159 | |
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[5e77d129] | 160 | void _CPU_cache_enable_data ( void ) |
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[cf1f72e] | 161 | { |
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| 162 | _CPU_CACR_OR( 0x80000000 ); |
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| 163 | } |
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| 164 | |
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[5e77d129] | 165 | void _CPU_cache_disable_data ( void ) |
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[cf1f72e] | 166 | { |
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| 167 | _CPU_CACR_AND( 0x7FFFFFFF ); |
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| 168 | } |
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| 169 | |
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[5e77d129] | 170 | void _CPU_cache_invalidate_1_instruction_line ( |
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[cf1f72e] | 171 | const void * i_addr ) |
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| 172 | { |
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| 173 | void * p_address = (void *) _CPU_virtual_to_physical( i_addr ); |
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| 174 | asm volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) ); |
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| 175 | } |
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| 176 | |
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[5e77d129] | 177 | void _CPU_cache_invalidate_entire_instruction ( void ) |
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[cf1f72e] | 178 | { |
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| 179 | asm volatile ( "cinva %%ic" :: ); |
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| 180 | } |
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| 181 | |
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[5e77d129] | 182 | void _CPU_cache_enable_instruction ( void ) |
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[cf1f72e] | 183 | { |
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| 184 | _CPU_CACR_OR( 0x00008000 ); |
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| 185 | } |
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| 186 | |
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[5e77d129] | 187 | void _CPU_cache_disable_instruction ( void ) |
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[cf1f72e] | 188 | { |
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| 189 | _CPU_CACR_AND( 0xFFFF7FFF ); |
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| 190 | } |
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| 191 | #endif |
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| 192 | /* end of file */ |
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