/* * File: mcf532x.h * Purpose: Register and bit definitions */ #ifndef __MCF532X_H__ #define __MCF532X_H__ /********************************************************************* * * System Control Module (SCM) * *********************************************************************/ /* Register read/write macros */ #define MCF_SCM_MPR0 (*(vuint32*)(0xEC000000)) #define MCF_SCM_MPR1 (*(vuint32*)(0xFC000000)) #define MCF_SCM_BMT0 (*(vuint32*)(0xEC000054)) #define MCF_SCM_BMT1 (*(vuint32*)(0xFC000054)) #define MCF_SCM_PACRA (*(vuint32*)(0xFC000020)) #define MCF_SCM_PACRB (*(vuint32*)(0xFC000024)) #define MCF_SCM_PACRC (*(vuint32*)(0xFC000028)) #define MCF_SCM_PACRD (*(vuint32*)(0xFC00002C)) #define MCF_SCM_PACRE (*(vuint32*)(0xFC000040)) #define MCF_SCM_PACRF (*(vuint32*)(0xFC000044)) #define MCF_SCM_PACRG (*(vuint32*)(0xEC000048)) #define MCF_SCM_PACRH (*(vuint32*)(0xEC000040)) #define MCF_SCM_CWCR (*(vuint16*)(0xFC040016)) #define MCF_SCM_CWSR (*(vuint8 *)(0xFC04001B)) #define MCF_SCM_CWIR (*(vuint8 *)(0xFC04001F)) #define MCF_SCM_BCR (*(vuint32*)(0xFC040024)) #define MCF_SCM_CFADR (*(vuint32*)(0xFC040070)) #define MCF_SCM_CFIER (*(vuint8 *)(0xFC040075)) #define MCF_SCM_CFLOC (*(vuint8 *)(0xFC040076)) #define MCF_SCM_CFATR (*(vuint8 *)(0xFC040077)) #define MCF_SCM_CFDTR (*(vuint32*)(0xFC04007C)) /* Bit definitions and macros for MCF_SCM_MPR */ #define MCF_SCM_MPR_MPROT6(x) (((x)&0x0000000F)<<4) #define MCF_SCM_MPR_MPROT5(x) (((x)&0x0000000F)<<8) #define MCF_SCM_MPR_MPROT4(x) (((x)&0x0000000F)<<12) #define MCF_SCM_MPR_MPROT2(x) (((x)&0x0000000F)<<20) #define MCF_SCM_MPR_MPROT1(x) (((x)&0x0000000F)<<24) #define MCF_SCM_MPR_MPROT0(x) (((x)&0x0000000F)<<28) #define MCF_SCM_MPR_MPROT_MTR (0x4) #define MCF_SCM_MPR_MPROT_MTW (0x2) #define MCF_SCM_MPR_MPROT_MPL (0x1) /* Bit definitions and macros for MCF_SCM_BMT */ #define MCF_SCM_BMT_BMT(x) (((x)&0x00000007)<<0) #define MCF_SCM_BMT_BME (0x00000008) #define MCF_SCM_BMT_BMT_1024 (0x00000000) #define MCF_SCM_BMT_BMT_512 (0x00000001) #define MCF_SCM_BMT_BMT_256 (0x00000002) #define MCF_SCM_BMT_BMT_128 (0x00000003) #define MCF_SCM_BMT_BMT_64 (0x00000004) #define MCF_SCM_BMT_BMT_32 (0x00000005) #define MCF_SCM_BMT_BMT_16 (0x00000006) #define MCF_SCM_BMT_BMT_8 (0x00000007) /* Bit definitions and macros for MCF_SCM_PACRA */ #define MCF_SCM_PACRA_PACR2(x) (((x)&0x0000000F)<<20) #define MCF_SCM_PACRA_PACR1(x) (((x)&0x0000000F)<<24) #define MCF_SCM_PACRA_PACR0(x) (((x)&0x0000000F)<<28) #define MCF_SCM_PACRA_PACR_SP (0x4) #define MCF_SCM_PACRA_PACR_WP (0x2) #define MCF_SCM_PACRA_PACR_TP (0x1) /* Bit definitions and macros for MCF_SCM_PACRB */ #define MCF_SCM_PACRB_PACR12(x) (((x)&0x0000000F)<<12) #define MCF_SCM_PACRB_PACR8(x) (((x)&0x0000000F)<<28) /* Bit definitions and macros for MCF_SCM_PACRC */ #define MCF_SCM_PACRC_PACR23(x) (((x)&0x0000000F)<<0) #define MCF_SCM_PACRC_PACR22(x) (((x)&0x0000000F)<<4) #define MCF_SCM_PACRC_PACR21(x) (((x)&0x0000000F)<<8) #define MCF_SCM_PACRC_PACR19(x) (((x)&0x0000000F)<<16) #define MCF_SCM_PACRC_PACR18(x) (((x)&0x0000000F)<<20) #define MCF_SCM_PACRC_PACR17(x) (((x)&0x0000000F)<<24) #define MCF_SCM_PACRC_PACR16(x) (((x)&0x0000000F)<<28) /* Bit definitions and macros for MCF_SCM_PACRD */ #define MCF_SCM_PACRD_PACR31(x) (((x)&0x0000000F)<<0) #define MCF_SCM_PACRD_PACR30(x) (((x)&0x0000000F)<<4) #define MCF_SCM_PACRD_PACR29(x) (((x)&0x0000000F)<<8) #define MCF_SCM_PACRD_PACR28(x) (((x)&0x0000000F)<<12) #define MCF_SCM_PACRD_PACR26(x) (((x)&0x0000000F)<<20) #define MCF_SCM_PACRD_PACR25(x) (((x)&0x0000000F)<<24) #define MCF_SCM_PACRD_PACR24(x) (((x)&0x0000000F)<<28) /* Bit definitions and macros for MCF_SCM_PACRE */ #define MCF_SCM_PACRE_PACR38(x) (((x)&0x0000000F)<<4) #define MCF_SCM_PACRE_PACR37(x) (((x)&0x0000000F)<<8) #define MCF_SCM_PACRE_PACR36(x) (((x)&0x0000000F)<<12) #define MCF_SCM_PACRE_PACR35(x) (((x)&0x0000000F)<<16) #define MCF_SCM_PACRE_PACR34(x) (((x)&0x0000000F)<<20) #define MCF_SCM_PACRE_PACR33(x) (((x)&0x0000000F)<<24) #define MCF_SCM_PACRE_PACR32(x) (((x)&0x0000000F)<<28) /* Bit definitions and macros for MCF_SCM_PACRF */ #define MCF_SCM_PACRF_PACR47(x) (((x)&0x0000000F)<<0) #define MCF_SCM_PACRF_PACR46(x) (((x)&0x0000000F)<<4) #define MCF_SCM_PACRF_PACR45(x) (((x)&0x0000000F)<<8) #define MCF_SCM_PACRF_PACR44(x) (((x)&0x0000000F)<<12) #define MCF_SCM_PACRF_PACR43(x) (((x)&0x0000000F)<<16) #define MCF_SCM_PACRF_PACR42(x) (((x)&0x0000000F)<<20) #define MCF_SCM_PACRF_PACR41(x) (((x)&0x0000000F)<<24) #define MCF_SCM_PACRF_PACR40(x) (((x)&0x0000000F)<<28) /* Bit definitions and macros for MCF_SCM_PACRG */ #define MCF_SCM_PACRG_PACR48(x) (((x)&0x0000000F)<<28) /* Bit definitions and macros for MCF_SCM_PACRH */ #define MCF_SCM_PACRH_PACR58(x) (((x)&0x0000000F)<<20) #define MCF_SCM_PACRH_PACR57(x) (((x)&0x0000000F)<<24) #define MCF_SCM_PACRH_PACR56(x) (((x)&0x0000000F)<<28) /* Bit definitions and macros for MCF_SCM_CWCR */ #define MCF_SCM_CWCR_CWT(x) (((x)&0x001F)<<0) #define MCF_SCM_CWCR_CWRI(x) (((x)&0x0003)<<5) #define MCF_SCM_CWCR_CWE (0x0080) #define MCF_SCM_CWCR_CWR_WH (0x0100) #define MCF_SCM_CWCR_RO (0x8000) #define MCF_SCM_CWCR_CWRI_INT (0x0000) #define MCF_SCM_CWCR_CWRI_INT_THEN_RESET (0x0020) #define MCF_SCM_CWCR_CWRI_RESET (0x0040) #define MCF_SCM_CWCR_CWRI_WINDOW (0x0060) /* Bit definitions and macros for MCF_SCM_CWSR */ #define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0) /* Bit definitions and macros for MCF_SCM_CWIR */ #define MCF_SCM_CWIR_CWIC (0x01) #define MCF_SCM_CWIR_CFEI (0x02) /* Bit definitions and macros for MCF_SCM_BCR */ #define MCF_SCM_BCR_S1 (0x00000002) #define MCF_SCM_BCR_S4 (0x00000010) #define MCF_SCM_BCR_S6 (0x00000040) #define MCF_SCM_BCR_S7 (0x00000080) #define MCF_SCM_BCR_GBW (0x00000100) #define MCF_SCM_BCR_GBR (0x00000200) /* Bit definitions and macros for MCF_SCM_CFADR */ #define MCF_SCM_CFADR_ADDR(x) (((x)&0xFFFFFFFF)<<0) /* Bit definitions and macros for MCF_SCM_CFIER */ #define MCF_SCM_CFIER_ECFEI (0x01) /* Bit definitions and macros for MCF_SCM_CFLOC */ #define MCF_SCM_CFLOC_LOC (0x80) /* Bit definitions and macros for MCF_SCM_CFATR */ #define MCF_SCM_CFATR_TYPE (0x01) #define MCF_SCM_CFATR_MODE (0x02) #define MCF_SCM_CFATR_CACHE (0x08) #define MCF_SCM_CFATR_SIZE(x) (((x)&0x07)<<4) #define MCF_SCM_CFATR_WRITE (0x80) /* Bit definitions and macros for MCF_SCM_CFDTR */ #define MCF_SCM_CFDTR_CFDTR(x) (((x)&0xFFFFFFFF)<<0) /********************************************************************* * * Message Digest Hardware Accelerator (MDHA) * *********************************************************************/ /* Register read/write macros */ #define MCF_MDHA_MDMR (*(vuint32*)(0xEC080000)) #define MCF_MDHA_MDCR (*(vuint32*)(0xEC080004)) #define MCF_MDHA_MDCMR (*(vuint32*)(0xEC080008)) #define MCF_MDHA_MDSR (*(vuint32*)(0xEC08000C)) #define MCF_MDHA_MDISR (*(vuint32*)(0xEC080010)) #define MCF_MDHA_MDIMR (*(vuint32*)(0xEC080014)) #define MCF_MDHA_MDDSR (*(vuint32*)(0xEC08001C)) #define MCF_MDHA_MDIN (*(vuint32*)(0xEC080020)) #define MCF_MDHA_MDA0 (*(vuint32*)(0xEC080030)) #define MCF_MDHA_MDB0 (*(vuint32*)(0xEC080034)) #define MCF_MDHA_MDC0 (*(vuint32*)(0xEC080038)) #define MCF_MDHA_MDD0 (*(vuint32*)(0xEC08003C)) #define MCF_MDHA_MDE0 (*(vuint32*)(0xEC080040)) #define MCF_MDHA_MDMDS (*(vuint32*)(0xEC080044)) #define MCF_MDHA_MDA1 (*(vuint32*)(0xEC080070)) #define MCF_MDHA_MDB1 (*(vuint32*)(0xEC080074)) #define MCF_MDHA_MDC1 (*(vuint32*)(0xEC080078)) #define MCF_MDHA_MDD1 (*(vuint32*)(0xEC08007C)) #define MCF_MDHA_MDE1 (*(vuint32*)(0xEC080080)) /* Bit definitions and macros for MCF_MDHA_MDMR */ #define MCF_MDHA_MDMR_ALG (0x00000001) #define MCF_MDHA_MDMR_PDATA (0x00000004) #define MCF_MDHA_MDMR_MAC(x) (((x)&0x00000003)<<3) #define MCF_MDHA_MDMR_INIT (0x00000020) #define MCF_MDHA_MDMR_IPAD (0x00000040) #define MCF_MDHA_MDMR_OPAD (0x00000080) #define MCF_MDHA_MDMR_SWAP (0x00000100) #define MCF_MDHA_MDMR_MACFULL (0x00000200) #define MCF_MDHA_MDMR_SSL (0x00000400) /* Bit definitions and macros for MCF_MDHA_MDCR */ #define MCF_MDHA_MDCR_IE (0x00000001) #define MCF_MDHA_MDCR_DMA (0x00000002) #define MCF_MDHA_MDCR_ENDIAN (0x00000004) #define MCF_MDHA_MDCR_DMAL(x) (((x)&0x0000001F)<<16) /* Bit definitions and macros for MCF_MDHA_MDCMR */ #define MCF_MDHA_MDCMR_SWR (0x00000001) #define MCF_MDHA_MDCMR_RI (0x00000002) #define MCF_MDHA_MDCMR_CI (0x00000004) #define MCF_MDHA_MDCMR_GO (0x00000008) /* Bit definitions and macros for MCF_MDHA_MDSR */ #define MCF_MDHA_MDSR_INT (0x00000001) #define MCF_MDHA_MDSR_DONE (0x00000002) #define MCF_MDHA_MDSR_ERR (0x00000004) #define MCF_MDHA_MDSR_RD (0x00000008) #define MCF_MDHA_MDSR_BUSY (0x00000010) #define MCF_MDHA_MDSR_END (0x00000020) #define MCF_MDHA_MDSR_HSH (0x00000040) #define MCF_MDHA_MDSR_GNW (0x00000080) #define MCF_MDHA_MDSR_FS(x) (((x)&0x00000007)<<8) #define MCF_MDHA_MDSR_APD(x) (((x)&0x00000007)<<13) #define MCF_MDHA_MDSR_IFL(x) (((x)&0x000000FF)<<16) /* Bit definitions and macros for MCF_MDHA_MDISR */ #define MCF_MDHA_MDISR_IFO (0x00000001) #define MCF_MDHA_MDISR_NON (0x00000004) #define MCF_MDHA_MDISR_IME (0x00000010) #define MCF_MDHA_MDISR_IDS (0x00000020) #define MCF_MDHA_MDISR_RMDP (0x00000080) #define MCF_MDHA_MDISR_ERE (0x00000100) #define MCF_MDHA_MDISR_GTDS (0x00000200) /* Bit definitions and macros for MCF_MDHA_MDIMR */ #define MCF_MDHA_MDIMR_IFO (0x00000001) #define MCF_MDHA_MDIMR_NON (0x00000004) #define MCF_MDHA_MDIMR_IME (0x00000010) #define MCF_MDHA_MDIMR_IDS (0x00000020) #define MCF_MDHA_MDIMR_RMDP (0x00000080) #define MCF_MDHA_MDIMR_ERE (0x00000100) #define MCF_MDHA_MDIMR_GTDS (0x00000200) /* Bit definitions and macros for MCF_MDHA_MDDSR */ #define MCF_MDHA_MDDSR_DATASIZE(x) (((x)&0x1FFFFFFF)<<0) /* Bit definitions and macros for MCF_MDHA_MDIN */ #define MCF_MDHA_MDIN_DATAIN(x) (((x)&0xFFFFFFFF)<<0) /* Bit definitions and macros for MCF_MDHA_MDA0 */ #define MCF_MDHA_MDA0_DATA(x) (((x)&0xFFFFFFFF)<<0) /* Bit definitions and macros for MCF_MDHA_MDB0 */ #define MCF_MDHA_MDB0_DATA(x) (((x)&0xFFFFFFFF)<<0) /* Bit definitions and macros for MCF_MDHA_MDC0 */ #define MCF_MDHA_MDC0_DATA(x) (((x)&0xFFFFFFFF)<<0) /* Bit definitions and macros for MCF_MDHA_MDD0 */ #define MCF_MDHA_MDD0_DATA(x) (((x)&0xFFFFFFFF)<<0) /* Bit definitions and macros for MCF_MDHA_MDE0 */ #define MCF_MDHA_MDE0_DATA(x) (((x)&0xFFFFFFFF)<<0) /* Bit definitions and macros for MCF_MDHA_MDMDS */ #define MCF_MDHA_MDMDS_DATASIZE(x) (((x)&0xFFFFFFFF)<<0) /* Bit definitions and macros for MCF_MDHA_MDA1 */ #define MCF_MDHA_MDA1_DATA(x) (((x)&0xFFFFFFFF)<<0) /* Bit definitions and macros for MCF_MDHA_MDB1 */ #define MCF_MDHA_MDB1_DATA(x) (((x)&0xFFFFFFFF)<<0) /* Bit definitions and macros for MCF_MDHA_MDC1 */ #define MCF_MDHA_MDC1_DATA(x) (((x)&0xFFFFFFFF)<<0) /* Bit definitions and macros for MCF_MDHA_MDD1 */ #define MCF_MDHA_MDD1_DATA(x) (((x)&0xFFFFFFFF)<<0) /* Bit definitions and macros for MCF_MDHA_MDE1 */ #define MCF_MDHA_MDE1_DATA(x) (((x)&0xFFFFFFFF)<<0) /********************************************************************* * * Symmetric Key Hardware Accelerator (SKHA) * *********************************************************************/ /* Register read/write macros */ #define MCF_SKHA_SKMR (*(vuint32*)(0xEC084000)) #define MCF_SKHA_SKCR (*(vuint32*)(0xEC084004)) #define MCF_SKHA_SKCMR (*(vuint32*)(0xEC084008)) #define MCF_SKHA_SKSR (*(vuint32*)(0xEC08400C)) #define MCF_SKHA_SKISR (*(vuint32*)(0xEC084010)) #define MCF_SKHA_SKIMR (*(vuint32*)(0xEC084014)) #define MCF_SKHA_SKKSR (*(vuint32*)(0xEC084018)) #define MCF_SKHA_SKDSR (*(vuint32*)(0xEC08401C)) #define MCF_SKHA_SKIN (*(vuint32*)(0xEC084020)) #define MCF_SKHA_SKOUT (*(vuint32*)(0xEC084024)) #define MCF_SKHA_SKK0 (*(vuint32*)(0xEC084030)) #define MCF_SKHA_SKK1 (*(vuint32*)(0xEC084034)) #define MCF_SKHA_SKK2 (*(vuint32*)(0xEC084038)) #define MCF_SKHA_SKK3 (*(vuint32*)(0xEC08403C)) #define MCF_SKHA_SKK4 (*(vuint32*)(0xEC084040)) #define MCF_SKHA_SKK5 (*(vuint32*)(0xEC084044)) #define MCF_SKHA_SKK(x) (*(vuint32*)(0xEC084030+((x)*0x004))) #define MCF_SKHA_SKC0 (*(vuint32*)(0xEC084070)) #define MCF_SKHA_SKC1 (*(vuint32*)(0xEC084074)) #define MCF_SKHA_SKC2 (*(vuint32*)(0xEC084078)) #define MCF_SKHA_SKC3 (*(vuint32*)(0xEC08407C)) #define MCF_SKHA_SKC4 (*(vuint32*)(0xEC084080)) #define MCF_SKHA_SKC5 (*(vuint32*)(0xEC084084)) #define MCF_SKHA_SKC6 (*(vuint32*)(0xEC084088)) #define MCF_SKHA_SKC7 (*(vuint32*)(0xEC08408C)) #define MCF_SKHA_SKC8 (*(vuint32*)(0xEC084090)) #define MCF_SKHA_SKC9 (*(vuint32*)(0xEC084094)) #define MCF_SKHA_SKC10 (*(vuint32*)(0xEC084098)) #define MCF_SKHA_SKC11 (*(vuint32*)(0xEC08409C)) #define MCF_SKHA_SKC(x) (*(vuint32*)(0xEC084070+((x)*0x004))) /* Bit definitions and macros for MCF_SKHA_SKMR */ #define MCF_SKHA_SKMR_ALG(x) (((x)&0x00000003)<<0) #define MCF_SKHA_SKMR_DIR (0x00000004) #define MCF_SKHA_SKMR_CM(x) (((x)&0x00000003)<<3) #define MCF_SKHA_SKMR_DKP (0x00000100) #define MCF_SKHA_SKMR_CTRM(x) (((x)&0x0000000F)<<9) #define MCF_SKHA_SKMR_CM_ECB (0x00000000) #define MCF_SKHA_SKMR_CM_CBC (0x00000008) #define MCF_SKHA_SKMR_CM_CTR (0x00000018) #define MCF_SKHA_SKMR_DIR_DEC (0x00000000) #define MCF_SKHA_SKMR_DIR_ENC (0x00000004) #define MCF_SKHA_SKMR_ALG_AES (0x00000000) #define MCF_SKHA_SKMR_ALG_DES (0x00000001) #define MCF_SKHA_SKMR_ALG_TDES (0x00000002) /* Bit definitions and macros for MCF_SKHA_SKCR */ #define MCF_SKHA_SKCR_IE (0x00000001) #define MCF_SKHA_SKCR_IDMA (0x00000002) #define MCF_SKHA_SKCR_ODMA (0x00000004) #define MCF_SKHA_SKCR_ENDIAN (0x00000008) #define MCF_SKHA_SKCR_IDMAL(x) (((x)&0x0000003F)<<16) #define MCF_SKHA_SKCR_ODMAL(x) (((x)&0x0000003F)<<24) /* Bit definitions and macros for MCF_SKHA_SKCMR */ #define MCF_SKHA_SKCMR_SWR (0x00000001) #define MCF_SKHA_SKCMR_RI (0x00000002) #define MCF_SKHA_SKCMR_CI (0x00000004) #define MCF_SKHA_SKCMR_GO (0x00000008) /* Bit definitions and macros for MCF_SKHA_SKSR */ #define MCF_SKHA_SKSR_INT (0x00000001) #define MCF_SKHA_SKSR_DONE (0x00000002) #define MCF_SKHA_SKSR_ERR (0x00000004) #define MCF_SKHA_SKSR_RD (0x00000008) #define MCF_SKHA_SKSR_BUSY (0x00000010) #define MCF_SKHA_SKSR_IFL(x) (((x)&0x000000FF)<<16) #define MCF_SKHA_SKSR_OFL(x) (((x)&0x000000FF)<<24) /* Bit definitions and macros for MCF_SKHA_SKISR */ #define MCF_SKHA_SKISR_IFO (0x00000001) #define MCF_SKHA_SKISR_OFU (0x00000002) #define MCF_SKHA_SKISR_NEIF (0x00000004) #define MCF_SKHA_SKISR_NEOF (0x00000008) #define MCF_SKHA_SKISR_IME (0x00000010) #define MCF_SKHA_SKISR_DSE (0x00000020) #define MCF_SKHA_SKISR_KSE (0x00000040) #define MCF_SKHA_SKISR_RMDP (0x00000080) #define MCF_SKHA_SKISR_ERE (0x00000100) #define MCF_SKHA_SKISR_KPE (0x00000200) #define MCF_SKHA_SKISR_KRE (0x00000400) #define MCF_SKHA_SKISR_DRL (0x00000800) /* Bit definitions and macros for MCF_SKHA_SKIMR */ #define MCF_SKHA_SKIMR_IFO (0x00000001) #define MCF_SKHA_SKIMR_OFU (0x00000002) #define MCF_SKHA_SKIMR_NEIF (0x00000004) #define MCF_SKHA_SKIMR_NEOF (0x00000008) #define MCF_SKHA_SKIMR_IME (0x00000010) #define MCF_SKHA_SKIMR_DSE (0x00000020) #define MCF_SKHA_SKIMR_KSE (0x00000040) #define MCF_SKHA_SKIMR_RMDP (0x00000080) #define MCF_SKHA_SKIMR_ERE (0x00000100) #define MCF_SKHA_SKIMR_KPE (0x00000200) #define MCF_SKHA_SKIMR_KRE (0x00000400) #define MCF_SKHA_SKIMR_DRL (0x00000800) /* Bit definitions and macros for MCF_SKHA_SKKSR */ #define MCF_SKHA_SKKSR_KEYSIZE(x) (((x)&0x0000003F)<<0) /* Bit definitions and macros for MCF_SKHA_SKDSR */ #define MCF_SKHA_SKDSR_DATASIZE(x) (((x)&0xFFFFFFFF)<<0) /* Bit definitions and macros for MCF_SKHA_SKIN */ #define MCF_SKHA_SKIN_DATAIN(x) (((x)&0xFFFFFFFF)<<0) /* Bit definitions and macros for MCF_SKHA_SKOUT */ #define MCF_SKHA_SKOUT_DATAOUT(x) (((x)&0xFFFFFFFF)<<0) /* Bit definitions and macros for MCF_SKHA_SKK */ #define MCF_SKHA_SKK_KEY(x) (((x)&0xFFFFFFFF)<<0) /* Bit definitions and macros for MCF_SKHA_SKC */ #define MCF_SKHA_SKC_CONTEXT(x) (((x)&0xFFFFFFFF)<<0) /********************************************************************* * * Random Number Generator (RNG) * *********************************************************************/ /* Register read/write macros */ #define MCF_RNG_RNGCR (*(vuint32*)(0xEC088000)) #define MCF_RNG_RNGSR (*(vuint32*)(0xEC088004)) #define MCF_RNG_RNGER (*(vuint32*)(0xEC088008)) #define MCF_RNG_RNGOUT (*(vuint32*)(0xEC08800C)) /* Bit definitions and macros for MCF_RNG_RNGCR */ #define MCF_RNG_RNGCR_GO (0x00000001) #define MCF_RNG_RNGCR_HA (0x00000002) #define MCF_RNG_RNGCR_IM (0x00000004) #define MCF_RNG_RNGCR_CI (0x00000008) /* Bit definitions and macros for MCF_RNG_RNGSR */ #define MCF_RNG_RNGSR_SV (0x00000001) #define MCF_RNG_RNGSR_LRS (0x00000002) #define MCF_RNG_RNGSR_FUF (0x00000004) #define MCF_RNG_RNGSR_EI (0x00000008) #define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8) #define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16) /* Bit definitions and macros for MCF_RNG_RNGER */ #define MCF_RNG_RNGER_ENTROPY(x) (((x)&0xFFFFFFFF)<<0) /* Bit definitions and macros for MCF_RNG_RNGOUT */ #define MCF_RNG_RNGOUT_OUTPUT(x) (((x)&0xFFFFFFFF)<<0) /********************************************************************* * * Power Management Module (PMM) * *********************************************************************/ /* Register read/write macros */ #define MCF_PMM_WCR (*(vuint8 *)(0xFC040013)) #define MCF_PMM_PPMSR0 (*(vuint8 *)(0xFC04002C)) #define MCF_PMM_PPMSR1 (*(vuint8 *)(0xFC04002E)) #define MCF_PMM_PPMCR0 (*(vuint8 *)(0xFC04002D)) #define MCF_PMM_PPMCR1 (*(vuint8 *)(0xFC04002F)) #define MCF_PMM_PPMHR0 (*(vuint32*)(0xFC040030)) #define MCF_PMM_PPMLR0 (*(vuint32*)(0xFC040034)) #define MCF_PMM_PPMHR1 (*(vuint32*)(0xFC040038)) #define MCF_PMM_LPCR (*(vuint8 *)(0xFC0A0007)) /* Bit definitions and macros for MCF_PMM_WCR */ #define MCF_PMM_WCR_PRILVL(x) (((x)&0x07)<<0) #define MCF_PMM_WCR_ENBWCR (0x80) /* Bit definitions and macros for MCF_PMM_PPMSR */ #define MCF_PMM_PPMSR_SMCD(x) (((x)&0x3F)<<0) #define MCF_PMM_PPMSR_SAMCD (0x40) /* Bit definitions and macros for MCF_PMM_PPMCR */ #define MCF_PMM_PPMCR_CMCD(x) (((x)&0x3F)<<0) #define MCF_PMM_PPMCR_CAMCD (0x40) /* Bit definitions and macros for MCF_PMM_PPMHR0 */ #define MCF_PMM_PPMHR0_CD32 (0x00000001) #define MCF_PMM_PPMHR0_CD33 (0x00000002) #define MCF_PMM_PPMHR0_CD34 (0x00000004) #define MCF_PMM_PPMHR0_CD35 (0x00000008) #define MCF_PMM_PPMHR0_CD36 (0x00000010) #define MCF_PMM_PPMHR0_CD37 (0x00000020) #define MCF_PMM_PPMHR0_CD38 (0x00000040) #define MCF_PMM_PPMHR0_CD40 (0x00000100) #define MCF_PMM_PPMHR0_CD41 (0x00000200) #define MCF_PMM_PPMHR0_CD42 (0x00000400) #define MCF_PMM_PPMHR0_CD43 (0x00000800) #define MCF_PMM_PPMHR0_CD44 (0x00001000) #define MCF_PMM_PPMHR0_CD45 (0x00002000) #define MCF_PMM_PPMHR0_CD46 (0x00004000) #define MCF_PMM_PPMHR0_CD47 (0x00008000) #define MCF_PMM_PPMHR0_CD48 (0x00010000) /* Bit definitions and macros for MCF_PMM_PPMLR0 */ #define MCF_PMM_PPMLR0_CD2 (0x00000004) #define MCF_PMM_PPMLR0_CD8 (0x00000100) #define MCF_PMM_PPMLR0_CD12 (0x00001000) #define MCF_PMM_PPMLR0_CD17 (0x00020000) #define MCF_PMM_PPMLR0_CD18 (0x00040000) #define MCF_PMM_PPMLR0_CD19 (0x00080000) #define MCF_PMM_PPMLR0_CD21 (0x00200000) #define MCF_PMM_PPMLR0_CD22 (0x00400000) #define MCF_PMM_PPMLR0_CD23 (0x00800000) #define MCF_PMM_PPMLR0_CD24 (0x01000000) #define MCF_PMM_PPMLR0_CD25 (0x02000000) #define MCF_PMM_PPMLR0_CD26 (0x04000000) #define MCF_PMM_PPMLR0_CD28 (0x10000000) #define MCF_PMM_PPMLR0_CD29 (0x20000000) #define MCF_PMM_PPMLR0_CD30 (0x40000000) #define MCF_PMM_PPMLR0_CD31 (0x80000000) /* Bit definitions and macros for MCF_PMM_PPMHR1 */ #define MCF_PMM_PPMHR1_CD32 (0x00000001) #define MCF_PMM_PPMHR1_CD33 (0x00000002) #define MCF_PMM_PPMHR1_CD34 (0x00000004) /* Bit definitions and macros for MCF_PMM_LPCR */ #define MCF_PMM_LPCR_STPMD(x) (((x)&0x03)<<3) #define MCF_PMM_LPCR_FWKUP (0x20) #define MCF_PMM_LPCR_LPMD(x) (((x)&0x03)<<6) #define MCF_PMM_LPCR_LPMD_RUN (0x00) #define MCF_PMM_LPCR_LPMD_DOZE (0x40) #define MCF_PMM_LPCR_LPMD_WAIT (0x80) #define MCF_PMM_LPCR_LPMD_STOP (0xC0) #define MCF_PMM_LPCR_STPMD_SYS_DISABLED (0x00) #define MCF_PMM_LPCR_STPMD_SYS_BUSCLK_DISABLED (0x04) #define MCF_PMM_LPCR_STPMD_ONLY_OSC_ENABLED (0x08) #define MCF_PMM_LPCR_STPMD_ALL_DISABLED (0x0C) /********************************************************************* * * Cross-bar switch (XBS) * *********************************************************************/ /* Register read/write macros */ #define MCF_XBS_PRS1 (*(vuint32*)(0xFC004100)) #define MCF_XBS_PRS2 (*(vuint32*)(0xFC004200)) #define MCF_XBS_PRS3 (*(vuint32*)(0xFC004300)) #define MCF_XBS_PRS4 (*(vuint32*)(0xFC004400)) #define MCF_XBS_PRS5 (*(vuint32*)(0xFC004500)) #define MCF_XBS_PRS6 (*(vuint32*)(0xFC004600)) #define MCF_XBS_PRS7 (*(vuint32*)(0xFC004700)) #define MCF_XBS_PRS(x) (*(vuint32*)(0xFC004100+((x-1)*0x100))) #define MCF_XBS_CRS1 (*(vuint32*)(0xFC004110)) #define MCF_XBS_CRS2 (*(vuint32*)(0xFC004210)) #define MCF_XBS_CRS3 (*(vuint32*)(0xFC004310)) #define MCF_XBS_CRS4 (*(vuint32*)(0xFC004410)) #define MCF_XBS_CRS5 (*(vuint32*)(0xFC004510)) #define MCF_XBS_CRS6 (*(vuint32*)(0xFC004610)) #define MCF_XBS_CRS7 (*(vuint32*)(0xFC004710)) #define MCF_XBS_CRS(x) (*(vuint32*)(0xFC004110+((x-1)*0x100))) /* Bit definitions and macros for MCF_XBS_PRS */ #define MCF_XBS_PRS_M0(x) (((x)&0x00000007)<<0) #define MCF_XBS_PRS_M1(x) (((x)&0x00000007)<<4) #define MCF_XBS_PRS_M2(x) (((x)&0x00000007)<<8) #define MCF_XBS_PRS_M4(x) (((x)&0x00000007)<<16) #define MCF_XBS_PRS_M5(x) (((x)&0x00000007)<<20) #define MCF_XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* Bit definitions and macros for MCF_XBS_CRS */ #define MCF_XBS_CRS_PARK(x) (((x)&0x00000007)<<0) #define MCF_XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) #define MCF_XBS_CRS_ARB (0x00000100) #define MCF_XBS_CRS_RO (0x80000000) #define MCF_XBS_CRS_PCTL_PARK_FIELD (0x00000000) #define MCF_XBS_CRS_PCTL_PARK_ON_LAST (0x00000010) #define MCF_XBS_CRS_PCTL_PARK_NO_MASTER (0x00000020) #define MCF_XBS_CRS_PCTL_PARK_CORE (0x00000000) #define MCF_XBS_CRS_PCTL_PARK_EDMA (0x00000001) #define MCF_XBS_CRS_PCTL_PARK_FEC (0x00000002) /********************************************************************* * * FlexBus Chip Selects (FBCS) * *********************************************************************/ /* Register read/write macros */ #define MCF_FBCS0_CSAR (*(vuint32*)(0xFC008000)) #define MCF_FBCS0_CSMR (*(vuint32*)(0xFC008004)) #define MCF_FBCS0_CSCR (*(vuint32*)(0xFC008008)) #define MCF_FBCS1_CSAR (*(vuint32*)(0xFC00800C)) #define MCF_FBCS1_CSMR (*(vuint32*)(0xFC008010)) #define MCF_FBCS1_CSCR (*(vuint32*)(0xFC008014)) #define MCF_FBCS2_CSAR (*(vuint32*)(0xFC008018)) #define MCF_FBCS2_CSMR (*(vuint32*)(0xFC00801C)) #define MCF_FBCS2_CSCR (*(vuint32*)(0xFC008020)) #define MCF_FBCS3_CSAR (*(vuint32*)(0xFC008024)) #define MCF_FBCS3_CSMR (*(vuint32*)(0xFC008028)) #define MCF_FBCS3_CSCR (*(vuint32*)(0xFC00802C)) #define MCF_FBCS4_CSAR (*(vuint32*)(0xFC008030)) #define MCF_FBCS4_CSMR (*(vuint32*)(0xFC008034)) #define MCF_FBCS4_CSCR (*(vuint32*)(0xFC008038)) #define MCF_FBCS5_CSAR (*(vuint32*)(0xFC00803C)) #define MCF_FBCS5_CSMR (*(vuint32*)(0xFC008040)) #define MCF_FBCS5_CSCR (*(vuint32*)(0xFC008044)) #define MCF_FBCS_CSAR(x) (*(vuint32*)(0xFC008000+((x)*0x00C))) #define MCF_FBCS_CSMR(x) (*(vuint32*)(0xFC008004+((x)*0x00C))) #define MCF_FBCS_CSCR(x) (*(vuint32*)(0xFC008008+((x)*0x00C))) /* Bit definitions and macros for MCF_FBCS_CSAR */ #define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) /* Bit definitions and macros for MCF_FBCS_CSMR */ #define MCF_FBCS_CSMR_V (0x00000001) #define MCF_FBCS_CSMR_WP (0x00000100) #define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) #define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) #define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) #define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) #define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) #define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) #define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000) #define MCF_FBCS_CSMR_BAM_128M (0x07FF0000) #define MCF_FBCS_CSMR_BAM_64M (0x03FF0000) #define MCF_FBCS_CSMR_BAM_32M (0x01FF0000) #define MCF_FBCS_CSMR_BAM_16M (0x00FF0000) #define MCF_FBCS_CSMR_BAM_8M (0x007F0000) #define MCF_FBCS_CSMR_BAM_4M (0x003F0000) #define MCF_FBCS_CSMR_BAM_2M (0x001F0000) #define MCF_FBCS_CSMR_BAM_1M (0x000F0000) #define MCF_FBCS_CSMR_BAM_1024K (0x000F0000) #define MCF_FBCS_CSMR_BAM_512K (0x00070000) #define MCF_FBCS_CSMR_BAM_256K (0x00030000) #define MCF_FBCS_CSMR_BAM_128K (0x00010000) #define MCF_FBCS_CSMR_BAM_64K (0x00000000) /* Bit definitions and macros for MCF_FBCS_CSCR */ #define MCF_FBCS_CSCR_BSTW (0x00000008) #define MCF_FBCS_CSCR_BSTR (0x00000010) #define MCF_FBCS_CSCR_BEM (0x00000020) #define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) #define MCF_FBCS_CSCR_AA (0x00000100) #define MCF_FBCS_CSCR_SBM (0x00000200) #define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) #define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) #define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) #define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) #define MCF_FBCS_CSCR_SWSEN (0x00800000) #define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) #define MCF_FBCS_CSCR_PS_8 (0x00000040) #define MCF_FBCS_CSCR_PS_16 (0x00000080) #define MCF_FBCS_CSCR_PS_32 (0x00000000) /********************************************************************* * * FlexCAN Module (CAN) * *********************************************************************/ /* Register read/write macros */ #define MCF_CAN_CANMCR (*(vuint32*)(0xFC020000)) #define MCF_CAN_CANCTRL (*(vuint32*)(0xFC020004)) #define MCF_CAN_TIMER (*(vuint32*)(0xFC020008)) #define MCF_CAN_RXGMASK (*(vuint32*)(0xFC020010)) #define MCF_CAN_RX14MASK (*(vuint32*)(0xFC020014)) #define MCF_CAN_RX15MASK (*(vuint32*)(0xFC020018)) #define MCF_CAN_ERRCNT (*(vuint32*)(0xFC02001C)) #define MCF_CAN_ERRSTAT (*(vuint32*)(0xFC020020)) #define MCF_CAN_IMASK (*(vuint32*)(0xFC020028)) #define MCF_CAN_IFLAG (*(vuint32*)(0xFC020030)) /* Bit definitions and macros for MCF_CAN_CANMCR */ #define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) #define MCF_CAN_CANMCR_LPMACK (0x00100000) #define MCF_CAN_CANMCR_SUPV (0x00800000) #define MCF_CAN_CANMCR_FRZACK (0x01000000) #define MCF_CAN_CANMCR_SOFTRST (0x02000000) #define MCF_CAN_CANMCR_NOTRDY (0x08000000) #define MCF_CAN_CANMCR_HALT (0x10000000) #define MCF_CAN_CANMCR_FRZ (0x40000000) #define MCF_CAN_CANMCR_MDIS (0x80000000) /* Bit definitions and macros for MCF_CAN_CANCTRL */ #define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) #define MCF_CAN_CANCTRL_LOM (0x00000008) #define MCF_CAN_CANCTRL_LBUF (0x00000010) #define MCF_CAN_CANCTRL_TSYNC (0x00000020) #define MCF_CAN_CANCTRL_BOFFREC (0x00000040) #define MCF_CAN_CANCTRL_SAMP (0x00000080) #define MCF_CAN_CANCTRL_LPB (0x00001000) #define MCF_CAN_CANCTRL_CLKSRC (0x00002000) #define MCF_CAN_CANCTRL_ERRMSK (0x00004000) #define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) #define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) #define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) #define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) #define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) /* Bit definitions and macros for MCF_CAN_TIMER */ #define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) /* Bit definitions and macros for MCF_CAN_RXGMASK */ #define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) /* Bit definitions and macros for MCF_CAN_RX14MASK */ #define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) /* Bit definitions and macros for MCF_CAN_RX15MASK */ #define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) /* Bit definitions and macros for MCF_CAN_ERRCNT */ #define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) #define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) /* Bit definitions and macros for MCF_CAN_ERRSTAT */ #define MCF_CAN_ERRSTAT_WAKINT (0x00000001) #define MCF_CAN_ERRSTAT_ERRINT (0x00000002) #define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) #define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) #define MCF_CAN_ERRSTAT_TXRX (0x00000040) #define MCF_CAN_ERRSTAT_IDLE (0x00000080) #define MCF_CAN_ERRSTAT_RXWRN (0x00000100) #define MCF_CAN_ERRSTAT_TXWRN (0x00000200) #define MCF_CAN_ERRSTAT_STFERR (0x00000400) #define MCF_CAN_ERRSTAT_FRMERR (0x00000800) #define MCF_CAN_ERRSTAT_CRCERR (0x00001000) #define MCF_CAN_ERRSTAT_ACKERR (0x00002000) #define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) #define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) #define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) #define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) /* Bit definitions and macros for MCF_CAN_IMASK */ #define MCF_CAN_IMASK_BUF0M (0x00000001) #define MCF_CAN_IMASK_BUF1M (0x00000002) #define MCF_CAN_IMASK_BUF2M (0x00000004) #define MCF_CAN_IMASK_BUF3M (0x00000008) #define MCF_CAN_IMASK_BUF4M (0x00000010) #define MCF_CAN_IMASK_BUF5M (0x00000020) #define MCF_CAN_IMASK_BUF6M (0x00000040) #define MCF_CAN_IMASK_BUF7M (0x00000080) #define MCF_CAN_IMASK_BUF8M (0x00000100) #define MCF_CAN_IMASK_BUF9M (0x00000200) #define MCF_CAN_IMASK_BUF10M (0x00000400) #define MCF_CAN_IMASK_BUF11M (0x00000800) #define MCF_CAN_IMASK_BUF12M (0x00001000) #define MCF_CAN_IMASK_BUF13M (0x00002000) #define MCF_CAN_IMASK_BUF14M (0x00004000) #define MCF_CAN_IMASK_BUF15M (0x00008000) #define MCF_CAN_IMASK_BUF(x) (1<