source: rtems/c/src/lib/libcpu/m68k/mcf532x/cache/cachepd.c @ 92a8cee

4.115
Last change on this file since 92a8cee was 92a8cee, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 13, 2014 at 9:55:01 PM

libcpu/m68k/mcf532x/cache/cachepd.c: Fix warnings

  • Property mode set to 100644
File size: 3.0 KB
Line 
1/**
2 *  @file
3 *
4 *  Cache Management Support Routines for the MCF532x
5 */
6
7#include <rtems.h>
8#include <mcf532x/mcf532x.h>
9#include "cache_.h"
10
11#define m68k_set_cacr(_cacr) \
12  __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr))
13
14/*
15 * Read/write copy of common cache
16 *  Default cache mode is *disabled* (cache only ACRx areas)
17 *  Allow CPUSHL to invalidate a cache line
18 *  Enable store buffer
19 */
20static uint32_t cacr_mode = MCF_CACR_ESB |
21                              MCF_CACR_DCM(3);
22
23/*
24 * Cannot be frozen
25 */
26void _CPU_cache_freeze_data(void)
27{
28}
29
30void _CPU_cache_unfreeze_data(void)
31{
32}
33
34void _CPU_cache_freeze_instruction(void)
35{
36}
37
38void _CPU_cache_unfreeze_instruction(void)
39{
40}
41
42void _CPU_cache_flush_1_data_line(const void *d_addr)
43{
44  register unsigned long adr = (((unsigned long) d_addr >> 4) & 0xff) << 4;
45
46  __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
47  adr += 1;
48  __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
49  adr += 1;
50  __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
51  adr += 1;
52  __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
53}
54
55void _CPU_cache_flush_entire_data(void)
56{
57  register unsigned long set, adr;
58
59  for(set = 0; set < 256; ++set) {
60    adr = (set << 4);
61    __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
62    adr += 1;
63    __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
64    adr += 1;
65    __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
66    adr += 1;
67    __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
68  }
69}
70
71void _CPU_cache_enable_instruction(void)
72{
73  rtems_interrupt_level level;
74
75  rtems_interrupt_disable(level);
76  if(!(cacr_mode & MCF_CACR_CENB))
77  {
78    cacr_mode |= MCF_CACR_CENB;
79    m68k_set_cacr(cacr_mode);
80  }
81  rtems_interrupt_enable(level);
82}
83
84void _CPU_cache_disable_instruction(void)
85{
86  rtems_interrupt_level level;
87
88  rtems_interrupt_disable(level);
89  if((cacr_mode & MCF_CACR_CENB))
90  {
91    cacr_mode &= ~MCF_CACR_CENB;
92    m68k_set_cacr(cacr_mode);
93  }
94  rtems_interrupt_enable(level);
95}
96
97void _CPU_cache_invalidate_entire_instruction(void)
98{
99  m68k_set_cacr(cacr_mode | MCF_CACR_CINVA);
100}
101
102void _CPU_cache_invalidate_1_instruction_line(const void *addr)
103{
104  register unsigned long adr = (((unsigned long) addr >> 4) & 0xff) << 4;
105
106  __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
107  adr += 1;
108  __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
109  adr += 1;
110  __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
111  adr += 1;
112  __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
113}
114
115void _CPU_cache_enable_data(void)
116{
117  /*
118   * The 532x has a unified data and instruction cache, so we call through
119   * to enable instruction.
120   */
121  _CPU_cache_enable_instruction();
122}
123
124void _CPU_cache_disable_data(void)
125{
126  /*
127   * The 532x has a unified data and instruction cache, so we call through
128   * to disable instruction.
129   */
130  _CPU_cache_disable_instruction();
131}
132
133void _CPU_cache_invalidate_entire_data(void)
134{
135  _CPU_cache_invalidate_entire_instruction();
136}
137
138void _CPU_cache_invalidate_1_data_line(const void *addr)
139{
140  _CPU_cache_invalidate_1_instruction_line(addr);
141}
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