[8fbe2e6] | 1 | /** |
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| 2 | * @file |
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[3cfd520] | 3 | * |
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| 4 | * This module initializes TIMER 2 for on the MCF5272 for benchmarks. |
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[8fbe2e6] | 5 | */ |
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| 6 | |
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| 7 | /* |
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[3cfd520] | 8 | * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia |
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| 9 | * Author: Victor V. Vengerov <vvv@oktet.ru> |
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| 10 | * |
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| 11 | * Based on work: |
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| 12 | * Author: |
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| 13 | * David Fiddes, D.J@fiddes.surfaid.org |
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| 14 | * http://www.calm.hw.ac.uk/davidf/coldfire/ |
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| 15 | * |
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| 16 | * COPYRIGHT (c) 1989-1998. |
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| 17 | * On-Line Applications Research Corporation (OAR). |
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| 18 | * |
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| 19 | * The license and distribution terms for this file may be |
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| 20 | * found in the file LICENSE in this distribution or at |
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[c499856] | 21 | * http://www.rtems.org/license/LICENSE. |
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[3cfd520] | 22 | */ |
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| 23 | |
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| 24 | #include <rtems.h> |
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| 25 | #include <bsp.h> |
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| 26 | #include <mcf5272/mcf5272.h> |
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[8fbe2e6] | 27 | #include <rtems/btimer.h> |
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[3cfd520] | 28 | |
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[023f1dd9] | 29 | #define TRR2_VAL 65530 |
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[3cfd520] | 30 | |
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[ee5769ad] | 31 | uint32_t Timer_interrupts; |
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[3cfd520] | 32 | |
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[3551166d] | 33 | bool benchmark_timer_find_average_overhead; |
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[3cfd520] | 34 | |
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| 35 | /* External assembler interrupt handler routine */ |
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| 36 | extern rtems_isr timerisr(rtems_vector_number vector); |
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| 37 | |
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| 38 | |
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[a5cd2271] | 39 | /* benchmark_timer_initialize -- |
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[3cfd520] | 40 | * Initialize timer 2 for accurate time measurement. |
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| 41 | * |
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| 42 | * PARAMETERS: |
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| 43 | * none |
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| 44 | * |
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| 45 | * RETURNS: |
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| 46 | * none |
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| 47 | */ |
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| 48 | void |
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[a5cd2271] | 49 | benchmark_timer_initialize(void) |
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[3cfd520] | 50 | { |
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[ee5769ad] | 51 | uint32_t icr; |
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[3cfd520] | 52 | /* Catch timer2 interrupts */ |
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| 53 | set_vector(timerisr, BSP_INTVEC_TMR2, 0); |
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[023f1dd9] | 54 | |
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[3cfd520] | 55 | /* Reset Timer */ |
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| 56 | g_timer_regs->tmr2 = MCF5272_TMR_RST; |
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| 57 | g_timer_regs->tmr2 = MCF5272_TMR_CLK_STOP; |
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| 58 | g_timer_regs->tmr2 = MCF5272_TMR_RST; |
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| 59 | g_timer_regs->tcn2 = 0; /* reset counter */ |
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| 60 | Timer_interrupts = 0; /* Clear timer ISR counter */ |
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| 61 | g_timer_regs->ter2 = MCF5272_TER_REF | MCF5272_TER_CAP; |
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| 62 | g_timer_regs->trr2 = TRR2_VAL -1 ; |
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| 63 | |
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| 64 | |
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| 65 | /* Set Timer 2 prescaler so that it counts in microseconds */ |
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| 66 | g_timer_regs->tmr2 = ( |
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| 67 | (((BSP_SYSTEM_FREQUENCY / 1000000) - 1) << MCF5272_TMR_PS_SHIFT) | |
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| 68 | MCF5272_TMR_CE_DISABLE | |
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| 69 | MCF5272_TMR_ORI | |
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| 70 | MCF5272_TMR_FRR | |
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| 71 | MCF5272_TMR_CLK_MSTR | |
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| 72 | MCF5272_TMR_RST); |
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| 73 | |
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| 74 | /* Initialize interrupts for timer2 */ |
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| 75 | icr = g_intctrl_regs->icr1; |
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| 76 | icr = icr & ~(MCF5272_ICR1_TMR2_MASK | MCF5272_ICR1_TMR2_PI); |
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| 77 | icr |= (MCF5272_ICR1_TMR2_IPL(BSP_INTLVL_TMR2) | MCF5272_ICR1_TMR2_PI); |
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| 78 | g_intctrl_regs->icr1 = icr; |
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| 79 | |
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| 80 | } |
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| 81 | |
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| 82 | /* |
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[a5cd2271] | 83 | * The following controls the behavior of benchmark_timer_read(). |
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[3cfd520] | 84 | * |
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| 85 | * FIND_AVG_OVERHEAD * instructs the routine to return the "raw" count. |
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| 86 | * |
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| 87 | * AVG_OVEREHAD is the overhead for starting and stopping the timer. It |
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| 88 | * is usually deducted from the number returned. |
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| 89 | * |
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| 90 | * LEAST_VALID is the lowest number this routine should trust. Numbers |
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| 91 | * below this are "noise" and zero is returned. |
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| 92 | */ |
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| 93 | |
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| 94 | #define AVG_OVERHEAD 0 /* It typically takes 2.0 microseconds */ |
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| 95 | /* (Y countdowns) to start/stop the timer. */ |
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| 96 | /* This value is in microseconds. */ |
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| 97 | #define LEAST_VALID 1 /* Don't trust a clicks value lower than this */ |
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| 98 | |
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[a5cd2271] | 99 | /* benchmark_timer_read -- |
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[3cfd520] | 100 | * Read timer value in microsecond units since timer start. |
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| 101 | * |
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| 102 | * PARAMETERS: |
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| 103 | * none |
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| 104 | * |
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| 105 | * RETURNS: |
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| 106 | * number of microseconds since timer has been started |
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| 107 | */ |
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[8fbe2e6] | 108 | benchmark_timer_t |
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[a5cd2271] | 109 | benchmark_timer_read( void ) |
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[3cfd520] | 110 | { |
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[ee5769ad] | 111 | uint16_t clicks; |
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| 112 | uint32_t total; |
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[3cfd520] | 113 | |
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| 114 | /* |
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| 115 | * Read the timer and see how many clicks it has been since counter |
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| 116 | * rolled over. |
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| 117 | */ |
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| 118 | clicks = g_timer_regs->tcn2; |
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[023f1dd9] | 119 | |
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[3cfd520] | 120 | /* Stop Timer... */ |
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| 121 | g_timer_regs->tmr2 = MCF5272_TMR_CLK_STOP | MCF5272_TMR_RST; |
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| 122 | |
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| 123 | /* |
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[023f1dd9] | 124 | * Total is calculated by taking into account the number of timer |
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[3cfd520] | 125 | * overflow interrupts since the timer was initialized and clicks |
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| 126 | * since the last interrupts. |
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| 127 | */ |
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| 128 | |
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| 129 | total = (Timer_interrupts * TRR2_VAL) + clicks; |
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| 130 | |
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[a5cd2271] | 131 | if ( benchmark_timer_find_average_overhead == 1 ) |
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[3cfd520] | 132 | return total; /* in XXX microsecond units */ |
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| 133 | |
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| 134 | if ( total < LEAST_VALID ) |
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| 135 | return 0; /* below timer resolution */ |
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| 136 | |
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| 137 | /* |
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| 138 | * Return the count in microseconds |
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| 139 | */ |
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| 140 | return (total - AVG_OVERHEAD); |
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| 141 | } |
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| 142 | |
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[a5cd2271] | 143 | /* benchmark_timer_disable_subtracting_average_overhead -- |
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[3cfd520] | 144 | * This routine is invoked by the "Check Timer" (tmck) test in the |
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[a5cd2271] | 145 | * RTEMS Timing Test Suite. It makes the benchmark_timer_read routine not |
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[3cfd520] | 146 | * subtract the overhead required to initialize and read the benchmark |
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| 147 | * timer. |
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| 148 | * |
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| 149 | * PARAMETERS: |
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[3551166d] | 150 | * find_flag - bool flag, true if overhead must not be subtracted. |
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[3cfd520] | 151 | * |
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| 152 | * RETURNS: |
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| 153 | * none |
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| 154 | */ |
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| 155 | void |
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[3551166d] | 156 | benchmark_timer_disable_subtracting_average_overhead(bool find_flag) |
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[3cfd520] | 157 | { |
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[a5cd2271] | 158 | benchmark_timer_find_average_overhead = find_flag; |
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[3cfd520] | 159 | } |
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