source: rtems/c/src/lib/libcpu/m68k/mcf5272/include/mcf5272.h @ 3cfd520

4.104.114.84.95
Last change on this file since 3cfd520 was 3cfd520, checked in by Jay Monkman <jtm@…>, on 08/03/04 at 04:59:11

2004-08-02 Jay Monkman <jtm@…>

  • Makefile.am, configure.ac: Added CSB360 BSP
  • mcf5272/.cvsignore, mcf5272/ChangeLog, mcf5272/Makefile.am, mcf5272/clock/.cvsignore, mcf5272/clock/ckinit.c, mcf5272/include/.cvsignore, mcf5272/include/mcf5272.h, mcf5272/timer/.cvsignore, mcf5272/timer/timer.c, mcf5272/timer/timerisr.S: New files.
  • Property mode set to 100644
File size: 20.7 KB
Line 
1/*
2 * Coldfire MCF5272 definitions.
3 * Contents of this file based on information provided in
4 * Motorola MCF5272 User's Manual.
5 *
6 * Copyright (C) 2004 Jay Monkman <jtm@lopingdog.com>
7 *
8 * The license and distribution terms for this file may be
9 * found in the file LICENSE in this distribution or at
10 *
11 * http://www.OARcorp.com/rtems/license.html.
12 *
13 * @(#) mcf5206e.h,v 1.1 2001/10/26 19:32:40 joel Exp
14 */
15
16#ifndef __MCF5272_H__
17#define __MCF5272_H__
18
19#ifndef ASM
20#include <rtems.h>
21#endif
22
23#define bit(x) (1 << (x))
24
25#define MCF5272_SIM_BASE(mbar)    ((mbar) + 0x0000)
26#define MCF5272_INT_BASE(mbar)    ((mbar) + 0x0020)
27#define MCF5272_CS_BASE(mbar)     ((mbar) + 0x0040)
28#define MCF5272_GPIO_BASE(mbar)   ((mbar) + 0x0080)
29#define MCF5272_QSPI_BASE(mbar)   ((mbar) + 0x00A0)
30#define MCF5272_PWM_BASE(mbar)    ((mbar) + 0x00C0)
31#define MCF5272_DMAC_BASE(mbar)   ((mbar) + 0x00E0)
32#define MCF5272_UART0_BASE(mbar)  ((mbar) + 0x0100)
33#define MCF5272_UART1_BASE(mbar)  ((mbar) + 0x0140)
34#define MCF5272_SDRAMC_BASE(mbar) ((mbar) + 0x0180)
35#define MCF5272_TIMER_BASE(mbar)  ((mbar) + 0x0200)
36#define MCF5272_PLIC_BASE(mbar)   ((mbar) + 0x0300)
37#define MCF5272_ENET_BASE(mbar)   ((mbar) + 0x0840)
38#define MCF5272_USB_BASE(mbar)    ((mbar) + 0x1000)
39
40
41/* RAMBAR - SRAM Base Address Register */
42#define MCF5272_RAMBAR_BA  (0xfffff000) /* SRAM Base Address */
43#define MCF5272_RAMBAR_WP  (0x00000100) /* Write Protect */
44#define MCF5272_RAMBAR_CI  (0x00000020) /* CPU Space mask */
45#define MCF5272_RAMBAR_SC  (0x00000010) /* Supervisor Code Space Mask */
46#define MCF5272_RAMBAR_SD  (0x00000008) /* Supervisor Data Space Mask */
47#define MCF5272_RAMBAR_UC  (0x00000004) /* User Code Space Mask */
48#define MCF5272_RAMBAR_UD  (0x00000002) /* User Data Space Mask */
49#define MCF5272_RAMBAR_V   (0x00000001) /* Contents of RAMBAR are valid */
50
51/* MBAR - Module Base Address Register */
52#define MCF5272_MBAR_BA  (0xffff0000) /* Base Address */
53#define MCF5272_MBAR_SC  (0x00000010) /* Supervisor Code Space Mask */
54#define MCF5272_MBAR_SD  (0x00000008) /* Supervisor Data Space Mask */
55#define MCF5272_MBAR_UC  (0x00000004) /* User Code Space Mask */
56#define MCF5272_MBAR_UD  (0x00000002) /* User Data Space Mask */
57#define MCF5272_MBAR_V   (0x00000001) /* Contents of MBAR are valid */
58
59/* CACR - Cache Control Register */
60#define MCF5272_CACR_CENB  (0x80000000) /* Cache Enable */
61#define MCF5272_CACR_CPDI  (0x10000000) /* Disable CPUSHL Invalidation */
62#define MCF5272_CACR_CFRZ  (0x08000000) /* Cache Freeze */
63#define MCF5272_CACR_CINV  (0x01000000) /* Cache Invalidate */
64#define MCF5272_CACR_CEIB  (0x00000400) /* Cache Enable Noncacheable
65                                           instruction bursting */
66#define MCF5272_CACR_DCM   (0x00000200) /* Default cache mode - noncacheable*/
67#define MCF5272_CACR_DBWE  (0x00000100) /* Default Buffered Write Enable */
68#define MCF5272_CACR_DWP   (0x00000020) /* Default Write Protection */
69#define MCF5272_CACR_CLNF  (0x00000003) /* Cache Line Fill */
70
71/* ACRx - Cache Access Control Registers */
72#define MCF5272_ACR_BA        (0xff000000) /* Address Base */
73#define MCF5272_ACR_BAM       (0x00ff0000) /* Address Mask */
74#define MCF5272_ACR_EN        (0x00008000) /* Enable */
75#define MCF5272_ACR_SM_USR    (0x00000000) /* Match if user mode */
76#define MCF5272_ACR_SM_SVR    (0x00002000) /* Match if supervisor mode */
77#define MCF5272_ACR_SM_ANY    (0x00004000) /* Match Always */
78#define MCF527_ACR_CM         (0x00000040) /* Cache Mode (1 - noncacheable) */
79#define MCF5272_ACR_BWE       (0x00000020) /* Buffered Write Enable */
80#define MCF5272_ACR_WP        (0x00000004) /* Write Protect */
81#define MCF5272_ACR_BASE(base) ((base) & MCF5272_ACR_BA)
82#define MCF5272_ACR_MASK(mask) (((mask) >> 8) & MCF5272_ACR_BAM)
83
84
85#define MCF5272_ICR1_INT1_PI     (bit(31))
86#define MCF5272_ICR1_INT1_IPL(x) ((x) << 28)
87#define MCF5272_ICR1_INT1_MASK   ((7) << 28)
88#define MCF5272_ICR1_INT2_PI     (bit(27))
89#define MCF5272_ICR1_INT2_IPL(x) ((x) << 24)
90#define MCF5272_ICR1_INT2_MASK   ((7) << 24)
91#define MCF5272_ICR1_INT3_PI     (bit(23))
92#define MCF5272_ICR1_INT3_IPL(x) ((x) << 20)
93#define MCF5272_ICR1_INT3_MASK   ((7) << 20)
94#define MCF5272_ICR1_INT3_PI     (bit(19))
95#define MCF5272_ICR1_INT3_IPL(x) ((x) << 16)
96#define MCF5272_ICR1_INT3_MASK   ((7) << 16)
97#define MCF5272_ICR1_TMR0_PI     (bit(15))
98#define MCF5272_ICR1_TMR0_IPL(x) ((x) << 12)
99#define MCF5272_ICR1_TMR0_MASK   ((7) << 12)
100#define MCF5272_ICR1_TMR1_PI     (bit(11))
101#define MCF5272_ICR1_TMR1_IPL(x) ((x) << 8)
102#define MCF5272_ICR1_TMR1_MASK   ((7) << 8)
103#define MCF5272_ICR1_TMR2_PI     (bit(7))
104#define MCF5272_ICR1_TMR2_IPL(x) ((x) << 4)
105#define MCF5272_ICR1_TMR2_MASK   ((7) << 4)
106#define MCF5272_ICR1_TMR3_PI     (bit(3))
107#define MCF5272_ICR1_TMR3_IPL(x) ((x) << 0)
108#define MCF5272_ICR1_TMR3_MASK   ((7) << 0)
109
110#define MCF5272_ICR3_USB4_PI     (bit(31))
111#define MCF5272_ICR3_USB4_IPL(x) ((x) << 28)
112#define MCF5272_ICR3_USB4_MASK   ((7) << 28)
113#define MCF5272_ICR3_USB5_PI     (bit(27))
114#define MCF5272_ICR3_USB5_IPL(x) ((x) << 24)
115#define MCF5272_ICR3_USB5_MASK   ((7) << 24)
116#define MCF5272_ICR3_USB6_PI     (bit(23))
117#define MCF5272_ICR3_USB6_IPL(x) ((x) << 20)
118#define MCF5272_ICR3_USB6_MASK   ((7) << 20)
119#define MCF5272_ICR3_USB7_PI     (bit(19))
120#define MCF5272_ICR3_USB7_IPL(x) ((x) << 16)
121#define MCF5272_ICR3_USB7_MASK   ((7) << 16)
122#define MCF5272_ICR3_DMA_PI     (bit(15))
123#define MCF5272_ICR3_DMA_IPL(x) ((x) << 12)
124#define MCF5272_ICR3_DMA_MASK   ((7) << 12)
125#define MCF5272_ICR3_ERX_PI     (bit(11))
126#define MCF5272_ICR3_ERX_IPL(x) ((x) << 8)
127#define MCF5272_ICR3_ERX_MASK   ((7) << 8)
128#define MCF5272_ICR3_ETX_PI     (bit(7))
129#define MCF5272_ICR3_ETX_IPL(x) ((x) << 4)
130#define MCF5272_ICR3_ETX_MASK   ((7) << 4)
131#define MCF5272_ICR3_ENTC_PI     (bit(3))
132#define MCF5272_ICR3_ENTC_IPL(x) ((x) << 0)
133#define MCF5272_ICR3_ENTC_MASK   ((7) << 0)
134
135
136#define MCF5272_USR_RB        (bit(7))
137#define MCF5272_USR_FE        (bit(6))
138#define MCF5272_USR_PE        (bit(5))
139#define MCF5272_USR_OE        (bit(4))
140#define MCF5272_USR_TXEMP     (bit(3))
141#define MCF5272_USR_TXRDY     (bit(2))
142#define MCF5272_USR_FFULL     (bit(1))
143#define MCF5272_USR_RXRDY     (bit(0))
144
145#define MCF5272_TMR_PS_MASK     0xff00
146#define MCF5272_TMR_PS_SHIFT    8
147#define MCF5272_TMR_CE_DISABLE  (0 << 6)
148#define MCF5272_TMR_CE_RISING   (1 << 6)
149#define MCF5272_TMR_CE_FALLING  (2 << 6)
150#define MCF5272_TMR_CE_ANY      (3 << 6)
151#define MCF5272_TMR_OM          (bit(5))
152#define MCF5272_TMR_ORI         (bit(4))
153#define MCF5272_TMR_FRR         (bit(3))
154#define MCF5272_TMR_CLK_STOP    (0 << 1)
155#define MCF5272_TMR_CLK_MSTR    (1 << 1)
156#define MCF5272_TMR_CLK_MSTR16  (2 << 1)
157#define MCF5272_TMR_CLK_TIN     (3 << 1)
158#define MCF5272_TMR_RST         (bit(0))
159#define MCF5272_TER_REF (bit(1))
160#define MCF5272_TER_CAP (bit(0))
161
162#define MCF5272_SCR_PRI         (bit(8))
163#define MCF5272_SCR_AR          (bit(7))
164#define MCF5272_SCR_SRST        (bit(6))
165#define MCF5272_SCR_BUSLOCK     (bit(3))
166#define MCF5272_SCR_HWR_128     (0)
167#define MCF5272_SCR_HWR_256     (1)
168#define MCF5272_SCR_HWR_512     (2)
169#define MCF5272_SCR_HWR_1024    (3)
170#define MCF5272_SCR_HWR_2048    (4)
171#define MCF5272_SCR_HWR_4096    (5)
172#define MCF5272_SCR_HWR_8192    (6)
173#define MCF5272_SCR_HWR_16384   (7)
174
175#define MCF5272_SPR_ADC         (bit(15))
176#define MCF5272_SPR_WPV         (bit(15))
177#define MCF5272_SPR_SMV         (bit(15))
178#define MCF5272_SPR_PE          (bit(15))
179#define MCF5272_SPR_HWT         (bit(15))
180#define MCF5272_SPR_RPV         (bit(15))
181#define MCF5272_SPR_EXT         (bit(15))
182#define MCF5272_SPR_SUV         (bit(15))
183#define MCF5272_SPR_ADCEN       (bit(15))
184#define MCF5272_SPR_WPVEN       (bit(15))
185#define MCF5272_SPR_SMVEN       (bit(15))
186#define MCF5272_SPR_PEEN        (bit(15))
187#define MCF5272_SPR_HWTEN       (bit(15))
188#define MCF5272_SPR_RPVEN       (bit(15))
189#define MCF5272_SPR_EXTEN       (bit(15))
190#define MCF5272_SPR_SUVEN       (bit(15))
191
192#define MCF5272_ENET_TX_RT      (bit(25))
193#define MCF5272_ENET_ETHERN_EN  (bit(1))
194#define MCF5272_ENET_RESET      (bit(0))
195
196#define MCF5272_ENET_EIR_HBERR  (bit(31))
197#define MCF5272_ENET_EIR_BABR   (bit(30))
198#define MCF5272_ENET_EIR_BABT   (bit(29))
199#define MCF5272_ENET_EIR_GRA    (bit(28))
200#define MCF5272_ENET_EIR_TXF    (bit(27))
201#define MCF5272_ENET_EIR_TXB    (bit(26))
202#define MCF5272_ENET_EIR_RXF    (bit(25))
203#define MCF5272_ENET_EIR_RXB    (bit(24))
204#define MCF5272_ENET_EIR_MII    (bit(23))
205#define MCF5272_ENET_EIR_EBERR  (bit(22))
206#define MCF5272_ENET_EIR_UMINT  (bit(21))
207
208#define MCF5272_ENET_RCR_PROM   (bit(3))
209#define MCF5272_ENET_RCR_MII    (bit(2))
210#define MCF5272_ENET_RCR_DRT    (bit(1))
211#define MCF5272_ENET_RCR_LOOP   (bit(0))
212
213#define MCF5272_ENET_TCR_FDEN   (bit(2))
214#define MCF5272_ENET_TCR_HBC    (bit(1))
215#define MCF5272_ENET_TCR_GTS    (bit(0))
216
217
218#ifndef ASM
219typedef struct {
220    volatile unsigned32 mbar;       /* READ ONLY!! */
221
222    volatile unsigned16 scr;
223    volatile unsigned16 _res0;
224
225    volatile unsigned16 _res1;
226    volatile unsigned16 spr;
227
228    volatile unsigned32 pmr;
229
230    volatile unsigned16 _res2;
231    volatile unsigned16 alpr;
232
233    volatile unsigned32 dir;
234} sim_regs_t;
235
236typedef struct {
237    volatile unsigned32 icr1;
238    volatile unsigned32 icr2;
239    volatile unsigned32 icr3;
240    volatile unsigned32 icr4;
241    volatile unsigned32 isr;
242    volatile unsigned32 pitr;
243    volatile unsigned32 piwr;
244    volatile unsigned8  _res0[3];
245    volatile unsigned8  pivr;
246} intctrl_regs_t;
247
248typedef struct {
249    volatile unsigned32 csbr0;
250    volatile unsigned32 csor0;
251    volatile unsigned32 csbr1;
252    volatile unsigned32 csor1;
253    volatile unsigned32 csbr2;
254    volatile unsigned32 csor2;
255    volatile unsigned32 csbr3;
256    volatile unsigned32 csor3;
257    volatile unsigned32 csbr4;
258    volatile unsigned32 csor4;
259    volatile unsigned32 csbr5;
260    volatile unsigned32 csor5;
261    volatile unsigned32 csbr6;
262    volatile unsigned32 csor6;
263    volatile unsigned32 csbr7;
264    volatile unsigned32 csor7;
265} chipsel_regs_t;
266
267typedef struct {
268    volatile unsigned32 pacnt;
269
270    volatile unsigned16 paddr;
271    volatile unsigned16 _res0;
272
273    volatile unsigned16 _res1;
274    volatile unsigned16 padat;
275
276    volatile unsigned32 pbcnt;
277
278    volatile unsigned16 pbddr;
279    volatile unsigned16 _res2;
280
281    volatile unsigned16 _res3;
282    volatile unsigned16 pbdat;
283
284    volatile unsigned16 pcddr;
285    volatile unsigned16 _res4;
286
287    volatile unsigned16 _res5;
288    volatile unsigned16 pcdat;
289
290    volatile unsigned32 pdcnt;
291} gpio_regs_t;
292
293typedef struct {
294    volatile unsigned32 qmr;
295    volatile unsigned32 qdlyr;
296    volatile unsigned32 qwr;
297    volatile unsigned32 qir;
298    volatile unsigned32 qar;
299    volatile unsigned32 qdr;
300} qspi_regs_t;
301
302typedef struct {
303    volatile unsigned8 pwcr1;
304    volatile unsigned8 _res0[3];
305
306    volatile unsigned8 pwcr2;
307    volatile unsigned8 _res1[3];
308
309    volatile unsigned8 pwcr3;
310    volatile unsigned8 _res2[3];
311
312    volatile unsigned8 pwwd1;
313    volatile unsigned8 _res3[3];
314
315    volatile unsigned8 pwwd2;
316    volatile unsigned8 _res4[3];
317
318    volatile unsigned8 pwwd3;
319    volatile unsigned8 _res5[3];
320} pwm_regs_t;
321
322typedef struct {
323    volatile unsigned32 dcmr;
324   
325    volatile unsigned16 _res0;
326    volatile unsigned16 dcir;
327
328    volatile unsigned32 dbcr;
329
330    volatile unsigned32 dsar;
331
332    volatile unsigned32 ddar;
333} dma_regs_t;
334
335typedef struct {
336    volatile unsigned8 umr;              /* 0x000 */
337    volatile unsigned8 _res0[3];
338
339    volatile unsigned8 ucsr;             /* 0x004 */
340    volatile unsigned8 _res2[3];
341
342    volatile unsigned8 ucr;              /* 0x008 */
343    volatile unsigned8 _res3[3];
344
345    volatile unsigned8 udata;            /* 0x00c */
346    volatile unsigned8 _res4[3];
347
348    volatile unsigned8 uccr;             /* 0x010 */
349    volatile unsigned8 _res6[3];
350
351    volatile unsigned8 uisr;             /* 0x014 */
352    volatile unsigned8 _res8[3];
353
354    volatile unsigned8 ubg1;             /* 0x018 */
355    volatile unsigned8 _res10[3];
356
357    volatile unsigned8 ubg2;             /* 0x01c */
358    volatile unsigned8 _res11[3];
359
360    volatile unsigned8 uabr1;            /* 0x020 */
361    volatile unsigned8 _res12[3];
362
363    volatile unsigned8 uabr2;            /* 0x024 */
364    volatile unsigned8 _res13[3];
365
366    volatile unsigned8 utxfcsr;          /* 0x028 */
367    volatile unsigned8 _res14[3];
368
369    volatile unsigned8 urxfcsr;          /* 0x02c */
370    volatile unsigned8 _res15[3];
371
372    volatile unsigned8 ufpdn;            /* 0x030 */
373    volatile unsigned8 _res16[3];
374
375    volatile unsigned8 uip;              /* 0x034 */
376    volatile unsigned8 _res17[3];
377
378    volatile unsigned8 uop1;             /* 0x038 */
379    volatile unsigned8 _res18[3];
380
381    volatile unsigned8 uop0;             /* 0x03c */
382    volatile unsigned8 _res19[3];
383} uart_regs_t;
384
385typedef struct {
386    volatile unsigned16 tmr0;
387    volatile unsigned16 _res0;
388
389    volatile unsigned16 trr0;
390    volatile unsigned16 _res1;
391
392    volatile unsigned16 tcap0;
393    volatile unsigned16 _res2;
394
395    volatile unsigned16 tcn0;
396    volatile unsigned16 _res3;
397
398    volatile unsigned16 ter0;
399    volatile unsigned16 _res4;
400
401    volatile unsigned8  _res40[12];
402
403    volatile unsigned16 tmr1;
404    volatile unsigned16 _res5;
405
406    volatile unsigned16 trr1;
407    volatile unsigned16 _res6;
408
409    volatile unsigned16 tcap1;
410    volatile unsigned16 _res7;
411
412    volatile unsigned16 tcn1;
413    volatile unsigned16 _res8;
414
415    volatile unsigned16 ter1;
416    volatile unsigned16 _res9;
417
418    volatile unsigned8  _res91[12];
419
420    volatile unsigned16 tmr2;
421    volatile unsigned16 _res10;
422
423    volatile unsigned16 trr2;
424    volatile unsigned16 _res11;
425
426    volatile unsigned16 tcap2;
427    volatile unsigned16 _res12;
428
429    volatile unsigned16 tcn2;
430    volatile unsigned16 _res13;
431
432    volatile unsigned16 ter2;
433    volatile unsigned16 _res14;
434
435    volatile unsigned8  _res140[12];
436
437    volatile unsigned16 tmr3;
438    volatile unsigned16 _res15;
439
440    volatile unsigned16 trr3;
441    volatile unsigned16 _res16;
442
443    volatile unsigned16 tcap3;
444    volatile unsigned16 _res17;
445
446    volatile unsigned16 tcn3;
447    volatile unsigned16 _res18;
448
449    volatile unsigned16 ter3;
450    volatile unsigned16 _res19;
451
452    volatile unsigned8  _res190[12];
453
454    volatile unsigned16 wrrr;
455    volatile unsigned16 _res20;
456
457    volatile unsigned16 wirr;
458    volatile unsigned16 _res21;
459
460    volatile unsigned16 wcr;
461    volatile unsigned16 _res22;
462
463    volatile unsigned16 wer;
464    volatile unsigned16 _res23;
465} timer_regs_t;
466
467typedef struct {
468    volatile unsigned32 p0b1rr;
469    volatile unsigned32 p1b1rr;
470    volatile unsigned32 p2b1rr;
471    volatile unsigned32 p3b1rr;
472    volatile unsigned32 p0b2rr;
473    volatile unsigned32 p1b2rr;
474    volatile unsigned32 p2b2rr;
475    volatile unsigned32 p3b2rr;
476
477    volatile unsigned8  p0drr;
478    volatile unsigned8  p1drr;
479    volatile unsigned8  p2drr;
480    volatile unsigned8  p3drr;
481
482    volatile unsigned32 p0b1tr;
483    volatile unsigned32 p1b1tr;
484    volatile unsigned32 p2b1tr;
485    volatile unsigned32 p3b1tr;
486    volatile unsigned32 p0b2tr;
487    volatile unsigned32 p1b2tr;
488    volatile unsigned32 p2b2tr;
489    volatile unsigned32 p3b2tr;
490
491    volatile unsigned8  p0dtr;
492    volatile unsigned8  p1dtr;
493    volatile unsigned8  p2dtr;
494    volatile unsigned8  p3dtr;
495
496    volatile unsigned16 p0cr;
497    volatile unsigned16 p1cr;
498    volatile unsigned16 p2cr;
499    volatile unsigned16 p3cr;
500    volatile unsigned16 p0icr;
501    volatile unsigned16 p1icr;
502    volatile unsigned16 p2icr;
503    volatile unsigned16 p3icr;
504    volatile unsigned16 p0gmr;
505    volatile unsigned16 p1gmr;
506    volatile unsigned16 p2gmr;
507    volatile unsigned16 p3gmr;
508    volatile unsigned16 p0gmt;
509    volatile unsigned16 p1gmt;
510    volatile unsigned16 p2gmt;
511    volatile unsigned16 p3gmt;
512
513    volatile unsigned8  _res0;
514    volatile unsigned8  pgmts;
515    volatile unsigned8  pgmta;
516    volatile unsigned8  _res1;
517    volatile unsigned8  p0gcir;
518    volatile unsigned8  p1gcir;
519    volatile unsigned8  p2gcir;
520    volatile unsigned8  p3gcir;
521    volatile unsigned8  p0gcit;
522    volatile unsigned8  p1gcit;
523    volatile unsigned8  p2gcit;
524    volatile unsigned8  p3gcit;
525    volatile unsigned8  _res3[3];
526    volatile unsigned8  pgcitsr;
527    volatile unsigned8  _res4[3];
528    volatile unsigned8  pdcsr;
529
530    volatile unsigned16 p0psr;
531    volatile unsigned16 p1psr;
532    volatile unsigned16 p2psr;
533    volatile unsigned16 p3psr;
534    volatile unsigned16 pasr;
535    volatile unsigned8  _res5;
536    volatile unsigned8  plcr;
537    volatile unsigned16 _res6;
538    volatile unsigned16 pdrqr;
539    volatile unsigned16 p0sdr;
540    volatile unsigned16 p1sdr;
541    volatile unsigned16 p2sdr;
542    volatile unsigned16 p3sdr;
543    volatile unsigned16 _res7;
544    volatile unsigned16 pcsr;
545} plic_regs_t;
546
547typedef struct {
548    volatile unsigned32 ecr;
549    volatile unsigned32 eir;
550    volatile unsigned32 eimr;
551    volatile unsigned32 ivsr;
552    volatile unsigned32 rdar;
553    volatile unsigned32 tdar;
554    volatile unsigned32 _res0[10];
555    volatile unsigned32 mmfr;
556    volatile unsigned32 mscr;
557    volatile unsigned32 _res1[17];
558    volatile unsigned32 frbr;
559    volatile unsigned32 frsr;
560    volatile unsigned32 _res2[4];
561    volatile unsigned32 tfwr;
562    volatile unsigned32 _res3[1];
563    volatile unsigned32 tfsr;
564    volatile unsigned32 _res4[21];
565    volatile unsigned32 rcr;
566    volatile unsigned32 mflr;
567    volatile unsigned32 _res5[14];
568    volatile unsigned32 tcr;
569    volatile unsigned32 _res6[158];
570    volatile unsigned32 malr;
571    volatile unsigned32 maur;
572    volatile unsigned32 htur;
573    volatile unsigned32 htlr;
574    volatile unsigned32 erdsr;
575    volatile unsigned32 etdsr;
576    volatile unsigned32 emrbr;
577/*    volatile unsigned8  fifo[448]; */
578} enet_regs_t;
579
580typedef struct {
581    volatile unsigned16 _res0;
582    volatile unsigned16 fnr;
583    volatile unsigned16 _res1;
584    volatile unsigned16 fnmr;
585    volatile unsigned16 _res2;
586    volatile unsigned16 rfmr;
587    volatile unsigned16 _res3;
588    volatile unsigned16 rfmmr;
589    volatile unsigned8  _res4[3];
590    volatile unsigned8  far;
591    volatile unsigned32 asr;
592    volatile unsigned32 drr1;
593    volatile unsigned32 drr2;
594    volatile unsigned16 _res5;
595    volatile unsigned16 specr;
596    volatile unsigned16 _res6;
597    volatile unsigned16 ep0sr;
598
599    volatile unsigned32 iep0cfg;
600    volatile unsigned32 oep0cfg;
601    volatile unsigned32 ep1cfg;
602    volatile unsigned32 ep2cfg;
603    volatile unsigned32 ep3cfg;
604    volatile unsigned32 ep4cfg;
605    volatile unsigned32 ep5cfg;
606    volatile unsigned32 ep6cfg;
607    volatile unsigned32 ep7cfg;
608    volatile unsigned32 ep0ctl;
609
610    volatile unsigned16 _res7;
611    volatile unsigned16 ep1ctl;
612    volatile unsigned16 _res8;
613    volatile unsigned16 ep2ctl;
614    volatile unsigned16 _res9;
615    volatile unsigned16 ep3ctl;
616    volatile unsigned16 _res10;
617    volatile unsigned16 ep4ctl;
618    volatile unsigned16 _res11;
619    volatile unsigned16 ep5ctl;
620    volatile unsigned16 _res12;
621    volatile unsigned16 ep6ctl;
622    volatile unsigned16 _res13;
623    volatile unsigned16 ep7ctl;
624
625    volatile unsigned32 ep0isr;
626
627    volatile unsigned16 _res14;
628    volatile unsigned16 ep1isr;
629    volatile unsigned16 _res15;
630    volatile unsigned16 ep2isr;
631    volatile unsigned16 _res16;
632    volatile unsigned16 ep3isr;
633    volatile unsigned16 _res17;
634    volatile unsigned16 ep4isr;
635    volatile unsigned16 _res18;
636    volatile unsigned16 ep5isr;
637    volatile unsigned16 _res19;
638    volatile unsigned16 ep6isr;
639    volatile unsigned16 _res20;
640    volatile unsigned16 ep7isr;
641
642    volatile unsigned32 ep0imr;
643
644    volatile unsigned16 _res21;
645    volatile unsigned16 ep1imr;
646    volatile unsigned16 _res22;
647    volatile unsigned16 ep2imr;
648    volatile unsigned16 _res23;
649    volatile unsigned16 ep3imr;
650    volatile unsigned16 _res24;
651    volatile unsigned16 ep4imr;
652    volatile unsigned16 _res25;
653    volatile unsigned16 ep5imr;
654    volatile unsigned16 _res26;
655    volatile unsigned16 ep6imr;
656    volatile unsigned16 _res27;
657    volatile unsigned16 ep7imr;
658
659    volatile unsigned32 ep0dr;
660    volatile unsigned32 ep1dr;
661    volatile unsigned32 ep2dr;
662    volatile unsigned32 ep3dr;
663    volatile unsigned32 ep4dr;
664    volatile unsigned32 ep5dr;
665    volatile unsigned32 ep6dr;
666    volatile unsigned32 ep7dr;
667
668    volatile unsigned16 _res28;
669    volatile unsigned16 ep0dpr;
670    volatile unsigned16 _res29;
671    volatile unsigned16 ep1dpr;
672    volatile unsigned16 _res30;
673    volatile unsigned16 ep2dpr;
674    volatile unsigned16 _res31;
675    volatile unsigned16 ep3dpr;
676    volatile unsigned16 _res32;
677    volatile unsigned16 ep4dpr;
678    volatile unsigned16 _res33;
679    volatile unsigned16 ep5dpr;
680    volatile unsigned16 _res34;
681    volatile unsigned16 ep6dpr;
682    volatile unsigned16 _res35;
683    volatile unsigned16 ep7dpr;
684/*    unsigned8  ram[1024]; */
685} usb_regs_t;
686
687extern intctrl_regs_t *g_intctrl_regs;
688extern chipsel_regs_t *g_chipsel_regs;
689extern gpio_regs_t *g_gpio_regs;
690extern qspi_regs_t *g_qspi_regs;
691extern pwm_regs_t *g_pwm_regs;
692extern dma_regs_t *g_dma_regs;
693extern uart_regs_t *g_uart0_regs;
694extern uart_regs_t *g_uart1_regs;
695extern timer_regs_t *g_timer_regs;
696extern plic_regs_t *g_plic_regs;
697extern enet_regs_t *g_enet_regs;
698extern usb_regs_t *g_usb_regs;
699
700#endif /* ASM */
701
702#endif /* __MCF5272_H__ */
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