[3cfd520] | 1 | /* |
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[78dea6ce] | 2 | * Coldfire MCF5272 definitions. |
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| 3 | * Contents of this file based on information provided in |
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| 4 | * Motorola MCF5272 User's Manual. |
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[3cfd520] | 5 | * |
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[78dea6ce] | 6 | * Copyright (C) 2004 Jay Monkman <jtm@lopingdog.com> |
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[3cfd520] | 7 | * |
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[78dea6ce] | 8 | * The license and distribution terms for this file may be |
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| 9 | * found in the file LICENSE in this distribution or at |
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[c499856] | 10 | * http://www.rtems.org/license/LICENSE. |
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[3cfd520] | 11 | */ |
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| 12 | |
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| 13 | #ifndef __MCF5272_H__ |
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| 14 | #define __MCF5272_H__ |
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| 15 | |
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| 16 | #ifndef ASM |
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| 17 | #include <rtems.h> |
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| 18 | #endif |
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| 19 | |
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| 20 | #define bit(x) (1 << (x)) |
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| 21 | |
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| 22 | #define MCF5272_SIM_BASE(mbar) ((mbar) + 0x0000) |
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| 23 | #define MCF5272_INT_BASE(mbar) ((mbar) + 0x0020) |
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| 24 | #define MCF5272_CS_BASE(mbar) ((mbar) + 0x0040) |
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| 25 | #define MCF5272_GPIO_BASE(mbar) ((mbar) + 0x0080) |
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| 26 | #define MCF5272_QSPI_BASE(mbar) ((mbar) + 0x00A0) |
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| 27 | #define MCF5272_PWM_BASE(mbar) ((mbar) + 0x00C0) |
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| 28 | #define MCF5272_DMAC_BASE(mbar) ((mbar) + 0x00E0) |
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| 29 | #define MCF5272_UART0_BASE(mbar) ((mbar) + 0x0100) |
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| 30 | #define MCF5272_UART1_BASE(mbar) ((mbar) + 0x0140) |
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| 31 | #define MCF5272_SDRAMC_BASE(mbar) ((mbar) + 0x0180) |
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| 32 | #define MCF5272_TIMER_BASE(mbar) ((mbar) + 0x0200) |
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| 33 | #define MCF5272_PLIC_BASE(mbar) ((mbar) + 0x0300) |
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| 34 | #define MCF5272_ENET_BASE(mbar) ((mbar) + 0x0840) |
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| 35 | #define MCF5272_USB_BASE(mbar) ((mbar) + 0x1000) |
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| 36 | |
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| 37 | |
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| 38 | /* RAMBAR - SRAM Base Address Register */ |
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| 39 | #define MCF5272_RAMBAR_BA (0xfffff000) /* SRAM Base Address */ |
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| 40 | #define MCF5272_RAMBAR_WP (0x00000100) /* Write Protect */ |
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| 41 | #define MCF5272_RAMBAR_CI (0x00000020) /* CPU Space mask */ |
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| 42 | #define MCF5272_RAMBAR_SC (0x00000010) /* Supervisor Code Space Mask */ |
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| 43 | #define MCF5272_RAMBAR_SD (0x00000008) /* Supervisor Data Space Mask */ |
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| 44 | #define MCF5272_RAMBAR_UC (0x00000004) /* User Code Space Mask */ |
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| 45 | #define MCF5272_RAMBAR_UD (0x00000002) /* User Data Space Mask */ |
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| 46 | #define MCF5272_RAMBAR_V (0x00000001) /* Contents of RAMBAR are valid */ |
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| 47 | |
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| 48 | /* MBAR - Module Base Address Register */ |
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| 49 | #define MCF5272_MBAR_BA (0xffff0000) /* Base Address */ |
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| 50 | #define MCF5272_MBAR_SC (0x00000010) /* Supervisor Code Space Mask */ |
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| 51 | #define MCF5272_MBAR_SD (0x00000008) /* Supervisor Data Space Mask */ |
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| 52 | #define MCF5272_MBAR_UC (0x00000004) /* User Code Space Mask */ |
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| 53 | #define MCF5272_MBAR_UD (0x00000002) /* User Data Space Mask */ |
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| 54 | #define MCF5272_MBAR_V (0x00000001) /* Contents of MBAR are valid */ |
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| 55 | |
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| 56 | /* CACR - Cache Control Register */ |
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| 57 | #define MCF5272_CACR_CENB (0x80000000) /* Cache Enable */ |
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| 58 | #define MCF5272_CACR_CPDI (0x10000000) /* Disable CPUSHL Invalidation */ |
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| 59 | #define MCF5272_CACR_CFRZ (0x08000000) /* Cache Freeze */ |
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| 60 | #define MCF5272_CACR_CINV (0x01000000) /* Cache Invalidate */ |
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| 61 | #define MCF5272_CACR_CEIB (0x00000400) /* Cache Enable Noncacheable |
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| 62 | instruction bursting */ |
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| 63 | #define MCF5272_CACR_DCM (0x00000200) /* Default cache mode - noncacheable*/ |
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| 64 | #define MCF5272_CACR_DBWE (0x00000100) /* Default Buffered Write Enable */ |
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| 65 | #define MCF5272_CACR_DWP (0x00000020) /* Default Write Protection */ |
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| 66 | #define MCF5272_CACR_CLNF (0x00000003) /* Cache Line Fill */ |
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| 67 | |
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| 68 | /* ACRx - Cache Access Control Registers */ |
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| 69 | #define MCF5272_ACR_BA (0xff000000) /* Address Base */ |
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| 70 | #define MCF5272_ACR_BAM (0x00ff0000) /* Address Mask */ |
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| 71 | #define MCF5272_ACR_EN (0x00008000) /* Enable */ |
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| 72 | #define MCF5272_ACR_SM_USR (0x00000000) /* Match if user mode */ |
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| 73 | #define MCF5272_ACR_SM_SVR (0x00002000) /* Match if supervisor mode */ |
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| 74 | #define MCF5272_ACR_SM_ANY (0x00004000) /* Match Always */ |
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| 75 | #define MCF527_ACR_CM (0x00000040) /* Cache Mode (1 - noncacheable) */ |
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| 76 | #define MCF5272_ACR_BWE (0x00000020) /* Buffered Write Enable */ |
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| 77 | #define MCF5272_ACR_WP (0x00000004) /* Write Protect */ |
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| 78 | #define MCF5272_ACR_BASE(base) ((base) & MCF5272_ACR_BA) |
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| 79 | #define MCF5272_ACR_MASK(mask) (((mask) >> 8) & MCF5272_ACR_BAM) |
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| 80 | |
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| 81 | |
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| 82 | #define MCF5272_ICR1_INT1_PI (bit(31)) |
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| 83 | #define MCF5272_ICR1_INT1_IPL(x) ((x) << 28) |
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| 84 | #define MCF5272_ICR1_INT1_MASK ((7) << 28) |
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| 85 | #define MCF5272_ICR1_INT2_PI (bit(27)) |
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| 86 | #define MCF5272_ICR1_INT2_IPL(x) ((x) << 24) |
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| 87 | #define MCF5272_ICR1_INT2_MASK ((7) << 24) |
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| 88 | #define MCF5272_ICR1_INT3_PI (bit(23)) |
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| 89 | #define MCF5272_ICR1_INT3_IPL(x) ((x) << 20) |
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| 90 | #define MCF5272_ICR1_INT3_MASK ((7) << 20) |
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| 91 | #define MCF5272_ICR1_INT3_PI (bit(19)) |
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| 92 | #define MCF5272_ICR1_INT3_IPL(x) ((x) << 16) |
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| 93 | #define MCF5272_ICR1_INT3_MASK ((7) << 16) |
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| 94 | #define MCF5272_ICR1_TMR0_PI (bit(15)) |
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| 95 | #define MCF5272_ICR1_TMR0_IPL(x) ((x) << 12) |
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| 96 | #define MCF5272_ICR1_TMR0_MASK ((7) << 12) |
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| 97 | #define MCF5272_ICR1_TMR1_PI (bit(11)) |
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| 98 | #define MCF5272_ICR1_TMR1_IPL(x) ((x) << 8) |
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| 99 | #define MCF5272_ICR1_TMR1_MASK ((7) << 8) |
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| 100 | #define MCF5272_ICR1_TMR2_PI (bit(7)) |
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| 101 | #define MCF5272_ICR1_TMR2_IPL(x) ((x) << 4) |
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| 102 | #define MCF5272_ICR1_TMR2_MASK ((7) << 4) |
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| 103 | #define MCF5272_ICR1_TMR3_PI (bit(3)) |
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| 104 | #define MCF5272_ICR1_TMR3_IPL(x) ((x) << 0) |
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| 105 | #define MCF5272_ICR1_TMR3_MASK ((7) << 0) |
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| 106 | |
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| 107 | #define MCF5272_ICR3_USB4_PI (bit(31)) |
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| 108 | #define MCF5272_ICR3_USB4_IPL(x) ((x) << 28) |
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| 109 | #define MCF5272_ICR3_USB4_MASK ((7) << 28) |
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| 110 | #define MCF5272_ICR3_USB5_PI (bit(27)) |
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| 111 | #define MCF5272_ICR3_USB5_IPL(x) ((x) << 24) |
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| 112 | #define MCF5272_ICR3_USB5_MASK ((7) << 24) |
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| 113 | #define MCF5272_ICR3_USB6_PI (bit(23)) |
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| 114 | #define MCF5272_ICR3_USB6_IPL(x) ((x) << 20) |
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| 115 | #define MCF5272_ICR3_USB6_MASK ((7) << 20) |
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| 116 | #define MCF5272_ICR3_USB7_PI (bit(19)) |
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| 117 | #define MCF5272_ICR3_USB7_IPL(x) ((x) << 16) |
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| 118 | #define MCF5272_ICR3_USB7_MASK ((7) << 16) |
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| 119 | #define MCF5272_ICR3_DMA_PI (bit(15)) |
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| 120 | #define MCF5272_ICR3_DMA_IPL(x) ((x) << 12) |
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| 121 | #define MCF5272_ICR3_DMA_MASK ((7) << 12) |
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| 122 | #define MCF5272_ICR3_ERX_PI (bit(11)) |
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| 123 | #define MCF5272_ICR3_ERX_IPL(x) ((x) << 8) |
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| 124 | #define MCF5272_ICR3_ERX_MASK ((7) << 8) |
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| 125 | #define MCF5272_ICR3_ETX_PI (bit(7)) |
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| 126 | #define MCF5272_ICR3_ETX_IPL(x) ((x) << 4) |
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| 127 | #define MCF5272_ICR3_ETX_MASK ((7) << 4) |
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| 128 | #define MCF5272_ICR3_ENTC_PI (bit(3)) |
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| 129 | #define MCF5272_ICR3_ENTC_IPL(x) ((x) << 0) |
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| 130 | #define MCF5272_ICR3_ENTC_MASK ((7) << 0) |
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| 131 | |
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| 132 | |
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| 133 | #define MCF5272_USR_RB (bit(7)) |
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| 134 | #define MCF5272_USR_FE (bit(6)) |
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| 135 | #define MCF5272_USR_PE (bit(5)) |
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| 136 | #define MCF5272_USR_OE (bit(4)) |
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| 137 | #define MCF5272_USR_TXEMP (bit(3)) |
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| 138 | #define MCF5272_USR_TXRDY (bit(2)) |
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| 139 | #define MCF5272_USR_FFULL (bit(1)) |
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| 140 | #define MCF5272_USR_RXRDY (bit(0)) |
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| 141 | |
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| 142 | #define MCF5272_TMR_PS_MASK 0xff00 |
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| 143 | #define MCF5272_TMR_PS_SHIFT 8 |
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| 144 | #define MCF5272_TMR_CE_DISABLE (0 << 6) |
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| 145 | #define MCF5272_TMR_CE_RISING (1 << 6) |
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| 146 | #define MCF5272_TMR_CE_FALLING (2 << 6) |
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| 147 | #define MCF5272_TMR_CE_ANY (3 << 6) |
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| 148 | #define MCF5272_TMR_OM (bit(5)) |
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| 149 | #define MCF5272_TMR_ORI (bit(4)) |
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| 150 | #define MCF5272_TMR_FRR (bit(3)) |
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| 151 | #define MCF5272_TMR_CLK_STOP (0 << 1) |
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| 152 | #define MCF5272_TMR_CLK_MSTR (1 << 1) |
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| 153 | #define MCF5272_TMR_CLK_MSTR16 (2 << 1) |
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| 154 | #define MCF5272_TMR_CLK_TIN (3 << 1) |
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| 155 | #define MCF5272_TMR_RST (bit(0)) |
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| 156 | #define MCF5272_TER_REF (bit(1)) |
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| 157 | #define MCF5272_TER_CAP (bit(0)) |
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| 158 | |
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| 159 | #define MCF5272_SCR_PRI (bit(8)) |
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| 160 | #define MCF5272_SCR_AR (bit(7)) |
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| 161 | #define MCF5272_SCR_SRST (bit(6)) |
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| 162 | #define MCF5272_SCR_BUSLOCK (bit(3)) |
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| 163 | #define MCF5272_SCR_HWR_128 (0) |
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| 164 | #define MCF5272_SCR_HWR_256 (1) |
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| 165 | #define MCF5272_SCR_HWR_512 (2) |
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| 166 | #define MCF5272_SCR_HWR_1024 (3) |
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| 167 | #define MCF5272_SCR_HWR_2048 (4) |
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| 168 | #define MCF5272_SCR_HWR_4096 (5) |
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| 169 | #define MCF5272_SCR_HWR_8192 (6) |
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| 170 | #define MCF5272_SCR_HWR_16384 (7) |
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| 171 | |
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| 172 | #define MCF5272_SPR_ADC (bit(15)) |
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| 173 | #define MCF5272_SPR_WPV (bit(15)) |
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| 174 | #define MCF5272_SPR_SMV (bit(15)) |
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| 175 | #define MCF5272_SPR_PE (bit(15)) |
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| 176 | #define MCF5272_SPR_HWT (bit(15)) |
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| 177 | #define MCF5272_SPR_RPV (bit(15)) |
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| 178 | #define MCF5272_SPR_EXT (bit(15)) |
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| 179 | #define MCF5272_SPR_SUV (bit(15)) |
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| 180 | #define MCF5272_SPR_ADCEN (bit(15)) |
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| 181 | #define MCF5272_SPR_WPVEN (bit(15)) |
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| 182 | #define MCF5272_SPR_SMVEN (bit(15)) |
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| 183 | #define MCF5272_SPR_PEEN (bit(15)) |
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| 184 | #define MCF5272_SPR_HWTEN (bit(15)) |
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| 185 | #define MCF5272_SPR_RPVEN (bit(15)) |
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| 186 | #define MCF5272_SPR_EXTEN (bit(15)) |
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| 187 | #define MCF5272_SPR_SUVEN (bit(15)) |
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| 188 | |
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| 189 | #define MCF5272_ENET_TX_RT (bit(25)) |
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| 190 | #define MCF5272_ENET_ETHERN_EN (bit(1)) |
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| 191 | #define MCF5272_ENET_RESET (bit(0)) |
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| 192 | |
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| 193 | #define MCF5272_ENET_EIR_HBERR (bit(31)) |
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| 194 | #define MCF5272_ENET_EIR_BABR (bit(30)) |
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| 195 | #define MCF5272_ENET_EIR_BABT (bit(29)) |
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| 196 | #define MCF5272_ENET_EIR_GRA (bit(28)) |
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| 197 | #define MCF5272_ENET_EIR_TXF (bit(27)) |
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| 198 | #define MCF5272_ENET_EIR_TXB (bit(26)) |
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| 199 | #define MCF5272_ENET_EIR_RXF (bit(25)) |
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| 200 | #define MCF5272_ENET_EIR_RXB (bit(24)) |
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| 201 | #define MCF5272_ENET_EIR_MII (bit(23)) |
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| 202 | #define MCF5272_ENET_EIR_EBERR (bit(22)) |
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| 203 | #define MCF5272_ENET_EIR_UMINT (bit(21)) |
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| 204 | |
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| 205 | #define MCF5272_ENET_RCR_PROM (bit(3)) |
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| 206 | #define MCF5272_ENET_RCR_MII (bit(2)) |
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| 207 | #define MCF5272_ENET_RCR_DRT (bit(1)) |
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| 208 | #define MCF5272_ENET_RCR_LOOP (bit(0)) |
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| 209 | |
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| 210 | #define MCF5272_ENET_TCR_FDEN (bit(2)) |
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| 211 | #define MCF5272_ENET_TCR_HBC (bit(1)) |
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| 212 | #define MCF5272_ENET_TCR_GTS (bit(0)) |
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| 213 | |
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| 214 | |
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| 215 | #ifndef ASM |
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| 216 | typedef struct { |
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[ee5769ad] | 217 | volatile uint32_t mbar; /* READ ONLY!! */ |
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[3cfd520] | 218 | |
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[ee5769ad] | 219 | volatile uint16_t scr; |
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| 220 | volatile uint16_t _res0; |
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[3cfd520] | 221 | |
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[ee5769ad] | 222 | volatile uint16_t _res1; |
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| 223 | volatile uint16_t spr; |
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[3cfd520] | 224 | |
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[ee5769ad] | 225 | volatile uint32_t pmr; |
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[3cfd520] | 226 | |
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[ee5769ad] | 227 | volatile uint16_t _res2; |
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| 228 | volatile uint16_t alpr; |
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[3cfd520] | 229 | |
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[ee5769ad] | 230 | volatile uint32_t dir; |
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[3cfd520] | 231 | } sim_regs_t; |
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| 232 | |
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| 233 | typedef struct { |
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[ee5769ad] | 234 | volatile uint32_t icr1; |
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| 235 | volatile uint32_t icr2; |
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| 236 | volatile uint32_t icr3; |
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| 237 | volatile uint32_t icr4; |
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| 238 | volatile uint32_t isr; |
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| 239 | volatile uint32_t pitr; |
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| 240 | volatile uint32_t piwr; |
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| 241 | volatile uint8_t _res0[3]; |
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| 242 | volatile uint8_t pivr; |
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[3cfd520] | 243 | } intctrl_regs_t; |
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| 244 | |
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| 245 | typedef struct { |
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[ee5769ad] | 246 | volatile uint32_t csbr0; |
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| 247 | volatile uint32_t csor0; |
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| 248 | volatile uint32_t csbr1; |
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| 249 | volatile uint32_t csor1; |
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| 250 | volatile uint32_t csbr2; |
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| 251 | volatile uint32_t csor2; |
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| 252 | volatile uint32_t csbr3; |
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| 253 | volatile uint32_t csor3; |
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| 254 | volatile uint32_t csbr4; |
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| 255 | volatile uint32_t csor4; |
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| 256 | volatile uint32_t csbr5; |
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| 257 | volatile uint32_t csor5; |
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| 258 | volatile uint32_t csbr6; |
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| 259 | volatile uint32_t csor6; |
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| 260 | volatile uint32_t csbr7; |
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| 261 | volatile uint32_t csor7; |
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[3cfd520] | 262 | } chipsel_regs_t; |
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| 263 | |
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| 264 | typedef struct { |
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[ee5769ad] | 265 | volatile uint32_t pacnt; |
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[3cfd520] | 266 | |
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[ee5769ad] | 267 | volatile uint16_t paddr; |
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| 268 | volatile uint16_t _res0; |
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[3cfd520] | 269 | |
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[ee5769ad] | 270 | volatile uint16_t _res1; |
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| 271 | volatile uint16_t padat; |
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[3cfd520] | 272 | |
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[ee5769ad] | 273 | volatile uint32_t pbcnt; |
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[3cfd520] | 274 | |
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[ee5769ad] | 275 | volatile uint16_t pbddr; |
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| 276 | volatile uint16_t _res2; |
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[3cfd520] | 277 | |
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[ee5769ad] | 278 | volatile uint16_t _res3; |
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| 279 | volatile uint16_t pbdat; |
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[3cfd520] | 280 | |
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[023f1dd9] | 281 | volatile uint16_t pcddr; |
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[ee5769ad] | 282 | volatile uint16_t _res4; |
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[3cfd520] | 283 | |
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[ee5769ad] | 284 | volatile uint16_t _res5; |
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| 285 | volatile uint16_t pcdat; |
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[3cfd520] | 286 | |
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[ee5769ad] | 287 | volatile uint32_t pdcnt; |
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[3cfd520] | 288 | } gpio_regs_t; |
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| 289 | |
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| 290 | typedef struct { |
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[ee5769ad] | 291 | volatile uint32_t qmr; |
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| 292 | volatile uint32_t qdlyr; |
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| 293 | volatile uint32_t qwr; |
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| 294 | volatile uint32_t qir; |
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| 295 | volatile uint32_t qar; |
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| 296 | volatile uint32_t qdr; |
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[3cfd520] | 297 | } qspi_regs_t; |
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| 298 | |
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| 299 | typedef struct { |
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[ee5769ad] | 300 | volatile uint8_t pwcr1; |
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| 301 | volatile uint8_t _res0[3]; |
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[3cfd520] | 302 | |
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[ee5769ad] | 303 | volatile uint8_t pwcr2; |
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| 304 | volatile uint8_t _res1[3]; |
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[3cfd520] | 305 | |
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[ee5769ad] | 306 | volatile uint8_t pwcr3; |
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| 307 | volatile uint8_t _res2[3]; |
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[3cfd520] | 308 | |
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[ee5769ad] | 309 | volatile uint8_t pwwd1; |
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| 310 | volatile uint8_t _res3[3]; |
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[3cfd520] | 311 | |
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[ee5769ad] | 312 | volatile uint8_t pwwd2; |
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| 313 | volatile uint8_t _res4[3]; |
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[3cfd520] | 314 | |
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[ee5769ad] | 315 | volatile uint8_t pwwd3; |
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| 316 | volatile uint8_t _res5[3]; |
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[3cfd520] | 317 | } pwm_regs_t; |
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| 318 | |
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| 319 | typedef struct { |
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[ee5769ad] | 320 | volatile uint32_t dcmr; |
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[023f1dd9] | 321 | |
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[ee5769ad] | 322 | volatile uint16_t _res0; |
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| 323 | volatile uint16_t dcir; |
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[3cfd520] | 324 | |
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[ee5769ad] | 325 | volatile uint32_t dbcr; |
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[3cfd520] | 326 | |
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[ee5769ad] | 327 | volatile uint32_t dsar; |
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[3cfd520] | 328 | |
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[ee5769ad] | 329 | volatile uint32_t ddar; |
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[3cfd520] | 330 | } dma_regs_t; |
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| 331 | |
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| 332 | typedef struct { |
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[ee5769ad] | 333 | volatile uint8_t umr; /* 0x000 */ |
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| 334 | volatile uint8_t _res0[3]; |
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[3cfd520] | 335 | |
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[ee5769ad] | 336 | volatile uint8_t ucsr; /* 0x004 */ |
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| 337 | volatile uint8_t _res2[3]; |
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[3cfd520] | 338 | |
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[ee5769ad] | 339 | volatile uint8_t ucr; /* 0x008 */ |
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| 340 | volatile uint8_t _res3[3]; |
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[3cfd520] | 341 | |
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[ee5769ad] | 342 | volatile uint8_t udata; /* 0x00c */ |
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| 343 | volatile uint8_t _res4[3]; |
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[3cfd520] | 344 | |
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[ee5769ad] | 345 | volatile uint8_t uccr; /* 0x010 */ |
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| 346 | volatile uint8_t _res6[3]; |
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[3cfd520] | 347 | |
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[ee5769ad] | 348 | volatile uint8_t uisr; /* 0x014 */ |
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| 349 | volatile uint8_t _res8[3]; |
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[3cfd520] | 350 | |
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[ee5769ad] | 351 | volatile uint8_t ubg1; /* 0x018 */ |
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| 352 | volatile uint8_t _res10[3]; |
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[3cfd520] | 353 | |
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[ee5769ad] | 354 | volatile uint8_t ubg2; /* 0x01c */ |
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| 355 | volatile uint8_t _res11[3]; |
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[3cfd520] | 356 | |
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[ee5769ad] | 357 | volatile uint8_t uabr1; /* 0x020 */ |
---|
| 358 | volatile uint8_t _res12[3]; |
---|
[3cfd520] | 359 | |
---|
[ee5769ad] | 360 | volatile uint8_t uabr2; /* 0x024 */ |
---|
| 361 | volatile uint8_t _res13[3]; |
---|
[3cfd520] | 362 | |
---|
[ee5769ad] | 363 | volatile uint8_t utxfcsr; /* 0x028 */ |
---|
| 364 | volatile uint8_t _res14[3]; |
---|
[3cfd520] | 365 | |
---|
[ee5769ad] | 366 | volatile uint8_t urxfcsr; /* 0x02c */ |
---|
| 367 | volatile uint8_t _res15[3]; |
---|
[3cfd520] | 368 | |
---|
[ee5769ad] | 369 | volatile uint8_t ufpdn; /* 0x030 */ |
---|
| 370 | volatile uint8_t _res16[3]; |
---|
[3cfd520] | 371 | |
---|
[ee5769ad] | 372 | volatile uint8_t uip; /* 0x034 */ |
---|
| 373 | volatile uint8_t _res17[3]; |
---|
[3cfd520] | 374 | |
---|
[ee5769ad] | 375 | volatile uint8_t uop1; /* 0x038 */ |
---|
| 376 | volatile uint8_t _res18[3]; |
---|
[3cfd520] | 377 | |
---|
[ee5769ad] | 378 | volatile uint8_t uop0; /* 0x03c */ |
---|
| 379 | volatile uint8_t _res19[3]; |
---|
[3cfd520] | 380 | } uart_regs_t; |
---|
| 381 | |
---|
| 382 | typedef struct { |
---|
[ee5769ad] | 383 | volatile uint16_t tmr0; |
---|
| 384 | volatile uint16_t _res0; |
---|
[3cfd520] | 385 | |
---|
[ee5769ad] | 386 | volatile uint16_t trr0; |
---|
| 387 | volatile uint16_t _res1; |
---|
[3cfd520] | 388 | |
---|
[ee5769ad] | 389 | volatile uint16_t tcap0; |
---|
| 390 | volatile uint16_t _res2; |
---|
[3cfd520] | 391 | |
---|
[ee5769ad] | 392 | volatile uint16_t tcn0; |
---|
| 393 | volatile uint16_t _res3; |
---|
[3cfd520] | 394 | |
---|
[ee5769ad] | 395 | volatile uint16_t ter0; |
---|
| 396 | volatile uint16_t _res4; |
---|
[3cfd520] | 397 | |
---|
[ee5769ad] | 398 | volatile uint8_t _res40[12]; |
---|
[3cfd520] | 399 | |
---|
[ee5769ad] | 400 | volatile uint16_t tmr1; |
---|
| 401 | volatile uint16_t _res5; |
---|
[3cfd520] | 402 | |
---|
[ee5769ad] | 403 | volatile uint16_t trr1; |
---|
| 404 | volatile uint16_t _res6; |
---|
[3cfd520] | 405 | |
---|
[ee5769ad] | 406 | volatile uint16_t tcap1; |
---|
| 407 | volatile uint16_t _res7; |
---|
[3cfd520] | 408 | |
---|
[ee5769ad] | 409 | volatile uint16_t tcn1; |
---|
| 410 | volatile uint16_t _res8; |
---|
[3cfd520] | 411 | |
---|
[ee5769ad] | 412 | volatile uint16_t ter1; |
---|
| 413 | volatile uint16_t _res9; |
---|
[3cfd520] | 414 | |
---|
[ee5769ad] | 415 | volatile uint8_t _res91[12]; |
---|
[3cfd520] | 416 | |
---|
[ee5769ad] | 417 | volatile uint16_t tmr2; |
---|
| 418 | volatile uint16_t _res10; |
---|
[3cfd520] | 419 | |
---|
[ee5769ad] | 420 | volatile uint16_t trr2; |
---|
| 421 | volatile uint16_t _res11; |
---|
[3cfd520] | 422 | |
---|
[ee5769ad] | 423 | volatile uint16_t tcap2; |
---|
| 424 | volatile uint16_t _res12; |
---|
[3cfd520] | 425 | |
---|
[ee5769ad] | 426 | volatile uint16_t tcn2; |
---|
| 427 | volatile uint16_t _res13; |
---|
[3cfd520] | 428 | |
---|
[ee5769ad] | 429 | volatile uint16_t ter2; |
---|
| 430 | volatile uint16_t _res14; |
---|
[3cfd520] | 431 | |
---|
[ee5769ad] | 432 | volatile uint8_t _res140[12]; |
---|
[3cfd520] | 433 | |
---|
[ee5769ad] | 434 | volatile uint16_t tmr3; |
---|
| 435 | volatile uint16_t _res15; |
---|
[3cfd520] | 436 | |
---|
[ee5769ad] | 437 | volatile uint16_t trr3; |
---|
| 438 | volatile uint16_t _res16; |
---|
[3cfd520] | 439 | |
---|
[ee5769ad] | 440 | volatile uint16_t tcap3; |
---|
| 441 | volatile uint16_t _res17; |
---|
[3cfd520] | 442 | |
---|
[ee5769ad] | 443 | volatile uint16_t tcn3; |
---|
| 444 | volatile uint16_t _res18; |
---|
[3cfd520] | 445 | |
---|
[ee5769ad] | 446 | volatile uint16_t ter3; |
---|
| 447 | volatile uint16_t _res19; |
---|
[3cfd520] | 448 | |
---|
[ee5769ad] | 449 | volatile uint8_t _res190[12]; |
---|
[3cfd520] | 450 | |
---|
[ee5769ad] | 451 | volatile uint16_t wrrr; |
---|
| 452 | volatile uint16_t _res20; |
---|
[3cfd520] | 453 | |
---|
[ee5769ad] | 454 | volatile uint16_t wirr; |
---|
| 455 | volatile uint16_t _res21; |
---|
[3cfd520] | 456 | |
---|
[ee5769ad] | 457 | volatile uint16_t wcr; |
---|
| 458 | volatile uint16_t _res22; |
---|
[3cfd520] | 459 | |
---|
[ee5769ad] | 460 | volatile uint16_t wer; |
---|
| 461 | volatile uint16_t _res23; |
---|
[3cfd520] | 462 | } timer_regs_t; |
---|
| 463 | |
---|
| 464 | typedef struct { |
---|
[ee5769ad] | 465 | volatile uint32_t p0b1rr; |
---|
| 466 | volatile uint32_t p1b1rr; |
---|
| 467 | volatile uint32_t p2b1rr; |
---|
| 468 | volatile uint32_t p3b1rr; |
---|
| 469 | volatile uint32_t p0b2rr; |
---|
| 470 | volatile uint32_t p1b2rr; |
---|
| 471 | volatile uint32_t p2b2rr; |
---|
| 472 | volatile uint32_t p3b2rr; |
---|
| 473 | |
---|
| 474 | volatile uint8_t p0drr; |
---|
| 475 | volatile uint8_t p1drr; |
---|
| 476 | volatile uint8_t p2drr; |
---|
| 477 | volatile uint8_t p3drr; |
---|
| 478 | |
---|
| 479 | volatile uint32_t p0b1tr; |
---|
| 480 | volatile uint32_t p1b1tr; |
---|
| 481 | volatile uint32_t p2b1tr; |
---|
| 482 | volatile uint32_t p3b1tr; |
---|
| 483 | volatile uint32_t p0b2tr; |
---|
| 484 | volatile uint32_t p1b2tr; |
---|
| 485 | volatile uint32_t p2b2tr; |
---|
| 486 | volatile uint32_t p3b2tr; |
---|
| 487 | |
---|
| 488 | volatile uint8_t p0dtr; |
---|
| 489 | volatile uint8_t p1dtr; |
---|
| 490 | volatile uint8_t p2dtr; |
---|
| 491 | volatile uint8_t p3dtr; |
---|
| 492 | |
---|
| 493 | volatile uint16_t p0cr; |
---|
| 494 | volatile uint16_t p1cr; |
---|
| 495 | volatile uint16_t p2cr; |
---|
| 496 | volatile uint16_t p3cr; |
---|
| 497 | volatile uint16_t p0icr; |
---|
| 498 | volatile uint16_t p1icr; |
---|
| 499 | volatile uint16_t p2icr; |
---|
| 500 | volatile uint16_t p3icr; |
---|
| 501 | volatile uint16_t p0gmr; |
---|
| 502 | volatile uint16_t p1gmr; |
---|
| 503 | volatile uint16_t p2gmr; |
---|
| 504 | volatile uint16_t p3gmr; |
---|
| 505 | volatile uint16_t p0gmt; |
---|
| 506 | volatile uint16_t p1gmt; |
---|
| 507 | volatile uint16_t p2gmt; |
---|
| 508 | volatile uint16_t p3gmt; |
---|
| 509 | |
---|
| 510 | volatile uint8_t _res0; |
---|
| 511 | volatile uint8_t pgmts; |
---|
| 512 | volatile uint8_t pgmta; |
---|
| 513 | volatile uint8_t _res1; |
---|
| 514 | volatile uint8_t p0gcir; |
---|
| 515 | volatile uint8_t p1gcir; |
---|
| 516 | volatile uint8_t p2gcir; |
---|
| 517 | volatile uint8_t p3gcir; |
---|
| 518 | volatile uint8_t p0gcit; |
---|
| 519 | volatile uint8_t p1gcit; |
---|
| 520 | volatile uint8_t p2gcit; |
---|
| 521 | volatile uint8_t p3gcit; |
---|
| 522 | volatile uint8_t _res3[3]; |
---|
| 523 | volatile uint8_t pgcitsr; |
---|
| 524 | volatile uint8_t _res4[3]; |
---|
| 525 | volatile uint8_t pdcsr; |
---|
| 526 | |
---|
| 527 | volatile uint16_t p0psr; |
---|
| 528 | volatile uint16_t p1psr; |
---|
| 529 | volatile uint16_t p2psr; |
---|
| 530 | volatile uint16_t p3psr; |
---|
| 531 | volatile uint16_t pasr; |
---|
| 532 | volatile uint8_t _res5; |
---|
| 533 | volatile uint8_t plcr; |
---|
| 534 | volatile uint16_t _res6; |
---|
| 535 | volatile uint16_t pdrqr; |
---|
| 536 | volatile uint16_t p0sdr; |
---|
| 537 | volatile uint16_t p1sdr; |
---|
| 538 | volatile uint16_t p2sdr; |
---|
| 539 | volatile uint16_t p3sdr; |
---|
| 540 | volatile uint16_t _res7; |
---|
| 541 | volatile uint16_t pcsr; |
---|
[3cfd520] | 542 | } plic_regs_t; |
---|
| 543 | |
---|
| 544 | typedef struct { |
---|
[ee5769ad] | 545 | volatile uint32_t ecr; |
---|
| 546 | volatile uint32_t eir; |
---|
| 547 | volatile uint32_t eimr; |
---|
| 548 | volatile uint32_t ivsr; |
---|
| 549 | volatile uint32_t rdar; |
---|
| 550 | volatile uint32_t tdar; |
---|
| 551 | volatile uint32_t _res0[10]; |
---|
| 552 | volatile uint32_t mmfr; |
---|
| 553 | volatile uint32_t mscr; |
---|
| 554 | volatile uint32_t _res1[17]; |
---|
| 555 | volatile uint32_t frbr; |
---|
| 556 | volatile uint32_t frsr; |
---|
| 557 | volatile uint32_t _res2[4]; |
---|
| 558 | volatile uint32_t tfwr; |
---|
| 559 | volatile uint32_t _res3[1]; |
---|
| 560 | volatile uint32_t tfsr; |
---|
| 561 | volatile uint32_t _res4[21]; |
---|
| 562 | volatile uint32_t rcr; |
---|
| 563 | volatile uint32_t mflr; |
---|
| 564 | volatile uint32_t _res5[14]; |
---|
| 565 | volatile uint32_t tcr; |
---|
| 566 | volatile uint32_t _res6[158]; |
---|
| 567 | volatile uint32_t malr; |
---|
| 568 | volatile uint32_t maur; |
---|
| 569 | volatile uint32_t htur; |
---|
| 570 | volatile uint32_t htlr; |
---|
| 571 | volatile uint32_t erdsr; |
---|
| 572 | volatile uint32_t etdsr; |
---|
| 573 | volatile uint32_t emrbr; |
---|
| 574 | /* volatile uint8_t fifo[448]; */ |
---|
[3cfd520] | 575 | } enet_regs_t; |
---|
| 576 | |
---|
| 577 | typedef struct { |
---|
[ee5769ad] | 578 | volatile uint16_t _res0; |
---|
| 579 | volatile uint16_t fnr; |
---|
| 580 | volatile uint16_t _res1; |
---|
| 581 | volatile uint16_t fnmr; |
---|
| 582 | volatile uint16_t _res2; |
---|
| 583 | volatile uint16_t rfmr; |
---|
| 584 | volatile uint16_t _res3; |
---|
| 585 | volatile uint16_t rfmmr; |
---|
[023f1dd9] | 586 | volatile uint8_t _res4[3]; |
---|
[ee5769ad] | 587 | volatile uint8_t far; |
---|
| 588 | volatile uint32_t asr; |
---|
| 589 | volatile uint32_t drr1; |
---|
| 590 | volatile uint32_t drr2; |
---|
[023f1dd9] | 591 | volatile uint16_t _res5; |
---|
[ee5769ad] | 592 | volatile uint16_t specr; |
---|
| 593 | volatile uint16_t _res6; |
---|
| 594 | volatile uint16_t ep0sr; |
---|
| 595 | |
---|
| 596 | volatile uint32_t iep0cfg; |
---|
| 597 | volatile uint32_t oep0cfg; |
---|
| 598 | volatile uint32_t ep1cfg; |
---|
| 599 | volatile uint32_t ep2cfg; |
---|
| 600 | volatile uint32_t ep3cfg; |
---|
| 601 | volatile uint32_t ep4cfg; |
---|
| 602 | volatile uint32_t ep5cfg; |
---|
| 603 | volatile uint32_t ep6cfg; |
---|
| 604 | volatile uint32_t ep7cfg; |
---|
| 605 | volatile uint32_t ep0ctl; |
---|
| 606 | |
---|
| 607 | volatile uint16_t _res7; |
---|
| 608 | volatile uint16_t ep1ctl; |
---|
| 609 | volatile uint16_t _res8; |
---|
| 610 | volatile uint16_t ep2ctl; |
---|
| 611 | volatile uint16_t _res9; |
---|
| 612 | volatile uint16_t ep3ctl; |
---|
| 613 | volatile uint16_t _res10; |
---|
| 614 | volatile uint16_t ep4ctl; |
---|
| 615 | volatile uint16_t _res11; |
---|
| 616 | volatile uint16_t ep5ctl; |
---|
| 617 | volatile uint16_t _res12; |
---|
| 618 | volatile uint16_t ep6ctl; |
---|
| 619 | volatile uint16_t _res13; |
---|
| 620 | volatile uint16_t ep7ctl; |
---|
| 621 | |
---|
| 622 | volatile uint32_t ep0isr; |
---|
| 623 | |
---|
| 624 | volatile uint16_t _res14; |
---|
| 625 | volatile uint16_t ep1isr; |
---|
| 626 | volatile uint16_t _res15; |
---|
| 627 | volatile uint16_t ep2isr; |
---|
| 628 | volatile uint16_t _res16; |
---|
| 629 | volatile uint16_t ep3isr; |
---|
| 630 | volatile uint16_t _res17; |
---|
| 631 | volatile uint16_t ep4isr; |
---|
| 632 | volatile uint16_t _res18; |
---|
| 633 | volatile uint16_t ep5isr; |
---|
| 634 | volatile uint16_t _res19; |
---|
| 635 | volatile uint16_t ep6isr; |
---|
| 636 | volatile uint16_t _res20; |
---|
| 637 | volatile uint16_t ep7isr; |
---|
| 638 | |
---|
| 639 | volatile uint32_t ep0imr; |
---|
| 640 | |
---|
| 641 | volatile uint16_t _res21; |
---|
| 642 | volatile uint16_t ep1imr; |
---|
| 643 | volatile uint16_t _res22; |
---|
| 644 | volatile uint16_t ep2imr; |
---|
| 645 | volatile uint16_t _res23; |
---|
| 646 | volatile uint16_t ep3imr; |
---|
| 647 | volatile uint16_t _res24; |
---|
| 648 | volatile uint16_t ep4imr; |
---|
| 649 | volatile uint16_t _res25; |
---|
| 650 | volatile uint16_t ep5imr; |
---|
| 651 | volatile uint16_t _res26; |
---|
| 652 | volatile uint16_t ep6imr; |
---|
| 653 | volatile uint16_t _res27; |
---|
| 654 | volatile uint16_t ep7imr; |
---|
| 655 | |
---|
| 656 | volatile uint32_t ep0dr; |
---|
| 657 | volatile uint32_t ep1dr; |
---|
| 658 | volatile uint32_t ep2dr; |
---|
| 659 | volatile uint32_t ep3dr; |
---|
| 660 | volatile uint32_t ep4dr; |
---|
| 661 | volatile uint32_t ep5dr; |
---|
| 662 | volatile uint32_t ep6dr; |
---|
| 663 | volatile uint32_t ep7dr; |
---|
| 664 | |
---|
| 665 | volatile uint16_t _res28; |
---|
| 666 | volatile uint16_t ep0dpr; |
---|
| 667 | volatile uint16_t _res29; |
---|
| 668 | volatile uint16_t ep1dpr; |
---|
| 669 | volatile uint16_t _res30; |
---|
| 670 | volatile uint16_t ep2dpr; |
---|
| 671 | volatile uint16_t _res31; |
---|
| 672 | volatile uint16_t ep3dpr; |
---|
| 673 | volatile uint16_t _res32; |
---|
| 674 | volatile uint16_t ep4dpr; |
---|
| 675 | volatile uint16_t _res33; |
---|
| 676 | volatile uint16_t ep5dpr; |
---|
| 677 | volatile uint16_t _res34; |
---|
| 678 | volatile uint16_t ep6dpr; |
---|
| 679 | volatile uint16_t _res35; |
---|
| 680 | volatile uint16_t ep7dpr; |
---|
| 681 | /* uint8_t ram[1024]; */ |
---|
[3cfd520] | 682 | } usb_regs_t; |
---|
| 683 | |
---|
| 684 | extern intctrl_regs_t *g_intctrl_regs; |
---|
| 685 | extern chipsel_regs_t *g_chipsel_regs; |
---|
| 686 | extern gpio_regs_t *g_gpio_regs; |
---|
| 687 | extern qspi_regs_t *g_qspi_regs; |
---|
| 688 | extern pwm_regs_t *g_pwm_regs; |
---|
| 689 | extern dma_regs_t *g_dma_regs; |
---|
| 690 | extern uart_regs_t *g_uart0_regs; |
---|
| 691 | extern uart_regs_t *g_uart1_regs; |
---|
| 692 | extern timer_regs_t *g_timer_regs; |
---|
| 693 | extern plic_regs_t *g_plic_regs; |
---|
| 694 | extern enet_regs_t *g_enet_regs; |
---|
| 695 | extern usb_regs_t *g_usb_regs; |
---|
| 696 | |
---|
| 697 | #endif /* ASM */ |
---|
| 698 | |
---|
| 699 | #endif /* __MCF5272_H__ */ |
---|