1 | /* |
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2 | * COPYRIGHT (c) 1989-2008. |
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3 | * On-Line Applications Research Corporation (OAR). |
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4 | * |
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5 | * The license and distribution terms for this file may be |
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6 | * found in the file LICENSE in this distribution or at |
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7 | * |
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8 | * http://www.rtems.com/license/LICENSE. |
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9 | * |
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10 | * $Id$ |
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11 | */ |
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12 | |
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13 | #include <rtems.h> |
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14 | #include <mcf5235/mcf5235.h> |
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15 | |
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16 | /* |
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17 | * Default value for the cacr is set by the BSP |
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18 | */ |
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19 | extern uint32_t cacr_mode; |
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20 | |
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21 | /* |
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22 | * Cannot be frozen |
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23 | */ |
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24 | void _CPU_cache_freeze_data(void) {} |
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25 | void _CPU_cache_unfreeze_data(void) {} |
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26 | void _CPU_cache_freeze_instruction(void) {} |
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27 | void _CPU_cache_unfreeze_instruction(void) {} |
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28 | |
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29 | /* |
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30 | * Write-through data cache -- flushes are unnecessary |
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31 | */ |
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32 | void _CPU_cache_flush_1_data_line(const void *d_addr) {} |
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33 | void _CPU_cache_flush_entire_data(void) {} |
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34 | |
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35 | void _CPU_cache_enable_instruction(void) |
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36 | { |
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37 | rtems_interrupt_level level; |
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38 | |
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39 | rtems_interrupt_disable(level); |
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40 | cacr_mode &= ~MCF5XXX_CACR_DIDI; |
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41 | m68k_set_cacr(cacr_mode); |
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42 | rtems_interrupt_enable(level); |
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43 | } |
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44 | |
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45 | void _CPU_cache_disable_instruction(void) |
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46 | { |
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47 | rtems_interrupt_level level; |
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48 | |
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49 | rtems_interrupt_disable(level); |
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50 | cacr_mode |= MCF5XXX_CACR_DIDI; |
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51 | m68k_set_cacr(cacr_mode); |
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52 | rtems_interrupt_enable(level); |
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53 | } |
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54 | |
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55 | void _CPU_cache_invalidate_entire_instruction(void) |
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56 | { |
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57 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); |
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58 | } |
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59 | |
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60 | void _CPU_cache_invalidate_1_instruction_line(const void *addr) |
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61 | { |
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62 | /* |
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63 | * Top half of cache is I-space |
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64 | */ |
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65 | addr = (void *)((int)addr | 0x400); |
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66 | asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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67 | } |
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68 | |
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69 | void _CPU_cache_enable_data(void) |
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70 | { |
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71 | rtems_interrupt_level level; |
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72 | |
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73 | rtems_interrupt_disable(level); |
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74 | cacr_mode &= ~MCF5XXX_CACR_DISD; |
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75 | m68k_set_cacr(cacr_mode); |
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76 | rtems_interrupt_enable(level); |
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77 | } |
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78 | |
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79 | void _CPU_cache_disable_data(void) |
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80 | { |
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81 | rtems_interrupt_level level; |
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82 | |
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83 | rtems_interrupt_disable(level); |
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84 | cacr_mode |= MCF5XXX_CACR_DISD; |
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85 | m68k_set_cacr(cacr_mode); |
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86 | rtems_interrupt_enable(level); |
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87 | } |
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88 | |
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89 | void _CPU_cache_invalidate_entire_data(void) |
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90 | { |
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91 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); |
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92 | } |
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93 | |
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94 | void _CPU_cache_invalidate_1_data_line(const void *addr) |
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95 | { |
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96 | /* |
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97 | * Bottom half of cache is D-space |
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98 | */ |
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99 | addr = (void *)((int)addr & ~0x400); |
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100 | asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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101 | } |
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