[c01e72b] | 1 | /* |
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| 2 | * COPYRIGHT (c) 1989-2008. |
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| 3 | * On-Line Applications Research Corporation (OAR). |
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| 4 | * |
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| 5 | * The license and distribution terms for this file may be |
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| 6 | * found in the file LICENSE in this distribution or at |
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[c499856] | 7 | * http://www.rtems.org/license/LICENSE. |
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[c01e72b] | 8 | */ |
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| 9 | |
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| 10 | #include <rtems.h> |
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| 11 | #include <mcf5235/mcf5235.h> |
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[e7c4f77] | 12 | #include "cache_.h" |
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[023f1dd9] | 13 | |
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[c01e72b] | 14 | /* |
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| 15 | * Default value for the cacr is set by the BSP |
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| 16 | */ |
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| 17 | extern uint32_t cacr_mode; |
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| 18 | |
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| 19 | /* |
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| 20 | * Cannot be frozen |
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| 21 | */ |
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| 22 | void _CPU_cache_freeze_data(void) {} |
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| 23 | void _CPU_cache_unfreeze_data(void) {} |
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| 24 | void _CPU_cache_freeze_instruction(void) {} |
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| 25 | void _CPU_cache_unfreeze_instruction(void) {} |
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| 26 | |
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| 27 | /* |
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| 28 | * Write-through data cache -- flushes are unnecessary |
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| 29 | */ |
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| 30 | void _CPU_cache_flush_1_data_line(const void *d_addr) {} |
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| 31 | void _CPU_cache_flush_entire_data(void) {} |
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| 32 | |
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| 33 | void _CPU_cache_enable_instruction(void) |
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| 34 | { |
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| 35 | rtems_interrupt_level level; |
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| 36 | |
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| 37 | rtems_interrupt_disable(level); |
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| 38 | cacr_mode &= ~MCF5XXX_CACR_DIDI; |
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| 39 | m68k_set_cacr(cacr_mode); |
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| 40 | rtems_interrupt_enable(level); |
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| 41 | } |
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| 42 | |
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| 43 | void _CPU_cache_disable_instruction(void) |
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| 44 | { |
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| 45 | rtems_interrupt_level level; |
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| 46 | |
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| 47 | rtems_interrupt_disable(level); |
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| 48 | cacr_mode |= MCF5XXX_CACR_DIDI; |
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| 49 | m68k_set_cacr(cacr_mode); |
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| 50 | rtems_interrupt_enable(level); |
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| 51 | } |
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| 52 | |
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| 53 | void _CPU_cache_invalidate_entire_instruction(void) |
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| 54 | { |
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| 55 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); |
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| 56 | } |
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| 57 | |
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| 58 | void _CPU_cache_invalidate_1_instruction_line(const void *addr) |
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| 59 | { |
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| 60 | /* |
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| 61 | * Top half of cache is I-space |
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| 62 | */ |
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| 63 | addr = (void *)((int)addr | 0x400); |
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[8525cff] | 64 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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[c01e72b] | 65 | } |
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| 66 | |
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| 67 | void _CPU_cache_enable_data(void) |
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| 68 | { |
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| 69 | rtems_interrupt_level level; |
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| 70 | |
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| 71 | rtems_interrupt_disable(level); |
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| 72 | cacr_mode &= ~MCF5XXX_CACR_DISD; |
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| 73 | m68k_set_cacr(cacr_mode); |
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| 74 | rtems_interrupt_enable(level); |
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| 75 | } |
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| 76 | |
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| 77 | void _CPU_cache_disable_data(void) |
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| 78 | { |
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| 79 | rtems_interrupt_level level; |
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| 80 | |
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| 81 | rtems_interrupt_disable(level); |
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| 82 | cacr_mode |= MCF5XXX_CACR_DISD; |
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| 83 | m68k_set_cacr(cacr_mode); |
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| 84 | rtems_interrupt_enable(level); |
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| 85 | } |
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| 86 | |
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| 87 | void _CPU_cache_invalidate_entire_data(void) |
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| 88 | { |
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| 89 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); |
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| 90 | } |
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| 91 | |
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| 92 | void _CPU_cache_invalidate_1_data_line(const void *addr) |
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| 93 | { |
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| 94 | /* |
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| 95 | * Bottom half of cache is D-space |
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| 96 | */ |
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| 97 | addr = (void *)((int)addr & ~0x400); |
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[8525cff] | 98 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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[c01e72b] | 99 | } |
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