1 | /* MCF5206e MBUS module (I2C bus) driver |
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2 | * |
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3 | * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia |
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4 | * Author: Victor V. Vengerov <vvv@oktet.ru> |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution or at |
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8 | * |
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9 | * http://www.rtems.com/license/LICENSE. |
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10 | * |
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11 | * @(#) $Id$ |
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12 | */ |
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13 | |
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14 | #include "mcf5206/mcfmbus.h" |
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15 | #include "mcf5206/mcf5206e.h" |
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16 | #include "i2c.h" |
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17 | |
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18 | /* Events of I2C machine */ |
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19 | typedef enum i2c_event { |
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20 | EVENT_NONE, /* Spurious event */ |
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21 | EVENT_TRANSFER, /* Start new transfer */ |
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22 | EVENT_NEXTMSG, /* Start processing of next message in transfer */ |
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23 | EVENT_ACK, /* Sending finished with ACK */ |
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24 | EVENT_NACK, /* Sending finished with NACK */ |
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25 | EVENT_TIMEOUT, /* Timeout occured */ |
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26 | EVENT_DATA_RECV, /* Data received */ |
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27 | EVENT_ARB_LOST, /* Arbitration lost */ |
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28 | EVENT_SLAVE /* Addressed as a slave */ |
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29 | } i2c_event; |
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30 | |
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31 | static mcfmbus *mbus; |
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32 | |
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33 | /*** Auxillary primitives ***/ |
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34 | |
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35 | /* Change state of finite state machine */ |
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36 | #define next_state(bus,new_state) \ |
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37 | do { \ |
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38 | (bus)->state = (new_state); \ |
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39 | } while (0) |
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40 | |
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41 | /* Initiate start condition on the I2C bus */ |
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42 | #define mcfmbus_start(bus) \ |
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43 | do { \ |
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44 | *MCF5206E_MBCR((bus)->base) |= MCF5206E_MBCR_MSTA; \ |
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45 | } while (0) |
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46 | |
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47 | /* Initiate stop condition on the I2C bus */ |
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48 | #define mcfmbus_stop(bus) \ |
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49 | do { \ |
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50 | *MCF5206E_MBCR((bus)->base) &= ~MCF5206E_MBCR_MSTA; \ |
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51 | } while (0) |
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52 | |
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53 | /* Initiate repeat start condition on the I2C bus */ |
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54 | #define mcfmbus_rstart(bus) \ |
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55 | do { \ |
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56 | *MCF5206E_MBCR((bus)->base) |= MCF5206E_MBCR_RSTA; \ |
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57 | } while (0) |
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58 | |
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59 | /* Send byte to the bus */ |
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60 | #define mcfmbus_send(bus,byte) \ |
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61 | do { \ |
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62 | *MCF5206E_MBDR((bus)->base) = (byte); \ |
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63 | } while (0) |
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64 | |
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65 | /* Set transmit mode */ |
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66 | #define mcfmbus_tx_mode(bus) \ |
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67 | do { \ |
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68 | *MCF5206E_MBCR((bus)->base) |= MCF5206E_MBCR_MTX; \ |
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69 | } while (0) |
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70 | |
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71 | /* Set receive mode */ |
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72 | #define mcfmbus_rx_mode(bus) \ |
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73 | do { \ |
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74 | *MCF5206E_MBCR((bus)->base) &= ~MCF5206E_MBCR_MTX; \ |
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75 | (void)*MCF5206E_MBDR((bus)->base); \ |
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76 | } while (0) |
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77 | |
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78 | |
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79 | /* Transmit acknowledge when byte received */ |
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80 | #define mcfmbus_send_ack(bus) \ |
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81 | do { \ |
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82 | *MCF5206E_MBCR((bus)->base) &= ~MCF5206E_MBCR_TXAK; \ |
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83 | } while (0) |
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84 | |
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85 | /* DO NOT transmit acknowledge when byte received */ |
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86 | #define mcfmbus_send_nack(bus) \ |
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87 | do { \ |
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88 | *MCF5206E_MBCR((bus)->base) |= MCF5206E_MBCR_TXAK; \ |
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89 | } while (0) |
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90 | |
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91 | #define mcfmbus_error(bus,err_status) \ |
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92 | do { \ |
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93 | do { \ |
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94 | (bus)->cmsg->status = (err_status); \ |
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95 | (bus)->cmsg++; \ |
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96 | } while (((bus)->cmsg - (bus)->msg < (bus)->nmsg) && \ |
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97 | ((bus)->cmsg->flags & I2C_MSG_ERRSKIP)); \ |
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98 | bus->cmsg--; \ |
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99 | } while (0) |
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100 | |
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101 | /* mcfmbus_get_event -- |
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102 | * Read MBUS module status register, determine interrupt reason and |
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103 | * return appropriate event. |
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104 | * |
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105 | * PARAMETERS: |
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106 | * bus - pointer to MBUS module descriptor structure |
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107 | * |
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108 | * RETURNS: |
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109 | * event code |
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110 | */ |
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111 | static i2c_event |
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112 | mcfmbus_get_event(mcfmbus *bus) |
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113 | { |
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114 | i2c_event event; |
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115 | uint8_t status, control; |
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116 | rtems_interrupt_level level; |
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117 | rtems_interrupt_disable(level); |
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118 | status = *MCF5206E_MBSR(bus->base); |
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119 | control = *MCF5206E_MBCR(bus->base); |
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120 | if (status & MCF5206E_MBSR_MIF) /* Interrupt occured */ |
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121 | { |
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122 | if (status & MCF5206E_MBSR_MAAS) |
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123 | { |
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124 | event = EVENT_SLAVE; |
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125 | *MCF5206E_MBCR(bus->base) = control; /* To clear Addressed As Slave |
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126 | condition */ |
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127 | } |
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128 | else if (status & MCF5206E_MBSR_MAL) /* Arbitration lost */ |
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129 | { |
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130 | *MCF5206E_MBSR(bus->base) = status & ~MCF5206E_MBSR_MAL; |
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131 | event = EVENT_ARB_LOST; |
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132 | } |
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133 | else if (control & MCF5206E_MBCR_MTX) /* Trasmit mode */ |
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134 | { |
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135 | if (status & MCF5206E_MBSR_RXAK) |
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136 | event = EVENT_NACK; |
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137 | else |
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138 | event = EVENT_ACK; |
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139 | } |
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140 | else /* Received */ |
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141 | { |
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142 | event = EVENT_DATA_RECV; |
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143 | } |
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144 | |
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145 | /* Clear interrupt condition */ |
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146 | *MCF5206E_MBSR(bus->base) &= ~MCF5206E_MBSR_MIF; |
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147 | } |
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148 | else |
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149 | { |
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150 | event = EVENT_NONE; |
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151 | } |
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152 | rtems_interrupt_enable(level); |
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153 | return event; |
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154 | } |
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155 | |
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156 | static void |
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157 | mcfmbus_machine_error(mcfmbus *bus, i2c_event event) |
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158 | { |
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159 | return; |
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160 | } |
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161 | |
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162 | /* mcfmbus_machine -- |
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163 | * finite state machine for I2C bus protocol |
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164 | * |
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165 | * PARAMETERS: |
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166 | * bus - pointer to ColdFire MBUS descriptor structure |
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167 | * event - I2C event |
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168 | * |
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169 | * RETURNS: |
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170 | * none |
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171 | */ |
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172 | static void |
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173 | mcfmbus_machine(mcfmbus *bus, i2c_event event) |
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174 | { |
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175 | uint8_t b; |
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176 | switch (bus->state) |
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177 | { |
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178 | case STATE_IDLE: |
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179 | switch (event) |
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180 | { |
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181 | case EVENT_NEXTMSG: /* Start new message processing */ |
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182 | bus->cmsg++; |
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183 | /* FALLTHRU */ |
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184 | |
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185 | case EVENT_TRANSFER: /* Initiate new transfer */ |
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186 | if (bus->cmsg - bus->msg >= bus->nmsg) |
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187 | { |
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188 | mcfmbus_stop(bus); |
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189 | next_state(bus, STATE_IDLE); |
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190 | bus->msg = bus->cmsg = NULL; |
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191 | bus->nmsg = bus->byte = 0; |
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192 | bus->done(bus->done_arg); |
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193 | break; |
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194 | } |
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195 | |
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196 | /* Initiate START or REPEATED START condition on the bus */ |
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197 | if (event == EVENT_TRANSFER) |
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198 | { |
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199 | mcfmbus_start(bus); |
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200 | } |
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201 | else /* (event == EVENT_NEXTMSG) */ |
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202 | { |
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203 | mcfmbus_rstart(bus); |
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204 | } |
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205 | |
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206 | bus->byte = 0; |
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207 | mcfmbus_tx_mode(bus); |
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208 | |
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209 | /* Initiate slave address sending */ |
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210 | if (bus->cmsg->flags & I2C_MSG_ADDR_10) |
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211 | { |
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212 | i2c_address a = bus->cmsg->addr; |
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213 | b = 0xf0 | (((a >> 8) & 0x03) << 1); |
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214 | if (bus->cmsg->flags & I2C_MSG_WR) |
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215 | { |
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216 | mcfmbus_send(bus, b); |
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217 | next_state(bus, STATE_ADDR_1_W); |
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218 | } |
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219 | else |
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220 | { |
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221 | mcfmbus_send(bus, b | 1); |
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222 | next_state(bus, STATE_ADDR_1_R); |
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223 | } |
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224 | } |
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225 | else |
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226 | { |
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227 | b = (bus->cmsg->addr & ~0x01); |
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228 | |
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229 | if (bus->cmsg->flags & I2C_MSG_WR) |
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230 | { |
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231 | next_state(bus, STATE_SENDING); |
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232 | } |
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233 | else |
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234 | { |
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235 | next_state(bus, STATE_ADDR_7); |
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236 | b |= 1; |
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237 | } |
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238 | |
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239 | mcfmbus_send(bus, b); |
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240 | } |
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241 | break; |
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242 | |
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243 | default: |
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244 | mcfmbus_machine_error(bus, event); |
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245 | break; |
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246 | } |
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247 | break; |
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248 | |
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249 | case STATE_ADDR_7: |
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250 | switch (event) |
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251 | { |
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252 | case EVENT_ACK: |
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253 | mcfmbus_rx_mode(bus); |
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254 | if (bus->cmsg->len <= 1) |
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255 | mcfmbus_send_nack(bus); |
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256 | else |
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257 | mcfmbus_send_ack(bus); |
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258 | next_state(bus, STATE_RECEIVING); |
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259 | break; |
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260 | |
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261 | case EVENT_NACK: |
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262 | mcfmbus_error(bus, I2C_NO_DEVICE); |
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263 | next_state(bus, STATE_IDLE); |
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264 | mcfmbus_machine(bus, EVENT_NEXTMSG); |
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265 | break; |
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266 | |
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267 | case EVENT_ARB_LOST: |
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268 | mcfmbus_error(bus, I2C_ARBITRATION_LOST); |
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269 | next_state(bus, STATE_IDLE); |
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270 | mcfmbus_machine(bus, EVENT_NEXTMSG); |
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271 | break; |
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272 | |
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273 | default: |
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274 | mcfmbus_machine_error(bus, event); |
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275 | break; |
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276 | } |
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277 | break; |
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278 | |
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279 | case STATE_ADDR_1_R: |
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280 | case STATE_ADDR_1_W: |
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281 | switch (event) |
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282 | { |
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283 | case EVENT_ACK: |
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284 | { |
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285 | uint8_t b = (bus->cmsg->addr & 0xff); |
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286 | mcfmbus_send(bus, b); |
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287 | if (bus->state == STATE_ADDR_1_W) |
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288 | { |
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289 | next_state(bus, STATE_SENDING); |
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290 | } |
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291 | else |
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292 | { |
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293 | i2c_address a; |
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294 | mcfmbus_rstart(bus); |
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295 | mcfmbus_tx_mode(bus); |
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296 | a = bus->cmsg->addr; |
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297 | b = 0xf0 | (((a >> 8) & 0x03) << 1) | 1; |
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298 | mcfmbus_send(bus, b); |
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299 | next_state(bus, STATE_ADDR_7); |
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300 | } |
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301 | break; |
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302 | } |
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303 | |
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304 | case EVENT_NACK: |
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305 | mcfmbus_error(bus, I2C_NO_DEVICE); |
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306 | next_state(bus, STATE_IDLE); |
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307 | mcfmbus_machine(bus, EVENT_NEXTMSG); |
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308 | break; |
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309 | |
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310 | case EVENT_ARB_LOST: |
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311 | mcfmbus_error(bus, I2C_ARBITRATION_LOST); |
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312 | next_state(bus, STATE_IDLE); |
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313 | mcfmbus_machine(bus, EVENT_NEXTMSG); |
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314 | break; |
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315 | |
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316 | default: |
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317 | mcfmbus_machine_error(bus, event); |
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318 | break; |
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319 | } |
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320 | break; |
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321 | |
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322 | case STATE_SENDING: |
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323 | switch (event) |
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324 | { |
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325 | case EVENT_ACK: |
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326 | if (bus->byte == bus->cmsg->len) |
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327 | { |
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328 | next_state(bus, STATE_IDLE); |
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329 | mcfmbus_machine(bus, EVENT_NEXTMSG); |
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330 | } |
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331 | else |
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332 | { |
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333 | mcfmbus_send(bus, bus->cmsg->buf[bus->byte++]); |
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334 | next_state(bus, STATE_SENDING); |
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335 | } |
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336 | break; |
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337 | |
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338 | case EVENT_NACK: |
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339 | if (bus->byte == 0) |
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340 | { |
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341 | mcfmbus_error(bus, I2C_NO_DEVICE); |
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342 | } |
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343 | else |
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344 | { |
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345 | mcfmbus_error(bus, I2C_NO_ACKNOWLEDGE); |
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346 | } |
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347 | next_state(bus, STATE_IDLE); |
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348 | mcfmbus_machine(bus, EVENT_NEXTMSG); |
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349 | break; |
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350 | |
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351 | case EVENT_ARB_LOST: |
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352 | mcfmbus_error(bus, I2C_ARBITRATION_LOST); |
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353 | next_state(bus, STATE_IDLE); |
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354 | mcfmbus_machine(bus, EVENT_NEXTMSG); |
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355 | break; |
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356 | |
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357 | default: |
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358 | mcfmbus_machine_error(bus, event); |
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359 | break; |
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360 | |
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361 | } |
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362 | break; |
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363 | |
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364 | case STATE_RECEIVING: |
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365 | switch (event) |
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366 | { |
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367 | case EVENT_DATA_RECV: |
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368 | if (bus->cmsg->len - bus->byte <= 2) |
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369 | { |
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370 | mcfmbus_send_nack(bus); |
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371 | if (bus->cmsg->len - bus->byte <= 1) |
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372 | { |
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373 | if (bus->cmsg - bus->msg + 1 == bus->nmsg) |
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374 | mcfmbus_stop(bus); |
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375 | else |
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376 | mcfmbus_rstart(bus); |
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377 | } |
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378 | } |
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379 | else |
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380 | { |
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381 | mcfmbus_send_ack(bus); |
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382 | } |
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383 | bus->cmsg->buf[bus->byte++] = *MCF5206E_MBDR(bus->base); |
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384 | if (bus->cmsg->len == bus->byte) |
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385 | { |
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386 | next_state(bus,STATE_IDLE); |
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387 | mcfmbus_machine(bus, EVENT_NEXTMSG); |
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388 | } |
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389 | else |
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390 | { |
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391 | next_state(bus,STATE_RECEIVING); |
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392 | } |
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393 | break; |
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394 | |
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395 | case EVENT_ARB_LOST: |
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396 | mcfmbus_error(bus, I2C_ARBITRATION_LOST); |
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397 | next_state(bus, STATE_IDLE); |
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398 | mcfmbus_machine(bus, EVENT_NEXTMSG); |
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399 | break; |
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400 | |
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401 | default: |
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402 | mcfmbus_machine_error(bus, event); |
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403 | break; |
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404 | } |
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405 | break; |
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406 | } |
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407 | } |
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408 | |
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409 | /* mcfmbus_interrupt_handler -- |
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410 | * MBUS module interrupt handler routine |
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411 | * |
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412 | * PARAMETERS: |
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413 | * vector - interrupt vector number (not used) |
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414 | * |
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415 | * RETURNS: |
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416 | * none |
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417 | */ |
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418 | rtems_isr |
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419 | mcfmbus_interrupt_handler(rtems_vector_number vector) |
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420 | { |
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421 | i2c_event event; |
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422 | event = mcfmbus_get_event(mbus); |
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423 | mcfmbus_machine(mbus, event); |
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424 | } |
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425 | |
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426 | /* mcfmbus_poll -- |
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427 | * MBUS module poll routine; used to poll events when I2C driver |
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428 | * operates in poll-driven mode. |
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429 | * |
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430 | * PARAMETERS: |
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431 | * none |
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432 | * |
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433 | * RETURNS: |
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434 | * none |
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435 | */ |
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436 | void |
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437 | mcfmbus_poll(mcfmbus *bus) |
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438 | { |
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439 | i2c_event event; |
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440 | event = mcfmbus_get_event(bus); |
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441 | if (event != EVENT_NONE) |
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442 | mcfmbus_machine(bus, event); |
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443 | } |
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444 | |
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445 | /* mcfmbus_select_clock_divider -- |
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446 | * Select divider for system clock which is used for I2C bus clock |
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447 | * generation. Not each divider can be selected for I2C bus; this |
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448 | * function select nearest larger or equal divider. |
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449 | * |
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450 | * PARAMETERS: |
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451 | * i2c_bus - pointer to the bus descriptor structure |
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452 | * divider - system frequency divider for I2C serial clock. |
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453 | * RETURNS: |
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454 | * RTEMS_SUCCESSFUL, if operation performed successfully, or |
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455 | * RTEMS error code when failed. |
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456 | */ |
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457 | rtems_status_code |
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458 | mcfmbus_select_clock_divider(mcfmbus *i2c_bus, int divider) |
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459 | { |
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460 | int i; |
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461 | int mbc; |
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462 | struct { |
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463 | int divider; |
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464 | int mbc; |
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465 | } dividers[] ={ |
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466 | { 20, 0x20 }, { 22, 0x21 }, { 24, 0x22 }, { 26, 0x23 }, |
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467 | { 28, 0x00 }, { 30, 0x01 }, { 32, 0x25 }, { 34, 0x02 }, |
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468 | { 36, 0x26 }, { 40, 0x03 }, { 44, 0x04 }, { 48, 0x05 }, |
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469 | { 56, 0x06 }, { 64, 0x2a }, { 68, 0x07 }, { 72, 0x2B }, |
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470 | { 80, 0x08 }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, |
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471 | { 112, 0x2E }, { 128, 0x0B }, { 144, 0x0C }, { 160, 0x0D }, |
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472 | { 192, 0x0E }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, |
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473 | { 288, 0x10 }, { 320, 0x11 }, { 384, 0x12 }, { 448, 0x36 }, |
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474 | { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x15 }, |
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475 | { 768, 0x16 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, |
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476 | { 1152, 0x18 }, { 1280, 0x19 }, { 1536, 0x1A }, { 1792, 0x3E }, |
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477 | { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, |
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478 | { 3072, 0x1E }, { 3840, 0x1F } |
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479 | }; |
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480 | |
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481 | if (i2c_bus == NULL) |
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482 | return RTEMS_INVALID_ADDRESS; |
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483 | |
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484 | for (i = 0, mbc = -1; i < sizeof(dividers)/sizeof(dividers[0]); i++) |
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485 | { |
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486 | mbc = dividers[i].mbc; |
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487 | if (dividers[i].divider >= divider) |
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488 | { |
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489 | break; |
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490 | } |
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491 | } |
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492 | *MCF5206E_MFDR(i2c_bus->base) = mbc; |
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493 | return RTEMS_SUCCESSFUL; |
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494 | } |
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495 | |
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496 | /* mcfmbus_initialize -- |
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497 | * Initialize ColdFire MBUS I2C bus controller. |
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498 | * |
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499 | * PARAMETERS: |
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500 | * i2c_bus - pointer to the bus descriptor structure |
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501 | * base - ColdFire internal peripherial base address |
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502 | * |
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503 | * RETURNS: |
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504 | * RTEMS_SUCCESSFUL, or RTEMS error code when initialization failed. |
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505 | */ |
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506 | rtems_status_code |
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507 | mcfmbus_initialize(mcfmbus *i2c_bus, uint32_t base) |
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508 | { |
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509 | rtems_interrupt_level level; |
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510 | rtems_status_code sc; |
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511 | |
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512 | if (mbus != NULL) /* Check if already initialized */ |
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513 | return RTEMS_RESOURCE_IN_USE; |
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514 | |
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515 | if (i2c_bus == NULL) |
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516 | return RTEMS_INVALID_ADDRESS; |
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517 | |
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518 | |
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519 | i2c_bus->base = base; |
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520 | i2c_bus->state = STATE_IDLE; |
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521 | i2c_bus->msg = NULL; |
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522 | i2c_bus->cmsg = NULL; |
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523 | i2c_bus->nmsg = 0; |
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524 | i2c_bus->byte = 0; |
---|
525 | |
---|
526 | sc = rtems_interrupt_catch( |
---|
527 | mcfmbus_interrupt_handler, |
---|
528 | 24 + ((*MCF5206E_ICR(base, MCF5206E_INTR_MBUS) & MCF5206E_ICR_IL) >> |
---|
529 | MCF5206E_ICR_IL_S), |
---|
530 | &i2c_bus->oldisr |
---|
531 | ); |
---|
532 | if (sc != RTEMS_SUCCESSFUL) |
---|
533 | return sc; |
---|
534 | |
---|
535 | mbus = i2c_bus; |
---|
536 | rtems_interrupt_disable(level); |
---|
537 | *MCF5206E_IMR(base) &= ~MCF5206E_INTR_BIT(MCF5206E_INTR_MBUS); |
---|
538 | *MCF5206E_MBCR(base) = 0; |
---|
539 | *MCF5206E_MBSR(base) = 0; |
---|
540 | *MCF5206E_MBDR(base) = 0x1F; /* Maximum possible divider is 3840 */ |
---|
541 | *MCF5206E_MBCR(base) = MCF5206E_MBCR_MEN | MCF5206E_MBCR_MIEN; |
---|
542 | rtems_interrupt_enable(level); |
---|
543 | |
---|
544 | return RTEMS_SUCCESSFUL; |
---|
545 | } |
---|
546 | |
---|
547 | /* mcfmbus_i2c_transfer -- |
---|
548 | * Initiate multiple-messages transfer over I2C bus via ColdFire MBUS |
---|
549 | * controller. |
---|
550 | * |
---|
551 | * PARAMETERS: |
---|
552 | * bus - pointer to MBUS controller descriptor |
---|
553 | * nmsg - number of messages |
---|
554 | * msg - pointer to messages array |
---|
555 | * done - function which is called when transfer is finished |
---|
556 | * done_arg - arbitrary argument passed to done funciton |
---|
557 | * |
---|
558 | * RETURNS: |
---|
559 | * RTEMS_SUCCESSFUL if transfer initiated successfully, or error |
---|
560 | * code when failed. |
---|
561 | */ |
---|
562 | rtems_status_code |
---|
563 | mcfmbus_i2c_transfer(mcfmbus *bus, int nmsg, i2c_message *msg, |
---|
564 | i2c_transfer_done done, uint32_t done_arg) |
---|
565 | { |
---|
566 | if (bus != mbus) |
---|
567 | return RTEMS_NOT_CONFIGURED; |
---|
568 | |
---|
569 | bus->done = done; |
---|
570 | bus->done_arg = done_arg; |
---|
571 | bus->cmsg = bus->msg = msg; |
---|
572 | bus->nmsg = nmsg; |
---|
573 | bus->byte = 0; |
---|
574 | bus->state = STATE_IDLE; |
---|
575 | mcfmbus_machine(bus, EVENT_TRANSFER); |
---|
576 | return RTEMS_SUCCESSFUL; |
---|
577 | } |
---|
578 | |
---|
579 | |
---|
580 | /* mcfmbus_i2c_done -- |
---|
581 | * Close ColdFire MBUS I2C bus controller and release all resources. |
---|
582 | * |
---|
583 | * PARAMETERS: |
---|
584 | * bus - pointer to MBUS controller descriptor |
---|
585 | * |
---|
586 | * RETURNS: |
---|
587 | * RTEMS_SUCCESSFUL, if transfer initiated successfully, or error |
---|
588 | * code when failed. |
---|
589 | */ |
---|
590 | rtems_status_code |
---|
591 | mcfmbus_i2c_done(mcfmbus *i2c_bus) |
---|
592 | { |
---|
593 | rtems_status_code sc; |
---|
594 | uint32_t base; |
---|
595 | if (mbus == NULL) |
---|
596 | return RTEMS_NOT_CONFIGURED; |
---|
597 | |
---|
598 | if (mbus != i2c_bus) |
---|
599 | return RTEMS_INVALID_ADDRESS; |
---|
600 | |
---|
601 | base = i2c_bus->base; |
---|
602 | |
---|
603 | *MCF5206E_IMR(base) |= MCF5206E_INTR_BIT(MCF5206E_INTR_MBUS); |
---|
604 | *MCF5206E_MBCR(base) = 0; |
---|
605 | |
---|
606 | sc = rtems_interrupt_catch( |
---|
607 | i2c_bus->oldisr, |
---|
608 | 24 + ((*MCF5206E_ICR(base, MCF5206E_INTR_MBUS) & MCF5206E_ICR_IL) >> |
---|
609 | MCF5206E_ICR_IL_S), |
---|
610 | NULL |
---|
611 | ); |
---|
612 | return sc; |
---|
613 | } |
---|