[00717a3] | 1 | /* |
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| 2 | * Coldfire MCF5206e on-chip peripherial definitions. |
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| 3 | * Contents of this file based on information provided in |
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| 4 | * Motorola MCF5206e User's Manual |
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| 5 | * |
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| 6 | * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia |
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| 7 | * Author: Victor V. Vengerov <vvv@oktet.ru> |
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| 8 | * |
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| 9 | * The license and distribution terms for this file may be |
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| 10 | * found in the file LICENSE in this distribution or at |
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| 11 | * |
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[57e9580f] | 12 | * http://www.rtems.com/license/LICENSE. |
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[00717a3] | 13 | * |
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| 14 | * @(#) $Id$ |
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| 15 | */ |
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| 16 | |
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| 17 | #ifndef __MCF5206E_H__ |
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| 18 | #define __MCF5206E_H__ |
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| 19 | |
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| 20 | #ifdef ASM |
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| 21 | #define MCF5206E_REG8(base,ofs) (ofs+base) |
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| 22 | #define MCF5206E_REG16(base,ofs) (ofs+base) |
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| 23 | #define MCF5206E_REG32(base,ofs) (ofs+base) |
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| 24 | #else |
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| 25 | #define MCF5206E_REG8(base,ofs) \ |
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| 26 | (volatile rtems_unsigned8 *)((rtems_unsigned8 *)(base) + (ofs)) |
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| 27 | #define MCF5206E_REG16(base,ofs) \ |
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| 28 | (volatile rtems_unsigned16 *)((rtems_unsigned8 *)(base) + (ofs)) |
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| 29 | #define MCF5206E_REG32(base,ofs) \ |
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| 30 | (volatile rtems_unsigned32 *)((rtems_unsigned8 *)(base) + (ofs)) |
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| 31 | #endif |
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| 32 | |
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| 33 | /*** Instruction Cache -- MCF5206e User's Manual, Chapter 4 ***/ |
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| 34 | |
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| 35 | /* CACR - Cache Control Register */ |
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| 36 | #define MCF5206E_CACR_CENB (0x80000000) /* Cache Enable */ |
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| 37 | #define MCF5206E_CACR_CPDI (0x10000000) /* Disable CPUSHL Invalidation */ |
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| 38 | #define MCF5206E_CACR_CFRZ (0x08000000) /* Cache Freeze */ |
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| 39 | #define MCF5206E_CACR_CINV (0x01000000) /* Cache Invalidate */ |
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| 40 | #define MCF5206E_CACR_CEIB (0x00000400) /* Cache Enable Noncacheable |
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| 41 | instruction bursting */ |
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| 42 | #define MCF5206E_CACR_DCM (0x00000200) /* Default cache mode - noncacheable*/ |
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| 43 | #define MCF5206E_CACR_DBWE (0x00000100) /* Default Buffered Write Enable */ |
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| 44 | #define MCF5206E_CACR_DWP (0x00000020) /* Default Write Protection */ |
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| 45 | #define MCF5206E_CACR_CLNF (0x00000003) /* Cache Line Fill */ |
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| 46 | |
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| 47 | /* ACR0, ACR1 - Access Control Registers */ |
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| 48 | #define MCF5206E_ACR_AB (0xff000000) /* Address Base */ |
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| 49 | #define MCF5206E_ACR_AB_S (24) |
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| 50 | #define MCF5206E_ACR_AM (0x00ff0000) /* Address Mask */ |
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| 51 | #define MCF5206E_ACR_AM_S (16) |
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| 52 | #define MCF5206E_ACR_EN (0x00008000) /* Enable ACR */ |
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| 53 | #define MCF5206E_ACR_SM (0x00006000) /* Supervisor Mode */ |
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| 54 | #define MCF5206E_ACR_SM_USR (0x00000000) /* Match if user mode */ |
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| 55 | #define MCF5206E_ACR_SM_SVR (0x00002000) /* Match if supervisor mode */ |
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| 56 | #define MCF5206E_ACR_SM_ANY (0x00004000) /* Match Always */ |
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| 57 | #define MCF5206E_ACR_CM (0x00000040) /* Cache Mode (1 - noncacheable) */ |
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| 58 | #define MCF5206E_ACR_BUFW (0x00000020) /* Buffered Write Enable */ |
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| 59 | #define MCF5206E_ACR_WP (0x00000004) /* Write Protect */ |
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| 60 | #define MCF5206E_ACR_BASE(base) ((base) & MCF5206E_ACR_AB) |
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| 61 | #define MCF5206E_ACR_MASK(mask) (((mask) >> 8) & MCF5206E_ACR_AM) |
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| 62 | |
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| 63 | /*** SRAM -- MCF5206e User's Manual, Chapter 5 ***/ |
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| 64 | |
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| 65 | /* RAMBAR - SRAM Base Address Register */ |
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| 66 | #define MCF5206E_RAMBAR_BA (0xffffe000) /* SRAM Base Address */ |
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| 67 | #define MCF5206E_RAMBAR_WP (0x00000100) /* Write Protect */ |
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| 68 | #define MCF5206E_RAMBAR_CI (0x00000020) /* CPU Space mask */ |
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| 69 | #define MCF5206E_RAMBAR_SC (0x00000010) /* Supervisor Code Space Mask */ |
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| 70 | #define MCF5206E_RAMBAR_SD (0x00000008) /* Supervisor Data Space Mask */ |
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| 71 | #define MCF5206E_RAMBAR_UC (0x00000004) /* User Code Space Mask */ |
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| 72 | #define MCF5206E_RAMBAR_UD (0x00000002) /* User Data Space Mask */ |
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| 73 | #define MCF5206E_RAMBAR_V (0x00000001) /* Contents of RAMBAR are valid */ |
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| 74 | |
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| 75 | /*** DMA Controller Module -- MCF5206e User's Manual, Chapter 7 ***/ |
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| 76 | |
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| 77 | /* DMA Source Address Register */ |
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| 78 | #define MCF5206E_SAR(mbar,chn) MCF5206E_REG32(mbar,0x200 + ((chn) * 0x40)) |
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| 79 | |
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| 80 | /* DMA Destination Address Register */ |
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| 81 | #define MCF5206E_DAR(mbar,chn) MCF5206E_REG32(mbar,0x204 + ((chn) * 0x40)) |
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| 82 | |
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| 83 | /* DMA Byte Count Register */ |
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| 84 | #define MCF5206E_BCR(mbar,chn) MCF5206E_REG16(mbar,0x20C + ((chn) * 0x40)) |
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| 85 | |
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| 86 | /* DMA Control Register */ |
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| 87 | #define MCF5206E_DCR(mbar,chn) MCF5206E_REG16(mbar,0x208 + ((chn) * 0x40)) |
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| 88 | #define MCF5206E_DCR_INT (0x8000) /* Interrupt on completion of transfer */ |
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| 89 | #define MCF5206E_DCR_EEXT (0x4000) /* Enable External DMA Request */ |
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| 90 | #define MCF5206E_DCR_CS (0x2000) /* Cycle Steal */ |
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| 91 | #define MCF5206E_DCR_AA (0x1000) /* Auto Align */ |
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| 92 | #define MCF5206E_DCR_BWC (0x0E00) /* Bandwidth Control: */ |
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| 93 | #define MCF5206E_DCR_BWC_DISABLE (0x0000) /* Bandwidth Control Disabled */ |
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| 94 | #define MCF5206E_DCR_BWC_512 (0x0200) /* 512 bytes */ |
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| 95 | #define MCF5206E_DCR_BWC_1024 (0x0400) /* 1024 bytes */ |
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| 96 | #define MCF5206E_DCR_BWC_2048 (0x0600) /* 2048 bytes */ |
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| 97 | #define MCF5206E_DCR_BWC_4096 (0x0800) /* 4096 bytes */ |
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| 98 | #define MCF5206E_DCR_BWC_8192 (0x0A00) /* 8192 bytes */ |
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| 99 | #define MCF5206E_DCR_BWC_16384 (0x0C00) /* 16384 bytes */ |
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| 100 | #define MCF5206E_DCR_BWC_32768 (0x0E00) /* 32768 bytes */ |
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| 101 | #define MCF5206E_DCR_SAA (0x0100) /* Single Address Access */ |
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| 102 | #define MCF5206E_DCR_S_RW (0x0080) /* Single Address Access Read/Write Val */ |
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| 103 | #define MCF5206E_DCR_SINC (0x0040) /* Source Increment */ |
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| 104 | #define MCF5206E_DCR_SSIZE (0x0030) /* Source Size: */ |
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| 105 | #define MCF5206E_DCR_SSIZE_LONG (0x0000) /* Longword (4 bytes) */ |
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| 106 | #define MCF5206E_DCR_SSIZE_BYTE (0x0010) /* Byte */ |
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| 107 | #define MCF5206E_DCR_SSIZE_WORD (0x0020) /* Word (2 bytes) */ |
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| 108 | #define MCF5206E_DCR_SSIZE_LINE (0x0030) /* Line (16 bytes) */ |
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| 109 | #define MCF5206E_DCR_DINC (0x0008) /* Destination Increment */ |
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| 110 | #define MCF5206E_DCR_DSIZE (0x0006) /* Destination Size: */ |
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| 111 | #define MCF5206E_DCR_DSIZE_LONG (0x0000) /* Longword (4 bytes) */ |
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| 112 | #define MCF5206E_DCR_DSIZE_BYTE (0x0002) /* Byte */ |
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| 113 | #define MCF5206E_DCR_DSIZE_WORD (0x0004) /* Word (2 bytes) */ |
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| 114 | #define MCF5206E_DCR_DSIZE_LINE (0x0006) /* Line (16 bytes) */ |
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| 115 | #define MCF5206E_DCR_START (0x0001) /* Start Transfer */ |
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| 116 | |
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| 117 | /* DMA Status Register */ |
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| 118 | #define MCF5206E_DSR(mbar,chn) MCF5206E_REG8(mbar,0x210 + ((chn) * 0x40)) |
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| 119 | #define MCF5206E_DSR_CE (0x40) /* Configuration Error has occured */ |
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| 120 | #define MCF5206E_DSR_BES (0x20) /* Bus Error on Source */ |
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| 121 | #define MCF5206E_DSR_BED (0x10) /* Bus Error on Destination */ |
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| 122 | #define MCF5206E_DSR_REQ (0x04) /* Request */ |
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| 123 | #define MCF5206E_DSR_BSY (0x02) /* Busy */ |
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| 124 | #define MCF5206E_DSR_DONE (0x01) /* Transaction Done */ |
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| 125 | |
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| 126 | /* DMA Interrupt Vector Register */ |
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| 127 | #define MCF5206E_DIVR(mbar,chn) MCF5206E_REG8(mbar,0x214 + ((chn) * 0x40)) |
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| 128 | |
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| 129 | |
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| 130 | /*** System Integration Module -- MCF5206e User's Manual, Chapter 8 ***/ |
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| 131 | |
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| 132 | /* MBAR - Module Base Address Register */ |
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| 133 | #define MCF5206E_MBAR_BA (0xFFFFFC00) /* Base Address */ |
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| 134 | #define MCF5206E_MBAR_SC (0x00000010) /* Supervisor Code Space Mask */ |
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| 135 | #define MCF5206E_MBAR_SD (0x00000008) /* Supervisor Data Space Mask */ |
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| 136 | #define MCF5206E_MBAR_UC (0x00000004) /* User Code Space Mask */ |
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| 137 | #define MCF5206E_MBAR_UD (0x00000002) /* User Data Space Mask */ |
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| 138 | #define MCF5206E_MBAR_V (0x00000001) /* Contents of MBAR are valid */ |
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| 139 | |
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| 140 | /* SIM Configuration Register */ |
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| 141 | #define MCF5206E_SIMR(mbar) MCF5206E_REG8(mbar,0x003) |
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| 142 | #define MCF5206E_SIMR_FRZ1 (0x80) /* Disable Soft Wdog Timer when FREEZE */ |
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| 143 | #define MCF5206E_SIMR_FRZ0 (0x40) /* Disable Bus Timeout monitor when FREEZE*/ |
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| 144 | #define MCF5206E_SIMR_BL (0x01) /* Bus Lock Enable */ |
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| 145 | |
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| 146 | /* Interrupt numbers assignment */ |
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| 147 | #define MCF5206E_INTR_EXT_IRQ1 (1) /* External IRQ1 */ |
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| 148 | #define MCF5206E_INTR_EXT_IPL1 (1) /* External IPL1 */ |
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| 149 | #define MCF5206E_INTR_EXT_IPL2 (2) /* External IPL2 */ |
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| 150 | #define MCF5206E_INTR_EXT_IPL3 (3) /* External IPL3 */ |
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| 151 | #define MCF5206E_INTR_EXT_IRQ4 (4) /* External IRQ4 */ |
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| 152 | #define MCF5206E_INTR_EXT_IPL4 (4) /* External IPL4 */ |
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| 153 | #define MCF5206E_INTR_EXT_IPL5 (5) /* External IPL5 */ |
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| 154 | #define MCF5206E_INTR_EXT_IPL6 (6) /* External IPL6 */ |
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| 155 | #define MCF5206E_INTR_EXT_IRQ7 (7) /* External IRQ7 */ |
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| 156 | #define MCF5206E_INTR_EXT_IPL7 (7) /* External IPL7 */ |
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| 157 | #define MCF5206E_INTR_SWT (8) /* Software Watchdog Timer */ |
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| 158 | #define MCF5206E_INTR_TIMER_1 (9) /* Timer 1 interrupt */ |
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| 159 | #define MCF5206E_INTR_TIMER_2 (10) /* Timer 2 interrupt */ |
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| 160 | #define MCF5206E_INTR_MBUS (11) /* MBUS interrupt */ |
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| 161 | #define MCF5206E_INTR_UART_1 (12) /* UART 1 interrupt */ |
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| 162 | #define MCF5206E_INTR_UART_2 (13) /* UART 2 interrupt */ |
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| 163 | #define MCF5206E_INTR_DMA_0 (14) /* DMA channel 0 interrupt */ |
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| 164 | #define MCF5206E_INTR_DMA_1 (15) /* DMA channel 1 interrupt */ |
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| 165 | |
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| 166 | #define MCF5206E_INTR_BIT(n) (1 << (n)) |
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| 167 | |
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| 168 | /* Interrupt Control Registers (ICR1 - ICR15) */ |
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| 169 | #define MCF5206E_ICR(mbar,n) MCF5206E_REG8(mbar,0x014 + (n) - 1) |
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| 170 | |
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| 171 | #define MCF5206E_ICR_AVEC (0x80) /* Autovector Enable */ |
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| 172 | #define MCF5206E_ICR_IL (0x1c) /* Interrupt Level */ |
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| 173 | #define MCF5206E_ICR_IL_S (2) |
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| 174 | #define MCF5206E_ICR_IP (0x03) /* Interrupt Priority */ |
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| 175 | #define MCF5206E_ICR_IP_S (0) |
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| 176 | |
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| 177 | /* Interrupt Mask Register */ |
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| 178 | #define MCF5206E_IMR(mbar) MCF5206E_REG16(mbar,0x036) |
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| 179 | |
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| 180 | /* Interrupt Pending Register */ |
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| 181 | #define MCF5206E_IPR(mbar) MCF5206E_REG16(mbar,0x03a) |
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| 182 | |
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| 183 | /* Reset Status Register */ |
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| 184 | #define MCF5206E_RSR(mbar) MCF5206E_REG8(mbar,0x040) |
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| 185 | #define MCF5206E_RSR_HRST (0x80) /* Hard Reset or System Reset */ |
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| 186 | #define MCF5206E_RSR_SWTR (0x20) /* Software Watchdog Timer Reset */ |
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| 187 | |
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| 188 | /* System Protection Control Register */ |
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| 189 | #define MCF5206E_SYPCR(mbar) MCF5206E_REG8(mbar,0x041) |
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| 190 | #define MCF5206E_SYPCR_SWE (0x80) /* Software Watchdog Enable */ |
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| 191 | #define MCF5206E_SYPCR_SWRI (0x40) /* Software Watchdog Reset/Interrupt Sel.*/ |
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| 192 | #define MCF5206E_SYPCR_SWP (0x20) /* Software Watchdog Prescaler */ |
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| 193 | #define MCF5206E_SYPCR_SWT (0x18) /* Software Watchdog Timing: */ |
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| 194 | #define MCF5206E_SYPCR_SWT_S (3) |
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| 195 | #define MCF5206E_SYPCR_SWT_9 (0x00) /* timeout = (1<<9)/sysfreq */ |
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| 196 | #define MCF5206E_SYPCR_SWT_11 (0x08) /* timeout = (1<<11)/sysfreq */ |
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| 197 | #define MCF5206E_SYPCR_SWT_13 (0x10) /* timeout = (1<<13)/sysfreq */ |
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| 198 | #define MCF5206E_SYPCR_SWT_15 (0x18) /* timeout = (1<<15)/sysfreq */ |
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| 199 | #define MCF5206E_SYPCR_SWT_18 (0x20) /* timeout = (1<<18)/sysfreq */ |
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| 200 | #define MCF5206E_SYPCR_SWT_20 (0x28) /* timeout = (1<<20)/sysfreq */ |
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| 201 | #define MCF5206E_SYPCR_SWT_22 (0x30) /* timeout = (1<<22)/sysfreq */ |
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| 202 | #define MCF5206E_SYPCR_SWT_24 (0x38) /* timeout = (1<<24)/sysfreq */ |
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| 203 | #define MCF5206E_SYPCR_BME (0x04) /* Bus Timeout Monitor Enable */ |
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| 204 | #define MCF5206E_SYPCR_BMT (0x03) /* Bus Monitor Timing: */ |
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| 205 | #define MCF5206E_SYPCR_BMT_1024 (0x00) /* timeout 1024 system clocks */ |
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| 206 | #define MCF5206E_SYPCR_BMT_512 (0x01) /* timeout 512 system clocks */ |
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| 207 | #define MCF5206E_SYPCR_BMT_256 (0x02) /* timeout 256 system clocks */ |
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| 208 | #define MCF5206E_SYPCR_BMT_128 (0x03) /* timeout 128 system clocks */ |
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| 209 | |
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| 210 | /* Software Watchdog Interrupt Vector Register */ |
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| 211 | #define MCF5206E_SWIVR(mbar) MCF5206E_REG8(mbar,0x042) |
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| 212 | |
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| 213 | /* Software Watchdog Service Register */ |
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| 214 | #define MCF5206E_SWSR(mbar) MCF5206E_REG8(mbar,0x043) |
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| 215 | #define MCF5206E_SWSR_KEY1 (0x55) |
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| 216 | #define MCF5206E_SWSR_KEY2 (0xAA) |
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| 217 | |
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| 218 | /* Pin Assignment Register */ |
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| 219 | #define MCF5206E_PAR(mbar) MCF5206E_REG16(mbar,0x0CA) |
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| 220 | #define MCF5206E_PAR_PAR9 (0x200) |
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| 221 | #define MCF5206E_PAR_PAR9_TOUT (0x000) /* Timer 0 output */ |
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| 222 | #define MCF5206E_PAR_PAR9_DREQ1 (0x200) /* DMA channel 1 request */ |
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| 223 | #define MCF5206E_PAR_PAR8 (0x100) |
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| 224 | #define MCF5206E_PAR_PAR8_TIN0 (0x000) /* Timer 1 input */ |
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| 225 | #define MCF5206E_PAR_PAR8_DREQ0 (0x100) /* DMA channel 0 request */ |
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| 226 | #define MCF5206E_PAR_PAR7 (0x080) |
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| 227 | #define MCF5206E_PAR_PAR7_RSTO (0x000) /* Reset output */ |
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| 228 | #define MCF5206E_PAR_PAR7_UART2 (0x080) /* UART 2 RTS output */ |
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| 229 | #define MCF5206E_PAR_PAR6 (0x040) |
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| 230 | #define MCF5206E_PAR_PAR6_IRQ (0x000) /* IRQ7, IRQ4, IRQ1 */ |
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| 231 | #define MCF5206E_PAR_PAR6_IPL (0x040) /* IPL2, IPL1, IPL0 */ |
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| 232 | #define MCF5206E_PAR_PAR5 (0x020) |
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| 233 | #define MCF5206E_PAR_PAR5_GPIO (0x000) /* General purpose I/O PP7-PP4 */ |
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| 234 | #define MCF5206E_PAR_PAR5_PST (0x020) /* BDM signals PST3-PST0 */ |
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| 235 | #define MCF5206E_PAR_PAR4 (0x010) |
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| 236 | #define MCF5206E_PAR_PAR4_GPIO (0x000) /* General purpose I/O PP3-PP0 */ |
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| 237 | #define MCF5206E_PAR_PAR4_DDATA (0x010) /* BDM signals DDATA3-DDATA0 */ |
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| 238 | #define MCF5206E_PAR_PAR3 (0x008) |
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| 239 | #define MCF5206E_PAR_PAR2 (0x004) |
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| 240 | #define MCF5206E_PAR_PAR1 (0x002) |
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| 241 | #define MCF5206E_PAR_PAR0 (0x001) |
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| 242 | #define MCF5206E_PAR_WE0_WE1_WE2_WE3 (0x000) |
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| 243 | #define MCF5206E_PAR_WE0_WE1_CS5_CS4 (0x001) |
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| 244 | #define MCF5206E_PAR_WE0_WE1_CS5_A24 (0x002) |
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| 245 | #define MCF5206E_PAR_WE0_WE1_A25_A24 (0x003) |
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| 246 | #define MCF5206E_PAR_WE0_CS6_CS5_CS4 (0x004) |
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| 247 | #define MCF5206E_PAR_WE0_CS6_CS5_A24 (0x005) |
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| 248 | #define MCF5206E_PAR_WE0_CS6_A25_A24 (0x006) |
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| 249 | #define MCF5206E_PAR_WE0_A26_A25_A24 (0x007) |
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| 250 | #define MCF5206E_PAR_CS7_CS6_CS5_CS4 (0x008) |
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| 251 | #define MCF5206E_PAR_CS7_CS6_CS4_A24 (0x009) |
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| 252 | #define MCF5206E_PAR_CS7_CS6_A25_A24 (0x00A) |
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| 253 | #define MCF5206E_PAR_CS7_A26_A25_A24 (0x00B) |
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| 254 | #define MCF5206E_PAR_A27_A26_A25_A24 (0x00C) |
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| 255 | |
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| 256 | /* Bus Master Arbitration Control */ |
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| 257 | #define MCF5206E_MARB(mbar) MCF5206E_REG8(mbar,0x007) |
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| 258 | #define MCF5206E_MARB_NOARB (0x08) /* Arbiter operation disable */ |
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| 259 | #define MCF5206E_MARB_ARBCTRL (0x04) /* Arb. order: Internal DMA, Coldfire */ |
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| 260 | |
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| 261 | /*** Chip Select Module -- MCF5206e User's Manual, Chapter 9 ***/ |
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| 262 | |
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| 263 | /* Chip Select Address Register */ |
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| 264 | #define MCF5206E_CSAR(mbar,bank) MCF5206E_REG16(mbar,0x064 + ((bank) * 12)) |
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| 265 | |
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| 266 | /* Chip Select Mask Register */ |
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| 267 | #define MCF5206E_CSMR(mbar,bank) MCF5206E_REG32(mbar,0x068 + ((bank) * 12)) |
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| 268 | #define MCF5206E_CSMR_BAM (0xffff0000) /* Base Address Mask */ |
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| 269 | #define MCF5206E_CSMR_BAM_S (16) |
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| 270 | #define MCF5206E_CSMR_MASK_256M (0x0FFF0000) |
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| 271 | #define MCF5206E_CSMR_MASK_128M (0x07FF0000) |
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| 272 | #define MCF5206E_CSMR_MASK_64M (0x03FF0000) |
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| 273 | #define MCF5206E_CSMR_MASK_32M (0x01FF0000) |
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| 274 | #define MCF5206E_CSMR_MASK_16M (0x00FF0000) |
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| 275 | #define MCF5206E_CSMR_MASK_8M (0x007F0000) |
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| 276 | #define MCF5206E_CSMR_MASK_4M (0x003F0000) |
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| 277 | #define MCF5206E_CSMR_MASK_2M (0x001F0000) |
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| 278 | #define MCF5206E_CSMR_MASK_1M (0x000F0000) |
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| 279 | #define MCF5206E_CSMR_MASK_1024K (0x000F0000) |
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| 280 | #define MCF5206E_CSMR_MASK_512K (0x00070000) |
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| 281 | #define MCF5206E_CSMR_MASK_256K (0x00030000) |
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| 282 | #define MCF5206E_CSMR_MASK_128K (0x00010000) |
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| 283 | #define MCF5206E_CSMR_MASK_64K (0x00000000) |
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| 284 | #define MCF5206E_CSMR_CI (0x00000020) /* CPU Space Mask (CSMR1 only) */ |
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| 285 | #define MCF5206E_CSMR_SC (0x00000010) /* Supervisor Code Space Mask */ |
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| 286 | #define MCF5206E_CSMR_SD (0x00000008) /* Supervisor Data Space Mask */ |
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| 287 | #define MCF5206E_CSMR_UC (0x00000004) /* User Code Space Mask */ |
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| 288 | #define MCF5206E_CSMR_UD (0x00000002) /* User Data Space Mask */ |
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| 289 | |
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| 290 | /* Chip Select Control Register */ |
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| 291 | #define MCF5206E_CSCR(mbar,bank) MCF5206E_REG16(mbar,0x6E + ((bank) * 12)) |
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| 292 | #define MCF5206E_CSCR_WS (0x3c00) /* Wait States */ |
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| 293 | #define MCF5206E_CSCR_WS_S (10) |
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| 294 | #define MCF5206E_CSCR_WS0 (0x0000) /* 0 Wait States */ |
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| 295 | #define MCF5206E_CSCR_WS1 (0x0400) /* 1 Wait States */ |
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| 296 | #define MCF5206E_CSCR_WS2 (0x0800) /* 2 Wait States */ |
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| 297 | #define MCF5206E_CSCR_WS3 (0x0C00) /* 3 Wait States */ |
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| 298 | #define MCF5206E_CSCR_WS4 (0x1000) /* 4 Wait States */ |
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| 299 | #define MCF5206E_CSCR_WS5 (0x1400) /* 5 Wait States */ |
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| 300 | #define MCF5206E_CSCR_WS6 (0x1800) /* 6 Wait States */ |
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| 301 | #define MCF5206E_CSCR_WS7 (0x1C00) /* 7 Wait States */ |
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| 302 | #define MCF5206E_CSCR_WS8 (0x2000) /* 8 Wait States */ |
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| 303 | #define MCF5206E_CSCR_WS9 (0x2400) /* 9 Wait States */ |
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| 304 | #define MCF5206E_CSCR_WS10 (0x2800) /* 10 Wait States */ |
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| 305 | #define MCF5206E_CSCR_WS11 (0x2C00) /* 11 Wait States */ |
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| 306 | #define MCF5206E_CSCR_WS12 (0x3000) /* 12 Wait States */ |
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| 307 | #define MCF5206E_CSCR_WS13 (0x3400) /* 13 Wait States */ |
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| 308 | #define MCF5206E_CSCR_WS14 (0x3800) /* 14 Wait States */ |
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| 309 | #define MCF5206E_CSCR_WS15 (0x3C00) /* 15 Wait States */ |
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| 310 | #define MCF5206E_CSCR_BRST (0x0200) /* Burst Enable */ |
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| 311 | #define MCF5206E_CSCR_AA (0x0100) /* Coldfire Core Auto Acknowledge |
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| 312 | Enable */ |
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| 313 | #define MCF5206E_CSCR_PS (0x00C0) /* Port Size */ |
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| 314 | #define MCF5206E_CSCR_PS_S (6) |
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| 315 | #define MCF5206E_CSCR_PS_32 (0x0000) /* Port Size = 32 bits */ |
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| 316 | #define MCF5206E_CSCR_PS_8 (0x0040) /* Port Size = 8 bits */ |
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| 317 | #define MCF5206E_CSCR_PS_16 (0x0080) /* Port Size = 16 bits */ |
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| 318 | #define MCF5206E_CSCR_EMAA (0x0020) /* External Master Automatic Acknowledge |
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| 319 | Enable */ |
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| 320 | #define MCF5206E_CSCR_ASET (0x0010) /* Address Setup Enable */ |
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| 321 | #define MCF5206E_CSCR_WRAH (0x0008) /* Write Address Hold Enable */ |
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| 322 | #define MCF5206E_CSCR_RDAH (0x0004) /* Read Address Hold Enable */ |
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| 323 | #define MCF5206E_CSCR_WR (0x0002) /* Write Enable */ |
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| 324 | #define MCF5206E_CSCR_RD (0x0001) /* Read Enable */ |
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| 325 | |
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| 326 | /* Default Memory Control Register */ |
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| 327 | #define MCF5206E_DMCR(mbar) MCF5206E_REG16(mbar, 0x0C6) |
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| 328 | |
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| 329 | /*** Parallel Port (GPIO) Module -- MCF5206e User's Manual, Chapter 10 ***/ |
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| 330 | |
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| 331 | /* Port A Data Direction Register */ |
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| 332 | #define MCF5206E_PPDDR(mbar) MCF5206E_REG8(mbar,0x1C5) |
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| 333 | |
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| 334 | /* Port A Data Register */ |
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| 335 | #define MCF5206E_PPDAT(mbar) MCF5206E_REG8(mbar,0x1C9) |
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| 336 | |
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| 337 | #define MCF5206E_PP_DAT0 (0x01) |
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| 338 | #define MCF5206E_PP_DAT1 (0x02) |
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| 339 | #define MCF5206E_PP_DAT2 (0x04) |
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| 340 | #define MCF5206E_PP_DAT3 (0x08) |
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| 341 | #define MCF5206E_PP_DAT4 (0x10) |
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| 342 | #define MCF5206E_PP_DAT5 (0x20) |
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| 343 | #define MCF5206E_PP_DAT6 (0x40) |
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| 344 | #define MCF5206E_PP_DAT7 (0x80) |
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| 345 | |
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| 346 | /*** DRAM Controller -- MCF5206e User's Manual, Chapter 11 ***/ |
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| 347 | |
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| 348 | /* DRAM Controller Refresh Register */ |
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| 349 | #define MCF5206E_DCRR(mbar) MCF5206E_REG16(mbar,0x046) |
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| 350 | |
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| 351 | /* DRAM Controller Timing Register */ |
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| 352 | #define MCF5206E_DCTR(mbar) MCF5206E_REG16(mbar,0x04A) |
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| 353 | #define MCF5206E_DCTR_DAEM (0x8000) /* Drive Multiplexed Address During |
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| 354 | External Master DRAM Transfers */ |
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| 355 | #define MCF5206E_DCTR_EDO (0x4000) /* Extended Data-Out Enable */ |
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| 356 | #define MCF5206E_DCTR_RCD (0x1000) /* RAS-to-CAS Delay Time */ |
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| 357 | #define MCF5206E_DCTR_RSH (0x0600) /* RAS Hold Time */ |
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| 358 | #define MCF5206E_DCTR_RSH_0 (0x0000) /* See User's Manual for details */ |
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| 359 | #define MCF5206E_DCTR_RSH_1 (0x0200) |
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| 360 | #define MCF5206E_DCTR_RSH_2 (0x0400) |
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| 361 | #define MCF5206E_DCTR_RP (0x0060) /* RAS Precharge Time */ |
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| 362 | #define MCF5206E_DCTR_RP_15 (0x0000) /* RAS Precharges for 1.5 system clks */ |
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| 363 | #define MCF5206E_DCTR_RP_25 (0x0020) /* RAS Precharges for 2.5 system clks */ |
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| 364 | #define MCF5206E_DCTR_RP_35 (0x0040) /* RAS Precharges for 3.5 system clks */ |
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| 365 | #define MCF5206E_DCTR_CAS (0x0008) /* Column Address Strobe Time */ |
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| 366 | #define MCF5206E_DCTR_CP (0x0002) /* CAS Precharge Time */ |
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| 367 | #define MCF5206E_DCTR_CSR (0x0001) /* CAS Setup Time for CAS before RAS |
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| 368 | refresh */ |
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| 369 | |
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| 370 | /* DRAM Controller Address Registers */ |
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| 371 | #define MCF5206E_DCAR(mbar,bank) MCF5206E_REG16(mbar,0x4C + ((bank) * 12)) |
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| 372 | |
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| 373 | /* DRAM Controller Mask Registers */ |
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| 374 | #define MCF5206E_DCMR(mbar,bank) MCF5206E_REG32(mbar,0x50 + ((bank) * 12)) |
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| 375 | #define MCF5206E_DCMR_BAM (0xffff0000) /* Base Address Mask */ |
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| 376 | #define MCF5206E_DCMR_BAM_S (16) |
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| 377 | #define MCF5206E_DCMR_MASK_256M (0x0FFE0000) |
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| 378 | #define MCF5206E_DCMR_MASK_128M (0x07FE0000) |
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| 379 | #define MCF5206E_DCMR_MASK_64M (0x03FE0000) |
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| 380 | #define MCF5206E_DCMR_MASK_32M (0x01FE0000) |
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| 381 | #define MCF5206E_DCMR_MASK_16M (0x00FE0000) |
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| 382 | #define MCF5206E_DCMR_MASK_8M (0x007E0000) |
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| 383 | #define MCF5206E_DCMR_MASK_4M (0x003E0000) |
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| 384 | #define MCF5206E_DCMR_MASK_2M (0x001E0000) |
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| 385 | #define MCF5206E_DCMR_MASK_1M (0x000E0000) |
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| 386 | #define MCF5206E_DCMR_MASK_1024K (0x000E0000) |
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| 387 | #define MCF5206E_DCMR_MASK_512K (0x00060000) |
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| 388 | #define MCF5206E_DCMR_MASK_256K (0x00020000) |
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| 389 | #define MCF5206E_DCMR_MASK_128K (0x00000000) |
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| 390 | #define MCF5206E_DCMR_SC (0x00000010) /* Supervisor Code Space Mask */ |
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| 391 | #define MCF5206E_DCMR_SD (0x00000008) /* Supervisor Data Space Mask */ |
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| 392 | #define MCF5206E_DCMR_UC (0x00000004) /* User Code Space Mask */ |
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| 393 | #define MCF5206E_DCMR_UD (0x00000002) /* User Data Space Mask */ |
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| 394 | |
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| 395 | /* DRAM Controller Control Register */ |
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| 396 | #define MCF5206E_DCCR(mbar,bank) MCF5206E_REG8(mbar, 0x57 + ((bank) * 12)) |
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| 397 | #define MCF5206E_DCCR_PS (0xC0) /* Port Size */ |
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| 398 | #define MCF5206E_DCCR_PS_32 (0x00) /* 32 bit Port Size */ |
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| 399 | #define MCF5206E_DCCR_PS_8 (0x40) /* 8 bit Port Size */ |
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| 400 | #define MCF5206E_DCCR_PS_16 (0x80) /* 16 bit Port Size */ |
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| 401 | #define MCF5206E_DCCR_BPS (0x30) /* Bank Page Size */ |
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| 402 | #define MCF5206E_DCCR_BPS_512 (0x00) /* 512 Byte Page Size */ |
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| 403 | #define MCF5206E_DCCR_BPS_1K (0x10) /* 1 KByte Page Size */ |
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| 404 | #define MCF5206E_DCCR_BPS_2K (0x20) /* 2 KByte Page Size */ |
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| 405 | #define MCF5206E_DCCR_PM (0x0C) /* Page Mode Select */ |
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| 406 | #define MCF5206E_DCCR_PM_NORMAL (0x00) /* Normal Mode */ |
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| 407 | #define MCF5206E_DCCR_PM_BURSTP (0x04) /* Burst Page Mode */ |
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| 408 | #define MCF5206E_DCCR_PM_FASTP (0x0C) /* Fast Page Mode */ |
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| 409 | #define MCF5206E_DCCR_WR (0x02) /* Write Enable */ |
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| 410 | #define MCF5206E_DCCR_RD (0x01) /* Read Enable */ |
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| 411 | |
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| 412 | /*** UART Module -- MCF5206e User's Manual, Chapter 12 ***/ |
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| 413 | |
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| 414 | #define MCF5206E_UART_CHANNELS (2) |
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| 415 | /* UART Mode Register */ |
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| 416 | #define MCF5206E_UMR(mbar,n) MCF5206E_REG8(mbar,0x140 + (((n)-1) * 0x40)) |
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| 417 | #define MCF5206E_UMR1_RXRTS (0x80) /* Receiver Request-to-Send |
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| 418 | Control */ |
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| 419 | #define MCF5206E_UMR1_RXIRQ (0x40) /* Receiver Interrupt Select */ |
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| 420 | #define MCF5206E_UMR1_ERR (0x20) /* Error Mode */ |
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| 421 | #define MCF5206E_UMR1_PM (0x1C) /* Parity Mode, Parity Type */ |
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| 422 | #define MCF5206E_UMR1_PM_EVEN (0x00) /* Even Parity */ |
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| 423 | #define MCF5206E_UMR1_PM_ODD (0x04) /* Odd Parity */ |
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| 424 | #define MCF5206E_UMR1_PM_FORCE_LOW (0x08) /* Force parity low */ |
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| 425 | #define MCF5206E_UMR1_PM_FORCE_HIGH (0x0C) /* Force parity high */ |
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| 426 | #define MCF5206E_UMR1_PM_NO_PARITY (0x10) /* No Parity */ |
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| 427 | #define MCF5206E_UMR1_PM_MULTI_DATA (0x18) /* Multidrop mode - data char */ |
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| 428 | #define MCF5206E_UMR1_PM_MULTI_ADDR (0x1C) /* Multidrop mode - addr char */ |
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| 429 | #define MCF5206E_UMR1_BC (0x03) /* Bits per Character */ |
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| 430 | #define MCF5206E_UMR1_BC_5 (0x00) /* 5 bits per character */ |
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| 431 | #define MCF5206E_UMR1_BC_6 (0x01) /* 6 bits per character */ |
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| 432 | #define MCF5206E_UMR1_BC_7 (0x02) /* 7 bits per character */ |
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| 433 | #define MCF5206E_UMR1_BC_8 (0x03) /* 8 bits per character */ |
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| 434 | |
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| 435 | #define MCF5206E_UMR2_CM (0xC0) /* Channel Mode */ |
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| 436 | #define MCF5206E_UMR2_CM_NORMAL (0x00) /* Normal Mode */ |
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| 437 | #define MCF5206E_UMR2_CM_AUTO_ECHO (0x40) /* Automatic Echo Mode */ |
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| 438 | #define MCF5206E_UMR2_CM_LOCAL_LOOP (0x80) /* Local Loopback Mode */ |
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| 439 | #define MCF5206E_UMR2_CM_REMOTE_LOOP (0xC0) /* Remote Loopback Modde */ |
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| 440 | #define MCF5206E_UMR2_TXRTS (0x20) /* Transmitter Ready-to-Send op */ |
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| 441 | #define MCF5206E_UMR2_TXCTS (0x10) /* Transmitter Clear-to-Send op */ |
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| 442 | #define MCF5206E_UMR2_SB (0x0F) /* Stop Bit Length */ |
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| 443 | #define MCF5206E_UMR2_SB_1 (0x07) /* 1 Stop Bit for 6-8 bits char */ |
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| 444 | #define MCF5206E_UMR2_SB_15 (0x08) /* 1.5 Stop Bits for 6-8 bits chr*/ |
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| 445 | #define MCF5206E_UMR2_SB_2 (0x0F) /* 2 Stop Bits for 6-8 bits char */ |
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| 446 | #define MCF5206E_UMR2_SB5_1 (0x00) /* 1 Stop Bits for 5 bit char */ |
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| 447 | #define MCF5206E_UMR2_SB5_15 (0x07) /* 1.5 Stop Bits for 5 bit char */ |
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| 448 | #define MCF5206E_UMR2_SB5_2 (0x0F) /* 2 Stop Bits for 5 bit char */ |
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| 449 | |
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| 450 | /* UART Status Register (read only) */ |
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| 451 | #define MCF5206E_USR(mbar,n) MCF5206E_REG8(mbar,0x144 + (((n)-1) * 0x40)) |
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| 452 | #define MCF5206E_USR_RB (0x80) /* Received Break */ |
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| 453 | #define MCF5206E_USR_FE (0x40) /* Framing Error */ |
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| 454 | #define MCF5206E_USR_PE (0x20) /* Parity Error */ |
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| 455 | #define MCF5206E_USR_OE (0x10) /* Overrun Error */ |
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| 456 | #define MCF5206E_USR_TXEMP (0x08) /* Transmitter Empty */ |
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| 457 | #define MCF5206E_USR_TXRDY (0x04) /* Transmitter Ready */ |
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| 458 | #define MCF5206E_USR_FFULL (0x02) /* FIFO Full */ |
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| 459 | #define MCF5206E_USR_RXRDY (0x01) /* Receiver Ready */ |
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| 460 | |
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| 461 | /* UART Clock Select Register (write only) */ |
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| 462 | #define MCF5206E_UCSR(mbar,n) MCF5206E_REG8(mbar,0x144 + (((n)-1) * 0x40)) |
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| 463 | #define MCF5206E_UCSR_RCS (0xF0) /* Receiver Clock Select */ |
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| 464 | #define MCF5206E_UCSR_RCS_TIMER (0xD0) /* Timer */ |
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| 465 | #define MCF5206E_UCSR_RCS_EXT16 (0xE0) /* External clk x16 */ |
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| 466 | #define MCF5206E_UCSR_RCS_EXT (0xF0) /* External clk x1 */ |
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| 467 | #define MCF5206E_UCSR_TCS (0x0F) /* Transmitter Clock Select */ |
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| 468 | #define MCF5206E_UCSR_TCS_TIMER (0x0D) /* Timer */ |
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| 469 | #define MCF5206E_UCSR_TCS_EXT16 (0x0E) /* External clk x16 */ |
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| 470 | #define MCF5206E_UCSR_TCS_EXT (0x0F) /* External clk x1 */ |
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| 471 | |
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| 472 | /* UART Command Register (write only) */ |
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| 473 | #define MCF5206E_UCR(mbar,n) MCF5206E_REG8(mbar,0x148 + (((n)-1) * 0x40)) |
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| 474 | #define MCF5206E_UCR_MISC (0x70) /* Miscellaneous Commands: */ |
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| 475 | #define MCF5206E_UCR_MISC_NOP (0x00) /* No Command */ |
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| 476 | #define MCF5206E_UCR_MISC_RESET_MR (0x10) /* Reset Mode Register Ptr */ |
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| 477 | #define MCF5206E_UCR_MISC_RESET_RX (0x20) /* Reset Receiver */ |
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| 478 | #define MCF5206E_UCR_MISC_RESET_TX (0x30) /* Reset Transmitter */ |
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| 479 | #define MCF5206E_UCR_MISC_RESET_ERR (0x40) /* Reset Error Status */ |
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| 480 | #define MCF5206E_UCR_MISC_RESET_BRK (0x50) /* Reset Break-Change Interrupt */ |
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| 481 | #define MCF5206E_UCR_MISC_START_BRK (0x60) /* Start Break */ |
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| 482 | #define MCF5206E_UCR_MISC_STOP_BRK (0x70) /* Stop Break */ |
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| 483 | #define MCF5206E_UCR_TC (0x0C) /* Transmitter Commands: */ |
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| 484 | #define MCF5206E_UCR_TC_NOP (0x00) /* No Action Taken */ |
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| 485 | #define MCF5206E_UCR_TC_ENABLE (0x04) /* Transmitter Enable */ |
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| 486 | #define MCF5206E_UCR_TC_DISABLE (0x08) /* Transmitter Disable */ |
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| 487 | #define MCF5206E_UCR_RC (0x03) /* Receiver Commands: */ |
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| 488 | #define MCF5206E_UCR_RC_NOP (0x00) /* No Action Taken */ |
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| 489 | #define MCF5206E_UCR_RC_ENABLE (0x01) /* Receiver Enable */ |
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| 490 | #define MCF5206E_UCR_RC_DISABLE (0x02) /* Receiver Disable */ |
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| 491 | |
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| 492 | /* UART Receive Buffer (read only) */ |
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| 493 | #define MCF5206E_URB(mbar,n) MCF5206E_REG8(mbar,0x14C + (((n)-1) * 0x40)) |
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| 494 | |
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| 495 | /* UART Transmit Buffer (write only) */ |
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| 496 | #define MCF5206E_UTB(mbar,n) MCF5206E_REG8(mbar,0x14C + (((n)-1) * 0x40)) |
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| 497 | |
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| 498 | /* UART Input Port Change Register (read only) */ |
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| 499 | #define MCF5206E_UIPCR(mbar,n) MCF5206E_REG8(mbar,0x150 + (((n)-1) * 0x40)) |
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| 500 | #define MCF5206E_UIPCR_COS (0x10) /* Change of State at CTS input */ |
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| 501 | #define MCF5206E_UIPCR_CTS (0x01) /* Current State of CTS */ |
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| 502 | |
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| 503 | /* UART Auxiliary Control Register (write only) */ |
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| 504 | #define MCF5206E_UACR(mbar,n) MCF5206E_REG8(mbar,0x150 + (((n)-1) * 0x40)) |
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| 505 | #define MCF5206E_UACR_IEC (0x01) /* Input Enable Control - generate interrupt |
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| 506 | on CTS change */ |
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| 507 | |
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| 508 | /* UART Interrupt Status Register (read only) */ |
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| 509 | #define MCF5206E_UISR(mbar,n) MCF5206E_REG8(mbar,0x154 + (((n)-1) * 0x40)) |
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| 510 | #define MCF5206E_UISR_COS (0x80) /* Change of State has occured at CTS */ |
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| 511 | #define MCF5206E_UISR_DB (0x04) /* Delta Break */ |
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| 512 | #define MCF5206E_UISR_RXRDY (0x02) /* Receiver Ready or FIFO Full */ |
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| 513 | #define MCF5206E_UISR_TXRDY (0x01) /* Transmitter Ready */ |
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| 514 | |
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| 515 | /* UART Interrupt Mask Register (write only) */ |
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| 516 | #define MCF5206E_UIMR(mbar,n) MCF5206E_REG8(mbar,0x154 + (((n)-1) * 0x40)) |
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| 517 | #define MCF5206E_UIMR_COS (0x80) /* Change of State interrupt enable */ |
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| 518 | #define MCF5206E_UIMR_DB (0x04) /* Delta Break interrupt enable */ |
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| 519 | #define MCF5206E_UIMR_FFULL (0x02) /* FIFO Full interrupt enable */ |
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| 520 | #define MCF5206E_UIMR_TXRDY (0x01) /* Transmitter Ready Interrupt enable */ |
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| 521 | |
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| 522 | /* UART Baud Rate Generator Prescale MSB Register */ |
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| 523 | #define MCF5206E_UBG1(mbar,n) MCF5206E_REG8(mbar,0x158 + (((n)-1) * 0x40)) |
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| 524 | |
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| 525 | /* UART Baud Rate Generator Prescale LSB Register */ |
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| 526 | #define MCF5206E_UBG2(mbar,n) MCF5206E_REG8(mbar,0x15C + (((n)-1) * 0x40)) |
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| 527 | |
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| 528 | /* UART Interrupt Vector Register */ |
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| 529 | #define MCF5206E_UIVR(mbar,n) MCF5206E_REG8(mbar,0x170 + (((n)-1) * 0x40)) |
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| 530 | |
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| 531 | /* UART Input Port Register (read only) */ |
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| 532 | #define MCF5206E_UIP(mbar,n) MCF5206E_REG8(mbar,0x174 + (((n)-1) * 0x40)) |
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| 533 | #define MCF5206E_UIP_CTS (0x01) /* Current state of CTS input */ |
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| 534 | |
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| 535 | /* UART Output Port Bit Set Command (address-triggered command, write) */ |
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| 536 | #define MCF5206E_UOP1(mbar,n) MCF5206E_REG8(mbar,0x178 + (((n)-1) * 0x40)) |
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| 537 | |
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| 538 | /* UART Output Port Bit Reset Command (address-triggered command, write */ |
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| 539 | #define MCF5206E_UOP0(mbar,n) MCF5206E_REG8(mbar,0x17C + (((n)-1) * 0x40)) |
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| 540 | |
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| 541 | /*** M-BUS (I2C) Module -- MCF5206e User's Manual, Chapter 13 ***/ |
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| 542 | |
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| 543 | /* M-Bus Address Register */ |
---|
| 544 | #define MCF5206E_MADR(mbar) MCF5206E_REG8(mbar, 0x1E0) |
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| 545 | |
---|
| 546 | /* M-Bus Frequency Divider Register */ |
---|
| 547 | #define MCF5206E_MFDR(mbar) MCF5206E_REG8(mbar, 0x1E4) |
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| 548 | |
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| 549 | /* M-Bus Control Register */ |
---|
| 550 | #define MCF5206E_MBCR(mbar) MCF5206E_REG8(mbar, 0x1E8) |
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| 551 | #define MCF5206E_MBCR_MEN (0x80) /* M-Bus Enable */ |
---|
| 552 | #define MCF5206E_MBCR_MIEN (0x40) /* M-Bus Interrupt Enable */ |
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| 553 | #define MCF5206E_MBCR_MSTA (0x20) /* Master Mode Selection */ |
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| 554 | #define MCF5206E_MBCR_MTX (0x10) /* Transmit Mode Selection */ |
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| 555 | #define MCF5206E_MBCR_TXAK (0x08) /* Transmit Acknowledge Enable */ |
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| 556 | #define MCF5206E_MBCR_RSTA (0x04) /* Repeat Start */ |
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| 557 | |
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| 558 | /* M-Bus Status Register */ |
---|
| 559 | #define MCF5206E_MBSR(mbar) MCF5206E_REG8(mbar, 0x1EC) |
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| 560 | #define MCF5206E_MBSR_MCF (0x80) /* Data Transferring Bit */ |
---|
| 561 | #define MCF5206E_MBSR_MAAS (0x40) /* Addressed as a Slave Bit */ |
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| 562 | #define MCF5206E_MBSR_MBB (0x20) /* Bus Busy Bit */ |
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| 563 | #define MCF5206E_MBSR_MAL (0x10) /* Arbitration Lost */ |
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| 564 | #define MCF5206E_MBSR_SRW (0x04) /* Slave Read/Write */ |
---|
| 565 | #define MCF5206E_MBSR_MIF (0x02) /* MBus Interrupt pending */ |
---|
| 566 | #define MCF5206E_MBSR_RXAK (0x01) /* Received Acknowledge */ |
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| 567 | |
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| 568 | /* M-Bus Data I/O Register */ |
---|
| 569 | #define MCF5206E_MBDR(mbar) MCF5206E_REG8(mbar, 0x1F0) |
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| 570 | |
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| 571 | /*** Timer Module -- MCF5206e User's Manual, Chapter 14 ***/ |
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| 572 | |
---|
| 573 | /* Timer Mode Register */ |
---|
| 574 | #define MCF5206E_TMR(mbar,n) MCF5206E_REG16(mbar, 0x100 + (((n)-1)*0x20)) |
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| 575 | #define MCF5206E_TMR_PS (0xFF00) /* Prescaler Value */ |
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| 576 | #define MCF5206E_TMR_PS_S (8) |
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| 577 | #define MCF5206E_TMR_CE (0x00C0) /* Capture Edge and Enable |
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| 578 | Interrupt */ |
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| 579 | #define MCF5206E_TMR_CE_ANY (0x00C0) /* Capture on any edge */ |
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| 580 | #define MCF5206E_TMR_CE_FALL (0x0080) /* Capture on falling edge only */ |
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| 581 | #define MCF5206E_TMR_CE_RISE (0x0040) /* Capture on rising edge only */ |
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| 582 | #define MCF5206E_TMR_CE_NONE (0x0000) /* Disable Interrupt on capture |
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| 583 | event */ |
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| 584 | #define MCF5206E_TMR_OM (0x0020) /* Output Mode - Toggle output */ |
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| 585 | #define MCF5206E_TMR_ORI (0x0010) /* Output Reference Interrupt |
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| 586 | Enable */ |
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| 587 | #define MCF5206E_TMR_FRR (0x0008) /* Free Run/Restart */ |
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| 588 | #define MCF5206E_TMR_ICLK (0x0006) /* Input Clock Source */ |
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| 589 | #define MCF5206E_TMR_ICLK_TIN (0x0006) /* TIN pin (falling edge) */ |
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| 590 | #define MCF5206E_TMR_ICLK_DIV16 (0x0004) /* Master system clock divided |
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| 591 | by 16 */ |
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| 592 | #define MCF5206E_TMR_ICLK_MSCLK (0x0002) /* Master System Clock */ |
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| 593 | #define MCF5206E_TMR_ICLK_STOP (0x0000) /* Stops counter */ |
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| 594 | #define MCF5206E_TMR_RST (0x0001) /* Reset/Enable Timer */ |
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| 595 | |
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| 596 | /* Timer Reference Register */ |
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| 597 | #define MCF5206E_TRR(mbar,n) MCF5206E_REG16(mbar, 0x104 + (((n)-1)*0x20)) |
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| 598 | |
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| 599 | /* Timer Capture Register */ |
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| 600 | #define MCF5206E_TCR(mbar,n) MCF5206E_REG16(mbar, 0x108 + (((n)-1)*0x20)) |
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| 601 | |
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| 602 | /* Timer Counter Register */ |
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| 603 | #define MCF5206E_TCN(mbar,n) MCF5206E_REG16(mbar, 0x10C + (((n)-1)*0x20)) |
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| 604 | |
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| 605 | /* Timer Event Register */ |
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| 606 | #define MCF5206E_TER(mbar,n) MCF5206E_REG8(mbar, 0x111 + (((n)-1)*0x20)) |
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| 607 | #define MCF5206E_TER_REF (0x02) /* Output Reference Event */ |
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| 608 | #define MCF5206E_TER_CAP (0x01) /* Capture Event */ |
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| 609 | |
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| 610 | |
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| 611 | |
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| 612 | #endif |
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| 613 | |
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