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fpsp.defs @ 6f9c75c3

4.104.114.84.95

Last change on this file since 6f9c75c3 was 6f9c75c3, checked in by Joel Sherrill <joel.sherrill@…>, on 01/16/98 at 16:56:48

Ralf Corsepius reported a number of missing CVS Id's:

RTEMS is under CVS control and has been since rtems 3.1.16 which was
around May 1995. So I just to add the $Id$. If you notice other files
with missing $Id$'s let me know. I try to keep w\up with it.

Now that you have asked -- I'll attach a list of files lacking an RCS-Id to
this mail. This list has been generated by a little sh-script I'll also
enclose.

Property mode set to 100644

File size: 11.3 KB

Line
1	\|
2	\| $Id$
3	\|
4	\| fpsp.h 3.3 3.3
5	\|
6	\| Copyright (C) Motorola, Inc. 1990
7	\| All Rights Reserved
8	\|
9	\| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
10	\| The copyright notice above does not evidence any
11	\| actual or intended publication of such source code.
12
13	\| fpsp.h --- stack frame offsets during FPSP exception handling
14	\|
15	\| These equates are used to access the exception frame, the fsave
16	\| frame and any local variables needed by the FPSP package.
17	\|
18	\| All FPSP handlers begin by executing:
19	\|
20	\| link a6,#-LOCAL_SIZE
21	\| fsave -(a7)
22	\| movem.l d0-d1/a0-a1,USER_DA(a6)
23	\| fmovem.x fp0-fp3,USER_FP0(a6)
24	\| fmove.l fpsr/fpcr/fpiar,USER_FPSR(a6)
25	\|
26	\| After initialization, the stack looks like this:
27	\|
28	\| A7 ---> +-------------------------------+
29	\| \| \|
30	\| \| FPU fsave area \|
31	\| \| \|
32	\| +-------------------------------+
33	\| \| \|
34	\| \| FPSP Local Variables \|
35	\| \| including \|
36	\| \| saved registers \|
37	\| \| \|
38	\| +-------------------------------+
39	\| A6 ---> \| Saved A6 \|
40	\| +-------------------------------+
41	\| \| \|
42	\| \| Exception Frame \|
43	\| \| \|
44	\| \| \|
45	\|
46	\| Positive offsets from A6 refer to the exception frame. Negative
47	\| offsets refer to the Local Variable area and the fsave area.
48	\| The fsave frame is also accessible 'from the top' via A7.
49	\|
50	\| On exit, the handlers execute:
51	\|
52	\| movem.l USER_DA(a6),d0-d1/a0-a1
53	\| fmovem.x USER_FP0(a6),fp0-fp3
54	\| fmove.l USER_FPSR(a6),fpsr/fpcr/fpiar
55	\| frestore (a7)+
56	\| unlk a6
57	\|
58	\| and then either 'bra fpsp_done' if the exception was completely
59	\| handled by the package, or 'bra real_xxxx' which is an external
60	\| label to a routine that will process a real exception of the
61	\| type that was generated. Some handlers may omit the 'frestore'
62	\| if the FPU state after the exception is idle.
63	\|
64	\| Sometimes the exception handler will transform the fsave area
65	\| because it needs to report an exception back to the user. This
66	\| can happen if the package is entered for an unimplemented float
67	\| instruction that generates (say) an underflow. Alternatively,
68	\| a second fsave frame can be pushed onto the stack and the
69	\| handler exit code will reload the new frame and discard the old.
70	\|
71	\| The registers d0, d1, a0, a1 and fp0-fp3 are always saved and
72	\| restored from the 'local variable' area and can be used as
73	\| temporaries. If a routine needs to change any
74	\| of these registers, it should modify the saved copy and let
75	\| the handler exit code restore the value.
76	\|
77	\|----------------------------------------------------------------------
78	\|
79	\| Local Variables on the stack
80	\|
81	.set LOCAL_SIZE,192 \| bytes needed for local variables
82	.set LV,-LOCAL_SIZE \| convenient base value
83	\|
84	.set USER_DA,LV+0 \| save space for D0-D1,A0-A1
85	.set USER_D0,LV+0 \| saved user D0
86	.set USER_D1,LV+4 \| saved user D1
87	.set USER_A0,LV+8 \| saved user A0
88	.set USER_A1,LV+12 \| saved user A1
89	.set USER_FP0,LV+16 \| saved user FP0
90	.set USER_FP1,LV+28 \| saved user FP1
91	.set USER_FP2,LV+40 \| saved user FP2
92	.set USER_FP3,LV+52 \| saved user FP3
93	.set USER_FPCR,LV+64 \| saved user FPCR
94	.set FPCR_ENABLE,USER_FPCR+2 \| FPCR exception enable
95	.set FPCR_MODE,USER_FPCR+3 \| FPCR rounding mode control
96	.set USER_FPSR,LV+68 \| saved user FPSR
97	.set FPSR_CC,USER_FPSR+0 \| FPSR condition code
98	.set FPSR_QBYTE,USER_FPSR+1 \| FPSR quotient
99	.set FPSR_EXCEPT,USER_FPSR+2 \| FPSR exception
100	.set FPSR_AEXCEPT,USER_FPSR+3 \| FPSR accrued exception
101	.set USER_FPIAR,LV+72 \| saved user FPIAR
102	.set FP_SCR1,LV+76 \| room for a temporary float value
103	.set FP_SCR2,LV+92 \| room for a temporary float value
104	.set L_SCR1,LV+108 \| room for a temporary long value
105	.set L_SCR2,LV+112 \| room for a temporary long value
106	.set STORE_FLG,LV+116
107	.set BINDEC_FLG,LV+117 \| used in bindec
108	.set DNRM_FLG,LV+118 \| used in res_func
109	.set RES_FLG,LV+119 \| used in res_func
110	.set DY_MO_FLG,LV+120 \| dyadic/monadic flag
111	.set UFLG_TMP,LV+121 \| temporary for uflag errata
112	.set CU_ONLY,LV+122 \| cu-only flag
113	.set VER_TMP,LV+123 \| temp holding for version number
114	.set L_SCR3,LV+124 \| room for a temporary long value
115	.set FP_SCR3,LV+128 \| room for a temporary float value
116	.set FP_SCR4,LV+144 \| room for a temporary float value
117	.set FP_SCR5,LV+160 \| room for a temporary float value
118	.set FP_SCR6,LV+176
119	\|
120	\|NEXT equ LV+192 ;need to increase LOCAL_SIZE
121	\|
122	\|--------------------------------------------------------------------------
123	\|
124	\| fsave offsets and bit definitions
125	\|
126	\| Offsets are defined from the end of an fsave because the last 10
127	\| words of a busy frame are the same as the unimplemented frame.
128	\|
129	.set CU_SAVEPC,LV-92 \| micro-pc for CU (1 byte)
130	.set FPR_DIRTY_BITS,LV-91 \| fpr dirty bits
131	\|
132	.set WBTEMP,LV-76 \| write back temp (12 bytes)
133	.set WBTEMP_EX,WBTEMP \| wbtemp sign and exponent (2 bytes)
134	.set WBTEMP_HI,WBTEMP+4 \| wbtemp mantissa [63:32] (4 bytes)
135	.set WBTEMP_LO,WBTEMP+8 \| wbtemp mantissa [31:00] (4 bytes)
136	\|
137	.set WBTEMP_SGN,WBTEMP+2 \| used to store sign
138	\|
139	.set FPSR_SHADOW,LV-64 \| fpsr shadow reg
140	\|
141	.set FPIARCU,LV-60 \| Instr. addr. reg. for CU (4 bytes)
142	\|
143	.set CMDREG2B,LV-52 \| cmd reg for machine 2
144	.set CMDREG3B,LV-48 \| cmd reg for E3 exceptions (2 bytes)
145	\|
146	.set NMNEXC,LV-44 \| NMNEXC (unsup,snan bits only)
147	.set nmn_unsup_bit,1
148	.set nmn_snan_bit,0
149	\|
150	.set NMCEXC,LV-43 \| NMNEXC & NMCEXC
151	.set nmn_operr_bit,7
152	.set nmn_ovfl_bit,6
153	.set nmn_unfl_bit,5
154	.set nmc_unsup_bit,4
155	.set nmc_snan_bit,3
156	.set nmc_operr_bit,2
157	.set nmc_ovfl_bit,1
158	.set nmc_unfl_bit,0
159	\|
160	.set STAG,LV-40 \| source tag (1 byte)
161	.set WBTEMP_GRS,LV-40 \| alias wbtemp guard, round, sticky
162	.set guard_bit,1 \| guard bit is bit number 1
163	.set round_bit,0 \| round bit is bit number 0
164	.set stag_mask,0xE0 \| upper 3 bits are source tag type
165	.set denorm_bit,7 \| bit determins if denorm or unnorm
166	.set etemp15_bit,4 \| etemp exponent bit #15
167	.set wbtemp66_bit,2 \| wbtemp mantissa bit #66
168	.set wbtemp1_bit,1 \| wbtemp mantissa bit #1
169	.set wbtemp0_bit,0 \| wbtemp mantissa bit #0
170	\|
171	.set STICKY,LV-39 \| holds sticky bit
172	.set sticky_bit,7
173	\|
174	.set CMDREG1B,LV-36 \| cmd reg for E1 exceptions (2 bytes)
175	.set kfact_bit,12 \| distinguishes static/dynamic k-factor
176	\| ;on packed move outs. NOTE: this
177	\| ;equate only works when CMDREG1B is in
178	\| ;a register.
179	\|
180	.set CMDWORD,LV-35 \| command word in cmd1b
181	.set direction_bit,5 \| bit 0 in opclass
182	.set size_bit2,12 \| bit 2 in size field
183	\|
184	.set DTAG,LV-32 \| dest tag (1 byte)
185	.set dtag_mask,0xE0 \| upper 3 bits are dest type tag
186	.set fptemp15_bit,4 \| fptemp exponent bit #15
187	\|
188	.set WB_BYTE,LV-31 \| holds WBTE15 bit (1 byte)
189	.set wbtemp15_bit,4 \| wbtemp exponent bit #15
190	\|
191	.set E_BYTE,LV-28 \| holds E1 and E3 bits (1 byte)
192	.set E1,2 \| which bit is E1 flag
193	.set E3,1 \| which bit is E3 flag
194	.set SFLAG,0 \| which bit is S flag
195	\|
196	.set T_BYTE,LV-27 \| holds T and U bits (1 byte)
197	.set XFLAG,7 \| which bit is X flag
198	.set UFLAG,5 \| which bit is U flag
199	.set TFLAG,4 \| which bit is T flag
200	\|
201	.set FPTEMP,LV-24 \| fptemp (12 bytes)
202	.set FPTEMP_EX,FPTEMP \| fptemp sign and exponent (2 bytes)
203	.set FPTEMP_HI,FPTEMP+4 \| fptemp mantissa [63:32] (4 bytes)
204	.set FPTEMP_LO,FPTEMP+8 \| fptemp mantissa [31:00] (4 bytes)
205	\|
206	.set FPTEMP_SGN,FPTEMP+2 \| used to store sign
207	\|
208	.set ETEMP,LV-12 \| etemp (12 bytes)
209	.set ETEMP_EX,ETEMP \| etemp sign and exponent (2 bytes)
210	.set ETEMP_HI,ETEMP+4 \| etemp mantissa [63:32] (4 bytes)
211	.set ETEMP_LO,ETEMP+8 \| etemp mantissa [31:00] (4 bytes)
212	\|
213	.set ETEMP_SGN,ETEMP+2 \| used to store sign
214	\|
215	.set EXC_SR,4 \| exception frame status register
216	.set EXC_PC,6 \| exception frame program counter
217	.set EXC_VEC,10 \| exception frame vector (format+vector#)
218	.set EXC_EA,12 \| exception frame effective address
219	\|
220	\|--------------------------------------------------------------------------
221	\|
222	\| FPSR/FPCR bits
223	\|
224	.set neg_bit,3 \| negative result
225	.set z_bit,2 \| zero result
226	.set inf_bit,1 \| infinity result
227	.set nan_bit,0 \| not-a-number result
228	\|
229	.set q_sn_bit,7 \| sign bit of quotient byte
230	\|
231	.set bsun_bit,7 \| branch on unordered
232	.set snan_bit,6 \| signalling nan
233	.set operr_bit,5 \| operand error
234	.set ovfl_bit,4 \| overflow
235	.set unfl_bit,3 \| underflow
236	.set dz_bit,2 \| divide by zero
237	.set inex2_bit,1 \| inexact result 2
238	.set inex1_bit,0 \| inexact result 1
239	\|
240	.set aiop_bit,7 \| accrued illegal operation
241	.set aovfl_bit,6 \| accrued overflow
242	.set aunfl_bit,5 \| accrued underflow
243	.set adz_bit,4 \| accrued divide by zero
244	.set ainex_bit,3 \| accrued inexact
245	\|
246	\| FPSR individual bit masks
247	\|
248	.set neg_mask,0x08000000
249	.set z_mask,0x04000000
250	.set inf_mask,0x02000000
251	.set nan_mask,0x01000000
252	\|
253	.set bsun_mask,0x00008000
254	.set snan_mask,0x00004000
255	.set operr_mask,0x00002000
256	.set ovfl_mask,0x00001000
257	.set unfl_mask,0x00000800
258	.set dz_mask,0x00000400
259	.set inex2_mask,0x00000200
260	.set inex1_mask,0x00000100
261	\|
262	.set aiop_mask,0x00000080 \| accrued illegal operation
263	.set aovfl_mask,0x00000040 \| accrued overflow
264	.set aunfl_mask,0x00000020 \| accrued underflow
265	.set adz_mask,0x00000010 \| accrued divide by zero
266	.set ainex_mask,0x00000008 \| accrued inexact
267	\|
268	\| FPSR combinations used in the FPSP
269	\|
270	.set dzinf_mask,inf_mask+dz_mask+adz_mask
271	.set opnan_mask,nan_mask+operr_mask+aiop_mask
272	.set nzi_mask,0x01ffffff \| clears N, Z, and I
273	.set unfinx_mask,unfl_mask+inex2_mask+aunfl_mask+ainex_mask
274	.set unf2inx_mask,unfl_mask+inex2_mask+ainex_mask
275	.set ovfinx_mask,ovfl_mask+inex2_mask+aovfl_mask+ainex_mask
276	.set inx1a_mask,inex1_mask+ainex_mask
277	.set inx2a_mask,inex2_mask+ainex_mask
278	.set snaniop_mask,nan_mask+snan_mask+aiop_mask
279	.set naniop_mask,nan_mask+aiop_mask
280	.set neginf_mask,neg_mask+inf_mask
281	.set infaiop_mask,inf_mask+aiop_mask
282	.set negz_mask,neg_mask+z_mask
283	.set opaop_mask,operr_mask+aiop_mask
284	.set unfl_inx_mask,unfl_mask+aunfl_mask+ainex_mask
285	.set ovfl_inx_mask,ovfl_mask+aovfl_mask+ainex_mask
286	\|
287	\|--------------------------------------------------------------------------
288	\|
289	\| FPCR rounding modes
290	\|
291	.set x_mode,0x00 \| round to extended
292	.set s_mode,0x40 \| round to single
293	.set d_mode,0x80 \| round to double
294	\|
295	.set rn_mode,0x00 \| round nearest
296	.set rz_mode,0x10 \| round to zero
297	.set rm_mode,0x20 \| round to minus infinity
298	.set rp_mode,0x30 \| round to plus infinity
299	\|
300	\|--------------------------------------------------------------------------
301	\|
302	\| Miscellaneous equates
303	\|
304	.set signan_bit,6 \| signalling nan bit in mantissa
305	.set sign_bit,7
306	\|
307	.set rnd_stky_bit,29 \| round/sticky bit of mantissa
308	\| this can only be used if in a data register
309	.set sx_mask,0x01800000 \| set s and x bits in word $48
310	\|
311	.set LOCAL_EX,0
312	.set LOCAL_SGN,2
313	.set LOCAL_HI,4
314	.set LOCAL_LO,8
315	.set LOCAL_GRS,12 \| valid ONLY for FP_SCR1, FP_SCR2
316	\|
317	\|
318	.set norm_tag,0x00 \| tag bits in {7:5} position
319	.set zero_tag,0x20
320	.set inf_tag,0x40
321	.set nan_tag,0x60
322	.set dnrm_tag,0x80
323	\|
324	\| fsave sizes and formats
325	\|
326	.set VER_4,0x40 \| fpsp compatible version numbers
327	\| are in the $40s {$40-$4f}
328	.set VER_40,0x40 \| original version number
329	.set VER_41,0x41 \| revision version number
330	\|
331	.set BUSY_SIZE,100 \| size of busy frame
332	.set BUSY_FRAME,LV-BUSY_SIZE \| start of busy frame
333	\|
334	.set UNIMP_40_SIZE,44 \| size of orig unimp frame
335	.set UNIMP_41_SIZE,52 \| size of rev unimp frame
336	\|
337	.set IDLE_SIZE,4 \| size of idle frame
338	.set IDLE_FRAME,LV-IDLE_SIZE \| start of idle frame
339	\|
340	\| exception vectors
341	\|
342	.set TRACE_VEC,0x2024 \| trace trap
343	.set FLINE_VEC,0x002C \| 'real' F-line
344	.set UNIMP_VEC,0x202C \| unimplemented
345	.set INEX_VEC,0x00C4
346	\|
347	.set dbl_thresh,0x3C01
348	.set sgl_thresh,0x3F81
349	\|

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