| [f9b93da] | 1 | | |
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| 2 | | fpsp.h 3.3 3.3 |
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| 3 | | |
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| 4 | |
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| 5 | | Copyright (C) Motorola, Inc. 1990 |
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| 6 | | All Rights Reserved |
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| 7 | | |
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| 8 | | THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA |
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| 9 | | The copyright notice above does not evidence any |
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| 10 | | actual or intended publication of such source code. |
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| 11 | |
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| 12 | | fpsp.h --- stack frame offsets during FPSP exception handling |
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| 13 | | |
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| 14 | | These equates are used to access the exception frame, the fsave |
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| 15 | | frame and any local variables needed by the FPSP package. |
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| 16 | | |
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| 17 | | All FPSP handlers begin by executing: |
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| 18 | | |
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| 19 | | link a6,#-LOCAL_SIZE |
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| 20 | | fsave -(a7) |
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| 21 | | movem.l d0-d1/a0-a1,USER_DA(a6) |
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| 22 | | fmovem.x fp0-fp3,USER_FP0(a6) |
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| 23 | | fmove.l fpsr/fpcr/fpiar,USER_FPSR(a6) |
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| 24 | | |
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| 25 | | After initialization, the stack looks like this: |
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| 26 | | |
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| 27 | | A7 ---> +-------------------------------+ |
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| 28 | | | | |
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| 29 | | | FPU fsave area | |
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| 30 | | | | |
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| 31 | | +-------------------------------+ |
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| 32 | | | | |
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| 33 | | | FPSP Local Variables | |
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| 34 | | | including | |
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| 35 | | | saved registers | |
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| 36 | | | | |
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| 37 | | +-------------------------------+ |
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| 38 | | A6 ---> | Saved A6 | |
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| 39 | | +-------------------------------+ |
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| 40 | | | | |
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| 41 | | | Exception Frame | |
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| 42 | | | | |
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| 43 | | | | |
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| 44 | | |
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| 45 | | Positive offsets from A6 refer to the exception frame. Negative |
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| 46 | | offsets refer to the Local Variable area and the fsave area. |
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| 47 | | The fsave frame is also accessible 'from the top' via A7. |
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| 48 | | |
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| 49 | | On exit, the handlers execute: |
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| 50 | | |
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| 51 | | movem.l USER_DA(a6),d0-d1/a0-a1 |
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| 52 | | fmovem.x USER_FP0(a6),fp0-fp3 |
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| 53 | | fmove.l USER_FPSR(a6),fpsr/fpcr/fpiar |
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| 54 | | frestore (a7)+ |
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| 55 | | unlk a6 |
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| 56 | | |
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| 57 | | and then either 'bra fpsp_done' if the exception was completely |
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| 58 | | handled by the package, or 'bra real_xxxx' which is an external |
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| 59 | | label to a routine that will process a real exception of the |
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| 60 | | type that was generated. Some handlers may omit the 'frestore' |
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| 61 | | if the FPU state after the exception is idle. |
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| 62 | | |
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| 63 | | Sometimes the exception handler will transform the fsave area |
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| 64 | | because it needs to report an exception back to the user. This |
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| 65 | | can happen if the package is entered for an unimplemented float |
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| 66 | | instruction that generates (say) an underflow. Alternatively, |
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| 67 | | a second fsave frame can be pushed onto the stack and the |
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| 68 | | handler exit code will reload the new frame and discard the old. |
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| 69 | | |
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| 70 | | The registers d0, d1, a0, a1 and fp0-fp3 are always saved and |
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| 71 | | restored from the 'local variable' area and can be used as |
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| 72 | | temporaries. If a routine needs to change any |
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| 73 | | of these registers, it should modify the saved copy and let |
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| 74 | | the handler exit code restore the value. |
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| 75 | | |
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| 76 | |---------------------------------------------------------------------- |
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| 77 | | |
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| 78 | | Local Variables on the stack |
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| 79 | | |
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| 80 | .set LOCAL_SIZE,192 | bytes needed for local variables |
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| 81 | .set LV,-LOCAL_SIZE | convenient base value |
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| 82 | | |
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| 83 | .set USER_DA,LV+0 | save space for D0-D1,A0-A1 |
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| 84 | .set USER_D0,LV+0 | saved user D0 |
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| 85 | .set USER_D1,LV+4 | saved user D1 |
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| 86 | .set USER_A0,LV+8 | saved user A0 |
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| 87 | .set USER_A1,LV+12 | saved user A1 |
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| 88 | .set USER_FP0,LV+16 | saved user FP0 |
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| 89 | .set USER_FP1,LV+28 | saved user FP1 |
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| 90 | .set USER_FP2,LV+40 | saved user FP2 |
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| 91 | .set USER_FP3,LV+52 | saved user FP3 |
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| 92 | .set USER_FPCR,LV+64 | saved user FPCR |
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| 93 | .set FPCR_ENABLE,USER_FPCR+2 | FPCR exception enable |
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| 94 | .set FPCR_MODE,USER_FPCR+3 | FPCR rounding mode control |
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| 95 | .set USER_FPSR,LV+68 | saved user FPSR |
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| 96 | .set FPSR_CC,USER_FPSR+0 | FPSR condition code |
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| 97 | .set FPSR_QBYTE,USER_FPSR+1 | FPSR quotient |
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| 98 | .set FPSR_EXCEPT,USER_FPSR+2 | FPSR exception |
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| 99 | .set FPSR_AEXCEPT,USER_FPSR+3 | FPSR accrued exception |
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| 100 | .set USER_FPIAR,LV+72 | saved user FPIAR |
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| 101 | .set FP_SCR1,LV+76 | room for a temporary float value |
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| 102 | .set FP_SCR2,LV+92 | room for a temporary float value |
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| 103 | .set L_SCR1,LV+108 | room for a temporary long value |
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| 104 | .set L_SCR2,LV+112 | room for a temporary long value |
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| 105 | .set STORE_FLG,LV+116 |
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| 106 | .set BINDEC_FLG,LV+117 | used in bindec |
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| 107 | .set DNRM_FLG,LV+118 | used in res_func |
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| 108 | .set RES_FLG,LV+119 | used in res_func |
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| 109 | .set DY_MO_FLG,LV+120 | dyadic/monadic flag |
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| 110 | .set UFLG_TMP,LV+121 | temporary for uflag errata |
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| 111 | .set CU_ONLY,LV+122 | cu-only flag |
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| 112 | .set VER_TMP,LV+123 | temp holding for version number |
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| 113 | .set L_SCR3,LV+124 | room for a temporary long value |
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| 114 | .set FP_SCR3,LV+128 | room for a temporary float value |
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| 115 | .set FP_SCR4,LV+144 | room for a temporary float value |
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| 116 | .set FP_SCR5,LV+160 | room for a temporary float value |
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| 117 | .set FP_SCR6,LV+176 |
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| 118 | | |
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| 119 | |NEXT equ LV+192 ;need to increase LOCAL_SIZE |
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| 120 | | |
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| 121 | |-------------------------------------------------------------------------- |
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| 122 | | |
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| 123 | | fsave offsets and bit definitions |
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| 124 | | |
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| 125 | | Offsets are defined from the end of an fsave because the last 10 |
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| 126 | | words of a busy frame are the same as the unimplemented frame. |
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| 127 | | |
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| 128 | .set CU_SAVEPC,LV-92 | micro-pc for CU (1 byte) |
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| 129 | .set FPR_DIRTY_BITS,LV-91 | fpr dirty bits |
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| 130 | | |
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| 131 | .set WBTEMP,LV-76 | write back temp (12 bytes) |
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| 132 | .set WBTEMP_EX,WBTEMP | wbtemp sign and exponent (2 bytes) |
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| 133 | .set WBTEMP_HI,WBTEMP+4 | wbtemp mantissa [63:32] (4 bytes) |
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| 134 | .set WBTEMP_LO,WBTEMP+8 | wbtemp mantissa [31:00] (4 bytes) |
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| 135 | | |
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| 136 | .set WBTEMP_SGN,WBTEMP+2 | used to store sign |
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| 137 | | |
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| 138 | .set FPSR_SHADOW,LV-64 | fpsr shadow reg |
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| 139 | | |
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| 140 | .set FPIARCU,LV-60 | Instr. addr. reg. for CU (4 bytes) |
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| 141 | | |
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| 142 | .set CMDREG2B,LV-52 | cmd reg for machine 2 |
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| 143 | .set CMDREG3B,LV-48 | cmd reg for E3 exceptions (2 bytes) |
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| 144 | | |
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| 145 | .set NMNEXC,LV-44 | NMNEXC (unsup,snan bits only) |
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| 146 | .set nmn_unsup_bit,1 |
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| 147 | .set nmn_snan_bit,0 |
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| 148 | | |
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| 149 | .set NMCEXC,LV-43 | NMNEXC & NMCEXC |
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| 150 | .set nmn_operr_bit,7 |
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| 151 | .set nmn_ovfl_bit,6 |
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| 152 | .set nmn_unfl_bit,5 |
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| 153 | .set nmc_unsup_bit,4 |
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| 154 | .set nmc_snan_bit,3 |
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| 155 | .set nmc_operr_bit,2 |
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| 156 | .set nmc_ovfl_bit,1 |
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| 157 | .set nmc_unfl_bit,0 |
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| 158 | | |
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| 159 | .set STAG,LV-40 | source tag (1 byte) |
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| 160 | .set WBTEMP_GRS,LV-40 | alias wbtemp guard, round, sticky |
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| 161 | .set guard_bit,1 | guard bit is bit number 1 |
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| 162 | .set round_bit,0 | round bit is bit number 0 |
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| 163 | .set stag_mask,0xE0 | upper 3 bits are source tag type |
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| 164 | .set denorm_bit,7 | bit determins if denorm or unnorm |
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| 165 | .set etemp15_bit,4 | etemp exponent bit #15 |
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| 166 | .set wbtemp66_bit,2 | wbtemp mantissa bit #66 |
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| 167 | .set wbtemp1_bit,1 | wbtemp mantissa bit #1 |
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| 168 | .set wbtemp0_bit,0 | wbtemp mantissa bit #0 |
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| 169 | | |
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| 170 | .set STICKY,LV-39 | holds sticky bit |
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| 171 | .set sticky_bit,7 |
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| 172 | | |
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| 173 | .set CMDREG1B,LV-36 | cmd reg for E1 exceptions (2 bytes) |
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| 174 | .set kfact_bit,12 | distinguishes static/dynamic k-factor |
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| 175 | | ;on packed move outs. NOTE: this |
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| 176 | | ;equate only works when CMDREG1B is in |
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| 177 | | ;a register. |
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| 178 | | |
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| 179 | .set CMDWORD,LV-35 | command word in cmd1b |
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| 180 | .set direction_bit,5 | bit 0 in opclass |
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| 181 | .set size_bit2,12 | bit 2 in size field |
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| 182 | | |
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| 183 | .set DTAG,LV-32 | dest tag (1 byte) |
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| 184 | .set dtag_mask,0xE0 | upper 3 bits are dest type tag |
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| 185 | .set fptemp15_bit,4 | fptemp exponent bit #15 |
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| 186 | | |
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| 187 | .set WB_BYTE,LV-31 | holds WBTE15 bit (1 byte) |
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| 188 | .set wbtemp15_bit,4 | wbtemp exponent bit #15 |
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| 189 | | |
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| 190 | .set E_BYTE,LV-28 | holds E1 and E3 bits (1 byte) |
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| 191 | .set E1,2 | which bit is E1 flag |
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| 192 | .set E3,1 | which bit is E3 flag |
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| 193 | .set SFLAG,0 | which bit is S flag |
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| 194 | | |
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| 195 | .set T_BYTE,LV-27 | holds T and U bits (1 byte) |
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| 196 | .set XFLAG,7 | which bit is X flag |
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| 197 | .set UFLAG,5 | which bit is U flag |
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| 198 | .set TFLAG,4 | which bit is T flag |
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| 199 | | |
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| 200 | .set FPTEMP,LV-24 | fptemp (12 bytes) |
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| 201 | .set FPTEMP_EX,FPTEMP | fptemp sign and exponent (2 bytes) |
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| 202 | .set FPTEMP_HI,FPTEMP+4 | fptemp mantissa [63:32] (4 bytes) |
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| 203 | .set FPTEMP_LO,FPTEMP+8 | fptemp mantissa [31:00] (4 bytes) |
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| 204 | | |
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| 205 | .set FPTEMP_SGN,FPTEMP+2 | used to store sign |
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| 206 | | |
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| 207 | .set ETEMP,LV-12 | etemp (12 bytes) |
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| 208 | .set ETEMP_EX,ETEMP | etemp sign and exponent (2 bytes) |
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| 209 | .set ETEMP_HI,ETEMP+4 | etemp mantissa [63:32] (4 bytes) |
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| 210 | .set ETEMP_LO,ETEMP+8 | etemp mantissa [31:00] (4 bytes) |
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| 211 | | |
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| 212 | .set ETEMP_SGN,ETEMP+2 | used to store sign |
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| 213 | | |
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| 214 | .set EXC_SR,4 | exception frame status register |
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| 215 | .set EXC_PC,6 | exception frame program counter |
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| 216 | .set EXC_VEC,10 | exception frame vector (format+vector#) |
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| 217 | .set EXC_EA,12 | exception frame effective address |
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| 218 | | |
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| 219 | |-------------------------------------------------------------------------- |
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| 220 | | |
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| 221 | | FPSR/FPCR bits |
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| 222 | | |
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| 223 | .set neg_bit,3 | negative result |
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| 224 | .set z_bit,2 | zero result |
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| 225 | .set inf_bit,1 | infinity result |
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| 226 | .set nan_bit,0 | not-a-number result |
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| 227 | | |
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| 228 | .set q_sn_bit,7 | sign bit of quotient byte |
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| 229 | | |
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| 230 | .set bsun_bit,7 | branch on unordered |
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| 231 | .set snan_bit,6 | signalling nan |
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| 232 | .set operr_bit,5 | operand error |
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| 233 | .set ovfl_bit,4 | overflow |
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| 234 | .set unfl_bit,3 | underflow |
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| 235 | .set dz_bit,2 | divide by zero |
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| 236 | .set inex2_bit,1 | inexact result 2 |
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| 237 | .set inex1_bit,0 | inexact result 1 |
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| 238 | | |
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| 239 | .set aiop_bit,7 | accrued illegal operation |
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| 240 | .set aovfl_bit,6 | accrued overflow |
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| 241 | .set aunfl_bit,5 | accrued underflow |
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| 242 | .set adz_bit,4 | accrued divide by zero |
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| 243 | .set ainex_bit,3 | accrued inexact |
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| 244 | | |
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| 245 | | FPSR individual bit masks |
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| 246 | | |
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| 247 | .set neg_mask,0x08000000 |
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| 248 | .set z_mask,0x04000000 |
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| 249 | .set inf_mask,0x02000000 |
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| 250 | .set nan_mask,0x01000000 |
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| 251 | | |
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| 252 | .set bsun_mask,0x00008000 |
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| 253 | .set snan_mask,0x00004000 |
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| 254 | .set operr_mask,0x00002000 |
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| 255 | .set ovfl_mask,0x00001000 |
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| 256 | .set unfl_mask,0x00000800 |
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| 257 | .set dz_mask,0x00000400 |
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| 258 | .set inex2_mask,0x00000200 |
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| 259 | .set inex1_mask,0x00000100 |
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| 260 | | |
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| 261 | .set aiop_mask,0x00000080 | accrued illegal operation |
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| 262 | .set aovfl_mask,0x00000040 | accrued overflow |
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| 263 | .set aunfl_mask,0x00000020 | accrued underflow |
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| 264 | .set adz_mask,0x00000010 | accrued divide by zero |
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| 265 | .set ainex_mask,0x00000008 | accrued inexact |
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| 266 | | |
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| 267 | | FPSR combinations used in the FPSP |
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| 268 | | |
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| 269 | .set dzinf_mask,inf_mask+dz_mask+adz_mask |
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| 270 | .set opnan_mask,nan_mask+operr_mask+aiop_mask |
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| 271 | .set nzi_mask,0x01ffffff | clears N, Z, and I |
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| 272 | .set unfinx_mask,unfl_mask+inex2_mask+aunfl_mask+ainex_mask |
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| 273 | .set unf2inx_mask,unfl_mask+inex2_mask+ainex_mask |
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| 274 | .set ovfinx_mask,ovfl_mask+inex2_mask+aovfl_mask+ainex_mask |
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| 275 | .set inx1a_mask,inex1_mask+ainex_mask |
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| 276 | .set inx2a_mask,inex2_mask+ainex_mask |
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| 277 | .set snaniop_mask,nan_mask+snan_mask+aiop_mask |
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| 278 | .set naniop_mask,nan_mask+aiop_mask |
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| 279 | .set neginf_mask,neg_mask+inf_mask |
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| 280 | .set infaiop_mask,inf_mask+aiop_mask |
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| 281 | .set negz_mask,neg_mask+z_mask |
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| 282 | .set opaop_mask,operr_mask+aiop_mask |
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| 283 | .set unfl_inx_mask,unfl_mask+aunfl_mask+ainex_mask |
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| 284 | .set ovfl_inx_mask,ovfl_mask+aovfl_mask+ainex_mask |
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| 285 | | |
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| 286 | |-------------------------------------------------------------------------- |
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| 287 | | |
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| 288 | | FPCR rounding modes |
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| 289 | | |
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| 290 | .set x_mode,0x00 | round to extended |
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| 291 | .set s_mode,0x40 | round to single |
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| 292 | .set d_mode,0x80 | round to double |
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| 293 | | |
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| 294 | .set rn_mode,0x00 | round nearest |
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| 295 | .set rz_mode,0x10 | round to zero |
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| 296 | .set rm_mode,0x20 | round to minus infinity |
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| 297 | .set rp_mode,0x30 | round to plus infinity |
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| 298 | | |
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| 299 | |-------------------------------------------------------------------------- |
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| 300 | | |
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| 301 | | Miscellaneous equates |
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| 302 | | |
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| 303 | .set signan_bit,6 | signalling nan bit in mantissa |
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| 304 | .set sign_bit,7 |
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| 305 | | |
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| 306 | .set rnd_stky_bit,29 | round/sticky bit of mantissa |
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| 307 | | this can only be used if in a data register |
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| 308 | .set sx_mask,0x01800000 | set s and x bits in word $48 |
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| 309 | | |
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| 310 | .set LOCAL_EX,0 |
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| 311 | .set LOCAL_SGN,2 |
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| 312 | .set LOCAL_HI,4 |
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| 313 | .set LOCAL_LO,8 |
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| 314 | .set LOCAL_GRS,12 | valid ONLY for FP_SCR1, FP_SCR2 |
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| 315 | | |
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| 316 | | |
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| 317 | .set norm_tag,0x00 | tag bits in {7:5} position |
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| 318 | .set zero_tag,0x20 |
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| 319 | .set inf_tag,0x40 |
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| 320 | .set nan_tag,0x60 |
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| 321 | .set dnrm_tag,0x80 |
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| 322 | | |
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| 323 | | fsave sizes and formats |
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| 324 | | |
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| 325 | .set VER_4,0x40 | fpsp compatible version numbers |
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| 326 | | are in the $40s {$40-$4f} |
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| 327 | .set VER_40,0x40 | original version number |
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| 328 | .set VER_41,0x41 | revision version number |
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| 329 | | |
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| 330 | .set BUSY_SIZE,100 | size of busy frame |
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| 331 | .set BUSY_FRAME,LV-BUSY_SIZE | start of busy frame |
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| 332 | | |
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| 333 | .set UNIMP_40_SIZE,44 | size of orig unimp frame |
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| 334 | .set UNIMP_41_SIZE,52 | size of rev unimp frame |
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| 335 | | |
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| 336 | .set IDLE_SIZE,4 | size of idle frame |
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| 337 | .set IDLE_FRAME,LV-IDLE_SIZE | start of idle frame |
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| 338 | | |
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| 339 | | exception vectors |
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| 340 | | |
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| 341 | .set TRACE_VEC,0x2024 | trace trap |
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| 342 | .set FLINE_VEC,0x002C | 'real' F-line |
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| 343 | .set UNIMP_VEC,0x202C | unimplemented |
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| 344 | .set INEX_VEC,0x00C4 |
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| 345 | | |
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| 346 | .set dbl_thresh,0x3C01 |
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| 347 | .set sgl_thresh,0x3F81 |
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| 348 | | |
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