source: rtems/c/src/lib/libcpu/i960/include/i960RP.h @ bc85fd5a

4.104.114.84.9
Last change on this file since bc85fd5a was bc85fd5a, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 11, 2000 at 7:31:04 PM

Reworked score/cpu/i960 so it can be safely compiled multilib. All
routines and structures that require CPU model specific information
are now in libcpu. This required significant rework of the
score/cpu header files and the creation of multiple header files
and subdirectories in libcpu/i960.

  • Property mode set to 100644
File size: 12.8 KB
Line 
1/*
2 *  i960RP Related Definitions.
3 *
4 *  NOTE:  There is some commonality with the JX series which is
5 *         not currently supported by RTEMS.
6 *
7 *  $Id$
8 */
9
10#ifndef __I960RP_h
11#define __I960RP_h
12
13/* i960RP control structures */
14
15/* Intel i960RP Control Table */
16
17typedef struct {
18                            /* Control Group 0 */
19  unsigned int rsvd00;
20  unsigned int rsvd01;
21  unsigned int rsvd02;
22  unsigned int rsvd03;
23                            /* Control Group 1 */
24  unsigned int imap0;             /* interrupt map 0 */
25  unsigned int imap1;             /* interrupt map 1 */
26  unsigned int imap2;             /* interrupt map 2 */
27  unsigned int icon;              /* interrupt control */
28                            /* Control Group 2 */
29  unsigned int pmcon0;            /* memory region 0 configuration */
30  unsigned int rsvd1;
31  unsigned int pmcon2;            /* memory region 2 configuration */
32  unsigned int rsvd2;
33                            /* Control Group 3 */
34  unsigned int pmcon4;            /* memory region 4 configuration */
35  unsigned int rsvd3;
36  unsigned int pmcon6;            /* memory region 6 configuration */
37  unsigned int rsvd4;
38                            /* Control Group 4 */
39  unsigned int pmcon8;            /* memory region 8 configuration */
40  unsigned int rsvd5;
41  unsigned int pmcon10;           /* memory region 10 configuration */
42  unsigned int rsvd6;
43                            /* Control Group 5 */
44  unsigned int pmcon12;           /* memory region 12 configuration */
45  unsigned int rsvd7;
46  unsigned int pmcon14;           /* memory region 14 configuration */
47  unsigned int rsvd8;
48                            /* Control Group 6 */
49  unsigned int rsvd9;
50  unsigned int rsvd10;
51  unsigned int tc;                /* trace control */
52  unsigned int bcon;              /* bus configuration control */
53}   i960rp_control_table;
54
55/* Intel i960RP Processor Control Block */
56
57/* Intel i960RP Processor Control Block */
58
59typedef struct { 
60  unsigned int    *fault_tbl;     /* fault table base address */
61  i960rp_control_table
62                  *control_tbl;   /* control table base address */
63  unsigned int     initial_ac;    /* AC register initial value */
64  unsigned int     fault_config;  /* fault configuration word */
65  void           **intr_tbl;      /* interrupt table base address */
66  void            *sys_proc_tbl;  /* system procedure table
67                                     base address */
68  unsigned int     reserved;      /* reserved */
69  unsigned int    *intr_stack;    /* interrupt stack pointer */
70  unsigned int     ins_cache_cfg; /* instruction cache
71                                     configuration word */
72  unsigned int     reg_cache_cfg; /* register cache configuration word */
73}   i960rp_PRCB;
74
75typedef i960rp_control_table i960_control_table;
76typedef i960rp_PRCB i960_PRCB;
77
78/* Addresses shared with JX */
79
80#include <libcpu/i960JX_RP_common.h>
81
82/* RP-only addresses: */
83/* RP MMRs */
84
85/* PCI-to-PCI Bridge Unit 0000 1000H through 0000 10FFH */
86#define VIDR_ADDR 0x00001000
87#define DIDR_ADDR 0x00001002
88#define PCMDR_ADDR 0x00001004
89#define PSR_ADDR 0x00001006
90#define RIDR_ADDR 0x00001008
91#define CCR_ADDR 0x00001009
92#define CLSR_ADDR 0x0000100C
93#define PLTR_ADDR 0x0000100D
94#define HTR_ADDR 0x0000100E
95/* Reserved 0x0000100F through  0x00001017 */
96#define PBNR_ADDR 0x00001018
97#define SBNR_ADDR 0x00001019
98#define SUBBNR_ADDR 0x0000101A
99#define SLTR_ADDR 0x0000101B
100#define IOBR_ADDR 0x0000101C
101#define IOLR_ADDR 0x0000101D
102#define SSR_ADDR 0x0000101E
103#define MBR_ADDR 0x00001020
104#define MLR_ADDR 0x00001022
105#define PMBR_ADDR 0x00001024
106#define PMLR_ADDR 0x00001026
107/* Reserved 0x00001028 through 0x00001033 */
108#define BSVIR_ADDR 0x00001034
109#define BSIR_ADDR 0x00001036
110/* Reserved 0x00001038 through 0x0000103D */
111#define BCR_ADDR 0x0000103E
112#define EBCR_ADDR 0x00001040
113#define SISR_ADDR 0x00001042
114#define PBISR_ADDR 0x00001044
115#define SBISR_ADDR 0x00001048
116#define SACR_ADDR 0x0000104C
117#define PIRSR_ADDR 0x00001050
118#define SIOBR_ADDR 0x00001054
119#define SIOLR_ADDR 0x00001055
120#define SMBR_ADDR 0x00001058
121#define SMLR_ADDR 0x0000105A
122#define SDER_ADDR 0x0000105C
123/* Reserved 0x0000105E through 0x000011FFH */
124
125/* Address Translation Unit 0000 1200H through 0000 12FFH */
126#define ATUVID_ADDR 0x00001200
127#define ATUDID_ADDR 0x00001202
128#define PATUCMD_ADDR 0x00001204
129#define PATUSR_ADDR 0x00001206
130#define ATURID_ADDR 0x00001208
131#define ATUCCR_ADDR 0x00001209
132#define ATUCLSR_ADDR 0x0000120C
133#define ATULT_ADDR 0x0000120D
134#define ATUHTR_ADDR 0x0000120E
135#define ATUBISTR_ADDR 0x0000120F
136#define PIABAR_ADDR 0x00001210
137/* Reserved 0x00001214 */
138/* Reserved 0x00001218 */
139/* Reserved 0x0000121C */
140/* Reserved 0x00001220 */
141/* Reserved 0x00001224 */
142/* Reserved 0x00001228 */
143#define ASVIR_ADDR 0x0000122C
144#define ASIR_ADDR 0x0000122E
145#define ERBAR_ADDR 0x00001230
146/* Reserved 0x00001234 */
147/* Reserved 0x00001238 */
148#define ATUILR_ADDR 0x0000123C
149#define ATUIPR_ADDR 0x0000123D
150#define ATUMGNT_ADDR 0x0000123E
151#define ATUMLAT_ADDR 0x0000123F
152#define PIALR_ADDR 0x00001240
153#define PIATVR_ADDR 0x00001244
154#define SIABAR_ADDR 0x00001248
155#define SIALR_ADDR 0x0000124C
156#define SIATVR_ADDR 0x00001250
157#define POMWVR_ADDR 0x00001254
158/* Reserved 0x00001258 */
159#define POIOWVR_ADDR 0x0000125C
160#define PODWVR_ADDR 0x00001260
161#define POUDR_ADDR 0x00001264
162#define SOMWVR_ADDR 0x00001268
163#define SOIOWVR_ADDR 0x0000126C
164/* Reserved 0x00001270 */
165#define ERLR_ADDR 0x00001274
166#define ERTVR_ADDR 0x00001278
167/* Reserved 0x0000127C */
168/* Reserved 0x00001280 */
169/* Reserved 0x00001284 */
170#define ATUCR_ADDR 0x00001288
171/* Reserved 0x0000128C */
172#define PATUISR_ADDR 0x00001290
173#define SATUISR_ADDR 0x00001294
174#define SATUCMD_ADDR 0x00001298
175#define SATUSR_ADDR 0x0000129A
176#define SODWVR_ADDR 0x0000129C
177#define SOUDR_ADDR 0x000012A0
178#define POCCAR_ADDR 0x000012A4
179#define SOCCAR_ADDR 0x000012A8
180#define POCCDR_ADDR 0x000012AC
181#define SOCCDR_ADDR 0x000012B0
182/* Reserved 0x000012B4 through 0x000012FF */
183
184/* Messaging Unit 0000 1300H through 0000 13FFH */
185#define ARSR_ADDR 0x00001300
186/* Reserved 0x00001304 */
187#define AWR_ADDR 0x00001308
188/* Reserved 0x0000130C */
189#define IMR0_ADDR 0x00001310
190#define IMR1_ADDR 0x00001314
191#define OMR0_ADDR 0x00001318
192#define OMR1_ADDR 0x0000131C
193#define IDR_ADDR 0x00001320
194#define IISR_ADDR 0x00001324
195#define IIMR_ADDR 0x00001328
196#define ODR_ADDR 0x0000132C
197#define OISR_ADDR 0x00001330
198#define OIMR_ADDR 0x00001334
199/* Reserved 0x00001338 through 0x0000134F */
200#define MUCR_ADDR 0x00001350
201#define QBAR_ADDR 0x00001354
202/* Reserved 0x00001358 */
203/* Reserved 0x0000135C */
204#define IFHPR_ADDR 0x00001360
205#define IFTPR_ADDR 0x00001364
206#define IPHPR_ADDR 0x00001368
207#define IPTPR_ADDR 0x0000136C
208#define OFHPR_ADDR 0x00001370
209#define OFTPR_ADDR 0x00001374
210#define OPHPR_ADDR 0x00001378
211#define OPTPR_ADDR 0x0000137C
212#define IAR_ADDR 0x00001380
213/* Reserved 0x00001384 through 0x000013FF */
214
215/* DMA Controller 0000 1400H through 0000 14FFH */
216#define CCR0_ADDR 0x00001400
217#define CSR0_ADDR 0x00001404
218/* Reserved 0x00001408 */
219#define DAR0_ADDR 0x0000140C
220#define NDAR0_ADDR 0x00001410
221#define PADR0_ADDR 0x00001414
222#define PUADR0_ADDR 0x00001418
223#define LADR0_ADDR 0x0000141C
224#define BCR0_ADDR 0x00001420
225#define DCR0_ADDR 0x00001424
226/* Reserved 0x00001428 through 0x0000143F */
227#define CCR1_ADDR 0x00001440
228#define CSR1_ADDR 0x00001444
229/* Reserved 0x00001448 */
230#define DAR1_ADDR 0x0000144C
231#define NDAR1_ADDR 0x00001450
232#define PADR1_ADDR 0x00001454
233#define PUADR1_ADDR 0x00001458
234#define LADR1_ADDR 0x0000145C
235#define BCR1_ADDR 0x00001460
236#define DCR1_ADDR 0x00001464
237/* Reserved 0x00001468 through 0x0000147F */
238#define CCR2_ADDR 0x00001480
239#define CSR2_ADDR 0x00001484
240/* Reserved 0x00001488 */
241#define DAR2_ADDR 0x0000148C
242#define NDAR2_ADDR 0x00001490
243#define PADR2_ADDR 0x00001494
244#define PUADR2_ADDR 0x00001498
245#define LADR2_ADDR 0x0000149C
246#define BCR2_ADDR 0x000014A0
247#define DCR2_ADDR 0x000014A4
248/* Reserved 0x000014A8 through 0x000014FF */
249
250/* Memory Controller 0000 1500H through 0000 15FFH */
251#define MBCR_ADDR 0x00001500
252#define MBBAR0_ADDR 0x00001504
253#define MBRWS0_ADDR 0x00001508
254#define MBWWS0_ADDR 0x0000150C
255#define MBBAR1_ADDR 0x00001510
256#define MBRWS1_ADDR 0x00001514
257#define MBWWS1_ADDR 0x00001518
258#define DBCR_ADDR 0x0000151C
259#define DBAR_ADDR 0x00001520
260#define DRWS_ADDR 0x00001524
261#define DWWS_ADDR 0x00001528
262#define DRIR_ADDR 0x0000152C
263#define DPER_ADDR 0x00001530
264#define BMER_ADDR 0x00001534
265#define MEAR_ADDR 0x00001538
266#define LPISR_ADDR 0x0000153C
267/* Reserved 0x00001540 through 0x000015FF */
268
269/* Local Bus Arbitration Unit 0000 1600H through 0000 167FH
270*/
271#define LBACR_ADDR 0x00001600
272#define LBALCR_ADDR 0x00001604
273/* Reserved 0x00001608 through 0x0000167F */
274
275/* I2C Bus Interface Unit 0000 1680H through 0000 16FFH */
276#define ICR_ADDR 0x00001680
277#define ISR_ADDR 0x00001684
278#define ISAR_ADDR 0x00001688
279#define IDBR_ADDR 0x0000168C
280#define ICCR_ADDR 0x00001690
281/* Reserved 0x00001694 through 0x000016FF */
282
283/* PCI And Peripheral Interrupt Controller 0000 1700H through
2840000 177FH */
285#define NISR_ADDR 0x00001700
286#define X7ISR_ADDR 0x00001704
287#define X6ISR_ADDR 0x00001708
288#define PDDIR_ADDR 0x00001710
289/* Reserved 0x00001714 through 0x0000177F */
290
291/* APIC Bus Interface Unit 0000 1780H through 0000 17FFH */
292#define APICIDR_ADDR 0x00001780
293#define APICARBID_ADDR 0x00001784
294#define EVR_ADDR 0x00001788
295#define IMR_ADDR 0x0000178C
296#define APICCSR_ADDR 0x00001790
297/* Reserved 0x00001794 through 0x000017FF  */
298
299/* Byte order bit for region configuration */
300/* Set to Little Endian for the 80960RP*/
301#define I960RP_BYTE_ORDER I960RP_BIG_ENDIAN(0)
302#define I960RP_BUS_WIDTH(bw)  ((bw==16)?(1<<22):(0)) | ((bw==32)?(2<<22):(0))
303#define I960RP_BIG_ENDIAN(on) ((on)?(0x1<<31):0)
304#define I960RP_BYTE_N(n,data)  (((unsigned)(data) >> (n*8)) & 0xFF)
305#define I960RP_BUS_WIDTH_8 0
306#define I960RP_BUS_WIDTH_16 (1<<22)
307#define I960RP_BUS_WIDTH_32 (1<<23)
308
309
310/* ATU Register Definitions */
311
312#define ATUCR_SECOUTEN 0x4
313#define ATUCR_PRIOUTEN 0x2
314#define ATUCR_DADRSELEN  0x100
315#define ATUCR_SECDADREN  0x80
316#define AUTCR_SECERRINTEN 0x20
317#define AUTCR_PRIERRINTEN 0x10
318
319#define ATUSCMD_IOEN 0x1
320#define ATUSCMD_MEMEN 0x2
321#define ATUSCMD_BUSMSTEN 0x4
322
323#define ATUPCMD_IOEN 0x1
324#define ATUPCMD_MEMEN 0x2
325#define ATUPCMD_BUSMSTEN 0x4
326
327/* EBCR Register Definitions */
328#define EBCR_CCR_MASK   0x4
329
330#define rp_readreg32( x) ( *((unsigned int *) x))
331#define rp_writereg32( x, v) ( *((unsigned int *) x) = v)
332#define rp_readreg16( x) ( *((unsigned short *) x))
333#define rp_writereg16( x, v) ( *((unsigned short *) x) = v)
334#define rp_readreg8( x) ( *((unsigned char *) x))
335#define rp_writereg8( x, v) ( *((unsigned char *) x) = v)
336
337
338/* i960 Memory Map values */
339
340#define RP_PRI_IO_WIND_BASE     0x90000000
341#define RP_SEC_IO_WIND_BASE     0x90010000
342#define RP_SEC_MEM_WIND_BASE    0x88000000
343#define RP_PRI_MEM_WIND_BASE    0x80000000
344
345#define i960_unmask_intr( xint ) \
346 { register unsigned int _mask= (1<<(xint)); \
347   register unsigned int *_imsk = (int * ) IMSK_ADDR; \
348   register unsigned int _val= *_imsk; \
349   asm volatile( "or %0,%2,%0; \
350                  st %0,(%1)" \
351                    : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
352                    : "0" (_val), "1" (_imsk), "2" (_mask) ); \
353 }
354
355#define i960_mask_intr( xint ) \
356 { register unsigned int _mask= (1<<(xint)); \
357   register unsigned int *_imsk = (int * ) IMSK_ADDR; \
358   register unsigned int _val = *_imsk; \
359   asm volatile( "andnot %2,%0,%0; \
360                  st %0,(%1)" \
361                    : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
362                    : "0" (_val), "1" (_imsk), "2" (_mask) ); \
363 }
364#define i960_clear_intr( xint ) \
365 { register unsigned int _xint=xint; \
366   register unsigned int _mask=(1<<(xint)); \
367   register unsigned int *_ipnd = (int * ) IPND_ADDR; \
368   register unsigned int          _rslt = 0; \
369asm volatile( "loop_til_cleared: mov 0, %0; \
370                  atmod %1, %2, %0; \
371                  bbs    %3,%0, loop_til_cleared" \
372                  : "=d" (_rslt), "=d" (_ipnd), "=d" (_mask), "=d" (_xint) \
373                  : "0"  (_rslt), "1"  (_ipnd), "2"  (_mask), "3"  (_xint) ); \
374 }
375
376static inline unsigned int i960_pend_intrs()
377{ register unsigned int _intr= *(unsigned int *) IPND_ADDR;
378  /*register unsigned int *_ipnd = (int * ) IPND_ADDR; \
379   asm volatile( "mov (%0),%1" \
380                    : "=d" (_ipnd), "=d" (_mask) \
381                    : "0" (_ipnd), "1" (_mask) ); \ */
382  return ( _intr );
383}
384
385static inline unsigned int i960_mask_intrs()
386{ register unsigned int _intr= *(unsigned int *) IMSK_ADDR;
387  /*asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );*/
388  return( _intr );
389}
390
391#define I960_SOFT_RESET_COMMAND 0x300
392
393#define i960_soft_reset( prcb ) \
394 { register i960_PRCB    *_prcb = (prcb); \
395   register unsigned int *_next=0; \
396   register unsigned int  _cmd  = I960_SOFT_RESET_COMMAND; \
397   asm volatile( "lda    next,%1; \
398                  sysctl %0,%1,%2; \
399            next: mov    g0,g0" \
400                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
401                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
402 }
403
404
405#endif
406/* end of include file */
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