source: rtems/c/src/lib/libcpu/i960/include/i960HA.h @ 073e2411

4.104.114.84.95
Last change on this file since 073e2411 was bc85fd5a, checked in by Joel Sherrill <joel.sherrill@…>, on 07/11/00 at 19:31:04

Reworked score/cpu/i960 so it can be safely compiled multilib. All
routines and structures that require CPU model specific information
are now in libcpu. This required significant rework of the
score/cpu header files and the creation of multiple header files
and subdirectories in libcpu/i960.
  • Property mode set to 100644
File size: 3.7 KB
Line 
1/*
2 *  i960ha
3 *
4 *  $Id$
5 */
6
7#ifndef __i960HA_h
8#define __i960HA_h
9
10
11
12/* i960HA control structures */
13
14/* Intel i960HA Control Table */
15
16typedef struct {
17                            /* Control Group 0 */
18  unsigned int ipb0;              /* IP breakpoint 0 */
19  unsigned int ipb1;              /* IP breakpoint 1 */
20  unsigned int dab0;              /* data address breakpoint 0 */
21  unsigned int dab1;              /* data address breakpoint 1 */
22                            /* Control Group 1 */
23  unsigned int imap0;             /* interrupt map 0 */
24  unsigned int imap1;             /* interrupt map 1 */
25  unsigned int imap2;             /* interrupt map 2 */
26  unsigned int icon;              /* interrupt control */
27                            /* Control Group 2 */
28  unsigned int mcon0;             /* memory region 0 configuration */
29  unsigned int mcon1;             /* memory region 1 configuration */
30  unsigned int mcon2;             /* memory region 2 configuration */
31  unsigned int mcon3;             /* memory region 3 configuration */
32                            /* Control Group 3 */
33  unsigned int mcon4;             /* memory region 4 configuration */
34  unsigned int mcon5;             /* memory region 5 configuration */
35  unsigned int mcon6;             /* memory region 6 configuration */
36  unsigned int mcon7;             /* memory region 7 configuration */
37                            /* Control Group 4 */
38  unsigned int mcon8;             /* memory region 8 configuration */
39  unsigned int mcon9;             /* memory region 9 configuration */
40  unsigned int mcon10;            /* memory region 10 configuration */
41  unsigned int mcon11;            /* memory region 11 configuration */
42                            /* Control Group 5 */
43  unsigned int mcon12;            /* memory region 12 configuration */
44  unsigned int mcon13;            /* memory region 13 configuration */
45  unsigned int mcon14;            /* memory region 14 configuration */
46  unsigned int mcon15;            /* memory region 15 configuration */
47                            /* Control Group 6 */
48  unsigned int reserved;          /* reserved */
49  unsigned int bpcon;             /* breakpoint control */
50  unsigned int tc;                /* trace control */
51  unsigned int bcon;              /* bus configuration control */
52}   i960ha_control_table;
53
54/* Intel i960HA Processor Control Block */
55
56typedef struct {
57  unsigned int    *fault_tbl;     /* fault table base address */
58  i960ha_control_table
59                  *control_tbl;   /* control table base address */
60  unsigned int     initial_ac;    /* AC register initial value */
61  unsigned int     fault_config;  /* fault configuration word */
62  void           **intr_tbl;      /* interrupt table base address */
63  void            *sys_proc_tbl;  /* system procedure table
64                                     base address */
65  unsigned int     reserved;      /* reserved */
66  unsigned int    *intr_stack;    /* interrupt stack pointer */
67  unsigned int     ins_cache_cfg; /* instruction cache
68                                     configuration word */
69  unsigned int     reg_cache_cfg; /* register cache configuration word */
70}   i960ha_PRCB;
71
72typedef i960ha_control_table i960_control_table;
73typedef i960ha_PRCB i960_PRCB;
74
75#define I960_SOFT_RESET_COMMAND 0x30000
76
77#define i960_soft_reset( prcb ) \
78 { register i960_PRCB    *_prcb = (prcb); \
79   register unsigned int *_next=0; \
80   register unsigned int  _cmd  = I960_SOFT_RESET_COMMAND; \
81   asm volatile( "lda    next,%1; \
82                  sysctl %0,%1,%2; \
83            next: mov    g0,g0" \
84                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
85                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
86 }
87
88
89
90#endif
91/* end of include file */
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