source: rtems/c/src/lib/libcpu/i960/include/i960CA.h @ 911158a

4.104.114.84.95
Last change on this file since 911158a was 911158a, checked in by Joel Sherrill <joel.sherrill@…>, on 05/09/02 at 21:43:28

2001-05-09 Joel Sherrill <joel@…>

  • include/i960CA.h, include/i960RP.h: Correct inline assembly forward reference labels.
  • Property mode set to 100644
File size: 4.5 KB
Line 
1/*
2 *  i960ca
3 *
4 *  $Id$
5 */
6
7#ifndef __i960CA_h
8#define __i960CA_h
9
10
11/* i960CA control structures */
12 
13/* Intel i960CA Control Table */
14 
15typedef struct {
16                            /* Control Group 0 */
17  unsigned int ipb0;              /* IP breakpoint 0 */
18  unsigned int ipb1;              /* IP breakpoint 1 */
19  unsigned int dab0;              /* data address breakpoint 0 */
20  unsigned int dab1;              /* data address breakpoint 1 */
21                            /* Control Group 1 */
22  unsigned int imap0;             /* interrupt map 0 */
23  unsigned int imap1;             /* interrupt map 1 */
24  unsigned int imap2;             /* interrupt map 2 */
25  unsigned int icon;              /* interrupt control */
26                            /* Control Group 2 */
27  unsigned int mcon0;             /* memory region 0 configuration */
28  unsigned int mcon1;             /* memory region 1 configuration */
29  unsigned int mcon2;             /* memory region 2 configuration */
30  unsigned int mcon3;             /* memory region 3 configuration */
31                            /* Control Group 3 */
32  unsigned int mcon4;             /* memory region 4 configuration */
33  unsigned int mcon5;             /* memory region 5 configuration */
34  unsigned int mcon6;             /* memory region 6 configuration */
35  unsigned int mcon7;             /* memory region 7 configuration */
36                            /* Control Group 4 */
37  unsigned int mcon8;             /* memory region 8 configuration */
38  unsigned int mcon9;             /* memory region 9 configuration */
39  unsigned int mcon10;            /* memory region 10 configuration */
40  unsigned int mcon11;            /* memory region 11 configuration */
41                            /* Control Group 5 */
42  unsigned int mcon12;            /* memory region 12 configuration */
43  unsigned int mcon13;            /* memory region 13 configuration */
44  unsigned int mcon14;            /* memory region 14 configuration */
45  unsigned int mcon15;            /* memory region 15 configuration */
46                            /* Control Group 6 */
47  unsigned int reserved;          /* reserved */
48  unsigned int bpcon;             /* breakpoint control */
49  unsigned int tc;                /* trace control */
50  unsigned int bcon;              /* bus configuration control */
51}   i960ca_control_table;
52 
53/* Intel i960CA Processor Control Block */
54 
55typedef struct {
56  unsigned int    *fault_tbl;     /* fault table base address */
57  i960ca_control_table
58                  *control_tbl;   /* control table base address */
59  unsigned int     initial_ac;    /* AC register initial value */
60  unsigned int     fault_config;  /* fault configuration word */
61  void           **intr_tbl;      /* interrupt table base address */
62  void            *sys_proc_tbl;  /* system procedure table
63                                     base address */
64  unsigned int     reserved;      /* reserved */
65  unsigned int    *intr_stack;    /* interrupt stack pointer */
66  unsigned int     ins_cache_cfg; /* instruction cache
67                                     configuration word */
68  unsigned int     reg_cache_cfg; /* register cache configuration word */
69}   i960ca_PRCB;
70
71typedef i960ca_control_table i960_control_table;
72typedef i960ca_PRCB i960_PRCB;
73
74#define i960_unmask_intr( xint ) \
75 { register unsigned int _mask= (1<<(xint)); \
76   asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \
77 }
78
79#define i960_mask_intr( xint ) \
80 { register unsigned int _mask= (1<<(xint)); \
81   asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \
82 }
83
84#define i960_clear_intr( xint ) \
85 { register unsigned int _xint=(xint); \
86asm volatile( "99: clrbit %0,sf0,sf0 ; \
87                  bbs    %0,sf0, 99b" \
88                  : "=d" (_xint) : "0" (_xint) ); \
89 }
90
91static inline unsigned int i960_pend_intrs()
92{ register unsigned int _intr=0;
93  asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) );
94  return ( _intr );
95}
96
97static inline unsigned int i960_mask_intrs()
98{ register unsigned int _intr=0;
99  asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );
100  return( _intr );
101}
102
103#define I960_SOFT_RESET_COMMAND 0x30000
104
105#define i960_soft_reset( prcb ) \
106 { register i960_PRCB    *_prcb = (prcb); \
107   register unsigned int *_next=0; \
108   register unsigned int  _cmd  = I960_SOFT_RESET_COMMAND; \
109   asm volatile( "lda    next,%1; \
110                  sysctl %0,%1,%2; \
111            next: mov    g0,g0" \
112                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
113                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
114 }
115
116
117
118#endif
119/* end of include file */
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