[bc85fd5a] | 1 | /* |
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| 2 | * i960ca |
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| 3 | * |
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| 4 | * $Id$ |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef __i960CA_h |
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| 8 | #define __i960CA_h |
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| 9 | |
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| 10 | |
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| 11 | /* i960CA control structures */ |
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| 12 | |
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| 13 | /* Intel i960CA Control Table */ |
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| 14 | |
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| 15 | typedef struct { |
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| 16 | /* Control Group 0 */ |
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| 17 | unsigned int ipb0; /* IP breakpoint 0 */ |
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| 18 | unsigned int ipb1; /* IP breakpoint 1 */ |
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| 19 | unsigned int dab0; /* data address breakpoint 0 */ |
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| 20 | unsigned int dab1; /* data address breakpoint 1 */ |
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| 21 | /* Control Group 1 */ |
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| 22 | unsigned int imap0; /* interrupt map 0 */ |
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| 23 | unsigned int imap1; /* interrupt map 1 */ |
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| 24 | unsigned int imap2; /* interrupt map 2 */ |
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| 25 | unsigned int icon; /* interrupt control */ |
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| 26 | /* Control Group 2 */ |
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| 27 | unsigned int mcon0; /* memory region 0 configuration */ |
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| 28 | unsigned int mcon1; /* memory region 1 configuration */ |
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| 29 | unsigned int mcon2; /* memory region 2 configuration */ |
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| 30 | unsigned int mcon3; /* memory region 3 configuration */ |
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| 31 | /* Control Group 3 */ |
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| 32 | unsigned int mcon4; /* memory region 4 configuration */ |
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| 33 | unsigned int mcon5; /* memory region 5 configuration */ |
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| 34 | unsigned int mcon6; /* memory region 6 configuration */ |
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| 35 | unsigned int mcon7; /* memory region 7 configuration */ |
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| 36 | /* Control Group 4 */ |
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| 37 | unsigned int mcon8; /* memory region 8 configuration */ |
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| 38 | unsigned int mcon9; /* memory region 9 configuration */ |
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| 39 | unsigned int mcon10; /* memory region 10 configuration */ |
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| 40 | unsigned int mcon11; /* memory region 11 configuration */ |
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| 41 | /* Control Group 5 */ |
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| 42 | unsigned int mcon12; /* memory region 12 configuration */ |
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| 43 | unsigned int mcon13; /* memory region 13 configuration */ |
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| 44 | unsigned int mcon14; /* memory region 14 configuration */ |
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| 45 | unsigned int mcon15; /* memory region 15 configuration */ |
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| 46 | /* Control Group 6 */ |
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| 47 | unsigned int reserved; /* reserved */ |
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| 48 | unsigned int bpcon; /* breakpoint control */ |
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| 49 | unsigned int tc; /* trace control */ |
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| 50 | unsigned int bcon; /* bus configuration control */ |
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| 51 | } i960ca_control_table; |
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| 52 | |
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| 53 | /* Intel i960CA Processor Control Block */ |
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| 54 | |
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| 55 | typedef struct { |
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| 56 | unsigned int *fault_tbl; /* fault table base address */ |
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| 57 | i960ca_control_table |
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| 58 | *control_tbl; /* control table base address */ |
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| 59 | unsigned int initial_ac; /* AC register initial value */ |
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| 60 | unsigned int fault_config; /* fault configuration word */ |
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| 61 | void **intr_tbl; /* interrupt table base address */ |
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| 62 | void *sys_proc_tbl; /* system procedure table |
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| 63 | base address */ |
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| 64 | unsigned int reserved; /* reserved */ |
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| 65 | unsigned int *intr_stack; /* interrupt stack pointer */ |
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| 66 | unsigned int ins_cache_cfg; /* instruction cache |
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| 67 | configuration word */ |
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| 68 | unsigned int reg_cache_cfg; /* register cache configuration word */ |
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| 69 | } i960ca_PRCB; |
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| 70 | |
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| 71 | typedef i960ca_control_table i960_control_table; |
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| 72 | typedef i960ca_PRCB i960_PRCB; |
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| 73 | |
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| 74 | #define i960_unmask_intr( xint ) \ |
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| 75 | { register unsigned int _mask= (1<<(xint)); \ |
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| 76 | asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \ |
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| 77 | } |
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| 78 | |
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| 79 | #define i960_mask_intr( xint ) \ |
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| 80 | { register unsigned int _mask= (1<<(xint)); \ |
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| 81 | asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \ |
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| 82 | } |
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| 83 | |
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| 84 | #define i960_clear_intr( xint ) \ |
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| 85 | { register unsigned int _xint=(xint); \ |
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| 86 | asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \ |
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| 87 | bbs %0,sf0, loop_til_cleared" \ |
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| 88 | : "=d" (_xint) : "0" (_xint) ); \ |
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| 89 | } |
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| 90 | |
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| 91 | static inline unsigned int i960_pend_intrs() |
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| 92 | { register unsigned int _intr=0; |
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| 93 | asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) ); |
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| 94 | return ( _intr ); |
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| 95 | } |
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| 96 | |
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| 97 | static inline unsigned int i960_mask_intrs() |
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| 98 | { register unsigned int _intr=0; |
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| 99 | asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) ); |
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| 100 | return( _intr ); |
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| 101 | } |
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| 102 | |
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| 103 | #define I960_SOFT_RESET_COMMAND 0x30000 |
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| 104 | |
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| 105 | #define i960_soft_reset( prcb ) \ |
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| 106 | { register i960_PRCB *_prcb = (prcb); \ |
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| 107 | register unsigned int *_next=0; \ |
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| 108 | register unsigned int _cmd = I960_SOFT_RESET_COMMAND; \ |
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| 109 | asm volatile( "lda next,%1; \ |
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| 110 | sysctl %0,%1,%2; \ |
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| 111 | next: mov g0,g0" \ |
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| 112 | : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ |
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| 113 | : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ |
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| 114 | } |
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| 115 | |
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| 116 | |
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| 117 | |
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| 118 | #endif |
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| 119 | /* end of include file */ |
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