4.104.114.84.95
Last change
on this file since bc85fd5a was
bc85fd5a,
checked in by Joel Sherrill <joel.sherrill@…>, on 07/11/00 at 19:31:04
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Reworked score/cpu/i960 so it can be safely compiled multilib. All
routines and structures that require CPU model specific information
are now in libcpu. This required significant rework of the
score/cpu header files and the creation of multiple header files
and subdirectories in libcpu/i960.
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-
Property mode set to
100644
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File size:
946 bytes
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Rev | Line | |
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[bc85fd5a] | 1 | /* |
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| 2 | * Install raw interrupt vector for i960ka |
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| 3 | * |
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| 4 | * $Id$ |
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| 5 | */ |
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| 6 | |
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| 7 | #include <rtems.h> |
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| 8 | #include <libcpu/i960KA.h> |
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| 9 | |
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| 10 | /* this is from the CA and probably not right */ |
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| 11 | #define i960_vector_caching_enabled( _prcb ) \ |
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| 12 | ((_prcb)->control_tbl->icon & 0x2000) |
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| 13 | |
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| 14 | extern i960_PRCB *Prcb; |
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| 15 | |
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| 16 | void _CPU_ISR_install_raw_handler( |
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| 17 | unsigned32 vector, |
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| 18 | proc_ptr new_handler, |
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| 19 | proc_ptr *old_handler |
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| 20 | ) |
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| 21 | { |
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| 22 | i960_PRCB *prcb = Prcb; |
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| 23 | proc_ptr *cached_intr_tbl = NULL; |
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| 24 | |
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| 25 | /* The i80960CA does not support vectors 0-7. The first 9 entries |
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| 26 | * in the Interrupt Table are used to manage pending interrupts. |
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| 27 | * Thus vector 8, the first valid vector number, is actually in |
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| 28 | * slot 9 in the table. |
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| 29 | */ |
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| 30 | |
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| 31 | *old_handler = prcb->intr_tbl[ vector + 1 ]; |
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| 32 | |
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| 33 | prcb->intr_tbl[ vector + 1 ] = new_handler; |
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| 34 | |
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| 35 | if ( i960_vector_caching_enabled( prcb ) ) |
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| 36 | if ( (vector & 0xf) == 0x2 ) /* cacheable? */ |
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| 37 | cached_intr_tbl[ vector >> 4 ] = new_handler; |
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| 38 | } |
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| 39 | |
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