source: rtems/c/src/lib/libcpu/i960/i960ca/cpu_install_raw_isr.c @ 073e2411

4.104.114.84.95
Last change on this file since 073e2411 was bc85fd5a, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 11, 2000 at 7:31:04 PM

Reworked score/cpu/i960 so it can be safely compiled multilib. All
routines and structures that require CPU model specific information
are now in libcpu. This required significant rework of the
score/cpu header files and the creation of multiple header files
and subdirectories in libcpu/i960.

  • Property mode set to 100644
File size: 897 bytes
Line 
1/*
2 *  Install raw interrupt vector for i960ca
3 *
4 *  $Id$
5 */
6
7#include <rtems.h>
8#include <libcpu/i960CA.h>
9
10#define i960_vector_caching_enabled( _prcb ) \
11   ((_prcb)->control_tbl->icon & 0x2000)
12
13extern i960_PRCB *Prcb;
14
15void _CPU_ISR_install_raw_handler(
16  unsigned32  vector,
17  proc_ptr    new_handler,
18  proc_ptr   *old_handler
19)
20{
21  i960_PRCB   *prcb = Prcb;
22  proc_ptr    *cached_intr_tbl = NULL;
23
24  /*  The i80960CA does not support vectors 0-7.  The first 9 entries
25   *  in the Interrupt Table are used to manage pending interrupts.
26   *  Thus vector 8, the first valid vector number, is actually in
27   *  slot 9 in the table.
28   */
29
30  *old_handler = prcb->intr_tbl[ vector + 1 ];
31
32  prcb->intr_tbl[ vector + 1 ] = new_handler;
33
34  if ( i960_vector_caching_enabled( prcb ) )
35    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
36      cached_intr_tbl[ vector >> 4 ] = new_handler;
37}
38
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