[ab0df696] | 1 | /* registers.h |
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| 2 | * |
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| 3 | * This file contains definition and constants related to Intel Cpu |
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| 4 | * |
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| 5 | * COPYRIGHT (c) 1998 valette@crf.canon.fr |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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| 9 | * http://www.OARcorp.com/rtems/license.html. |
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| 10 | * |
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| 11 | * $Id$ |
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| 12 | */ |
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| 13 | |
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| 14 | #ifndef _LIBCPU_i386_REGISTERS_H |
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| 15 | #define _LIBCPU_i386_REGISTERS_H |
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| 16 | |
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| 17 | /* |
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| 18 | * definition related to EFLAGS |
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| 19 | */ |
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| 20 | #define EFLAGS_CARRY 0x1 |
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| 21 | #define EFLAGS_PARITY 0x4 |
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| 22 | |
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| 23 | #define EFLAGS_AUX_CARRY 0x10 |
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| 24 | #define EFLAGS_ZERO 0x40 |
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| 25 | #define EFLAGS_SIGN 0x80 |
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| 26 | |
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| 27 | #define EFLAGS_TRAP 0x100 |
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| 28 | #define EFLAGS_INTR_ENABLE 0x200 |
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| 29 | #define EFLAGS_DIRECTION 0x400 |
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| 30 | #define EFLAGS_OVERFLOW 0x800 |
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| 31 | |
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| 32 | #define EFLAGS_IOPL_MASK 0x3000 |
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| 33 | #define EFLAGS_NESTED_TASK 0x8000 |
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| 34 | |
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| 35 | #define EFLAGS_RESUME 0x10000 |
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| 36 | #define EFLAGS_VIRTUAL_MODE 0x20000 |
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| 37 | #define EFLAGS_ALIGN_CHECK 0x40000 |
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| 38 | #define EFLAGS_VIRTUAL_INTR 0x80000 |
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| 39 | |
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| 40 | #define EFLAGS_VIRTUAL_INTR_PEND 0x100000 |
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| 41 | #define EFLAGS_ID 0x200000 |
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| 42 | |
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| 43 | /* |
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| 44 | * definitions related to CR0 |
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| 45 | */ |
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| 46 | #define CR0_PROTECTION_ENABLE 0x1 |
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| 47 | #define CR0_MONITOR_COPROC 0x2 |
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| 48 | #define CR0_COPROC_SOFT_EMUL 0x4 |
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| 49 | #define CR0_FLOATING_INSTR_EXCEPTION 0x8 |
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| 50 | |
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| 51 | #define CR0_EXTENSION_TYPE 0x10 |
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| 52 | #define CR0_NUMERIC_ERROR 0x20 |
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| 53 | |
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| 54 | #define CR0_WRITE_PROTECT 0x10000 |
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| 55 | #define CR0_ALIGMENT_MASK 0x40000 |
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| 56 | |
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| 57 | #define CR0_NO_WRITE_THROUGH 0x20000000 |
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| 58 | #define CR0_PAGE_LEVEL_CACHE_DISABLE 0x40000000 |
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| 59 | #define CR0_PAGING 0x80000000 |
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| 60 | |
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[e029467] | 61 | /* |
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| 62 | * definitions related to CR3 |
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| 63 | */ |
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| 64 | |
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| 65 | #define CR3_PAGE_CACHE_DISABLE 0x10 |
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| 66 | #define CR3_PAGE_WRITE_THROUGH 0x8 |
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| 67 | |
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| 68 | |
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[ab0df696] | 69 | #ifndef ASM |
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| 70 | |
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| 71 | /* |
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| 72 | * definition of eflags registers has a bit field structure |
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| 73 | */ |
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| 74 | typedef struct { |
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| 75 | /* |
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| 76 | * fist byte : bits 0->7 |
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| 77 | */ |
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| 78 | unsigned int carry : 1; |
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| 79 | unsigned int : 1; |
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| 80 | unsigned int parity : 1; |
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| 81 | unsigned int : 1; |
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| 82 | |
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| 83 | unsigned int auxiliary_carry : 1; |
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| 84 | unsigned int : 1; |
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| 85 | unsigned int zero : 1; /* result is zero */ |
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| 86 | unsigned int sign : 1; /* result is less than zero */ |
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| 87 | /* |
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| 88 | * Second byte : bits 7->15 |
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| 89 | */ |
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| 90 | unsigned int trap : 1; |
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| 91 | unsigned int intr_enable : 1; /* set => intr on */ |
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| 92 | unsigned int direction : 1; /* set => autodecrement */ |
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| 93 | unsigned int overflow : 1; |
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| 94 | |
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| 95 | unsigned int IO_privilege : 2; |
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| 96 | unsigned int nested_task : 1; |
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| 97 | unsigned int : 1; |
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| 98 | /* |
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| 99 | * Third byte : bits 15->23 |
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| 100 | */ |
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| 101 | unsigned int resume : 1; |
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| 102 | unsigned int virtual_mode : 1; |
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| 103 | unsigned int aligment_check : 1; |
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| 104 | unsigned int virtual_intr : 1; |
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| 105 | |
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| 106 | unsigned int virtual_intr_pending : 1; |
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| 107 | unsigned int id : 1; |
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| 108 | unsigned int : 2; |
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| 109 | |
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| 110 | /* |
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| 111 | * fourth byte : bits 24->31 : UNUSED |
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| 112 | */ |
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| 113 | unsigned int : 8; |
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| 114 | }eflags_bits; |
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| 115 | |
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| 116 | typedef union { |
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| 117 | eflags_bits eflags; |
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| 118 | unsigned int i; |
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| 119 | }eflags; |
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| 120 | /* |
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| 121 | * definition of eflags registers has a bit field structure |
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| 122 | */ |
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| 123 | typedef struct { |
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| 124 | /* |
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| 125 | * fist byte : bits 0->7 |
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| 126 | */ |
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| 127 | unsigned int protection_enable : 1; |
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| 128 | unsigned int monitor_coproc : 1; |
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| 129 | unsigned int coproc_soft_emul : 1; |
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| 130 | unsigned int floating_instr_except : 1; |
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| 131 | |
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| 132 | unsigned int extension_type : 1; |
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| 133 | unsigned int numeric_error : 1; |
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| 134 | unsigned int : 2; |
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| 135 | /* |
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| 136 | * second byte 8->15 : UNUSED |
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| 137 | */ |
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| 138 | unsigned int : 8; |
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| 139 | /* |
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| 140 | * third byte 16->23 |
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| 141 | */ |
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| 142 | unsigned int write_protect : 1; |
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| 143 | unsigned int : 1; |
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| 144 | unsigned int aligment_mask : 1; |
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| 145 | unsigned int : 1; |
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| 146 | |
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| 147 | unsigned int : 4; |
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| 148 | /* |
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| 149 | * fourth byte 24->31 |
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| 150 | */ |
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| 151 | unsigned int : 4; |
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| 152 | |
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| 153 | unsigned int : 1; |
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| 154 | unsigned int no_write_through : 1; |
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| 155 | unsigned int page_level_cache_disable : 1; |
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| 156 | unsigned int paging : 1; |
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| 157 | }cr0_bits; |
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| 158 | |
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| 159 | typedef union { |
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| 160 | cr0_bits cr0; |
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| 161 | unsigned int i; |
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| 162 | }cr0; |
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| 163 | |
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[e029467] | 164 | /* |
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| 165 | * definition of cr3 registers has a bit field structure |
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| 166 | */ |
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| 167 | typedef struct { |
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| 168 | |
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| 169 | unsigned int : 3; |
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| 170 | unsigned int page_write_transparent : 1; |
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| 171 | unsigned int page_cache_disable : 1; |
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| 172 | unsigned int : 7; |
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| 173 | unsigned int page_directory_base :20; |
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| 174 | }cr3_bits; |
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| 175 | |
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| 176 | typedef union { |
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| 177 | cr3_bits cr3; |
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| 178 | unsigned int i; |
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| 179 | }cr3; |
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| 180 | |
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[ab0df696] | 181 | #endif |
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| 182 | |
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| 183 | #endif |
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| 184 | |
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