[adbaa61] | 1 | * Instanciate paging. More detailled information |
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| 2 | * can be found on Intel site and more precisely in |
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| 3 | * the following book : |
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| 4 | * |
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| 5 | * Pentium Processor familly |
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| 6 | * Developper's Manual |
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| 7 | * |
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| 8 | * Volume 3 : Architecture and Programming Manual |
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| 9 | * |
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| 10 | * Copyright (C) 1999 Emmanuel Raguet (raguet@crf.canon.fr) |
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| 11 | * Canon Centre Recherche France. |
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| 12 | * |
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| 13 | * The license and distribution terms for this file may be |
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| 14 | * found in found in the file LICENSE in this distribution or at |
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| 15 | * http://www.OARcorp.com/rtems/license.html. |
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| 16 | * |
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| 17 | * $Header$ |
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| 18 | */ |
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| 19 | |
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| 20 | #include <stdio.h> |
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| 21 | #include <stdlib.h> |
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| 22 | #include <string.h> |
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| 23 | #include <rtems.h> |
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| 24 | #include <libcpu/cpu.h> |
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| 25 | |
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| 26 | #define MEMORY_SIZE 0x4000000 /* 64Mo */ |
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| 27 | |
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| 28 | static int directoryEntry=0; |
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| 29 | static int tableEntry=0; |
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| 30 | static page_directory *pageDirectory; |
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| 31 | |
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| 32 | extern rtems_unsigned32 rtemsFreeMemStart; |
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| 33 | |
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| 34 | |
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| 35 | /*************************************************************************/ |
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| 36 | /************** IT IS A ONE-TO-ONE TRANSLATION ***************************/ |
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| 37 | /*************************************************************************/ |
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| 38 | |
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| 39 | |
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| 40 | /* |
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| 41 | * Disable the paging |
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| 42 | */ |
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| 43 | void _CPU_disable_paging() { |
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| 44 | cr0 regCr0; |
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| 45 | |
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[5e77d129] | 46 | rtems_cache_flush_entire_data(); |
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[adbaa61] | 47 | regCr0.i = i386_get_cr0(); |
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| 48 | regCr0.cr0.paging = 0; |
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| 49 | i386_set_cr0( regCr0.i ); |
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| 50 | } |
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| 51 | |
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| 52 | /* |
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| 53 | * Enable the paging |
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| 54 | */ |
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| 55 | void _CPU_enable_paging() { |
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| 56 | cr0 regCr0; |
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| 57 | |
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| 58 | regCr0.i = i386_get_cr0(); |
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| 59 | regCr0.cr0.paging = 1; |
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| 60 | i386_set_cr0( regCr0.i ); |
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[5e77d129] | 61 | rtems_cache_flush_entire_data(); |
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[adbaa61] | 62 | } |
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| 63 | |
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| 64 | |
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| 65 | /* |
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| 66 | * Initialize the paging with 1-to-1 mapping |
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| 67 | */ |
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| 68 | |
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| 69 | int init_paging() { |
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| 70 | |
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| 71 | int memorySize; |
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| 72 | int nbPages; |
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| 73 | int nbInitPages; |
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| 74 | char *Tables; |
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| 75 | cr3 regCr3; |
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| 76 | page_table *pageTable; |
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| 77 | unsigned int physPage; |
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| 78 | int nbTables=0; |
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| 79 | |
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| 80 | /* |
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| 81 | * rtemsFreeMemStart is the last valid 32-bits address |
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| 82 | * so the size is rtemsFreeMemStart + 4 |
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| 83 | */ |
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| 84 | memorySize = rtemsFreeMemStart + 4; |
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| 85 | |
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| 86 | nbPages = ( (memorySize - 1) / PG_SIZE ) + 1; |
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| 87 | nbTables = ( (memorySize - 1) / FOUR_MB ) + 2; |
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| 88 | |
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| 89 | /* allocate 1 page more to page alignement */ |
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| 90 | Tables = (char *)malloc( (nbTables + 1)*sizeof(page_table) ); |
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| 91 | if ( Tables == NULL ){ |
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| 92 | return -1; /*unable to allocate memory */ |
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| 93 | } |
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| 94 | |
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| 95 | /* 4K-page alignement */ |
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| 96 | Tables += (PG_SIZE - (int)Tables) & 0xFFF; |
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| 97 | |
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| 98 | /* Reset Tables */ |
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[c629812] | 99 | memset( Tables, 0, nbTables*sizeof(page_table) ); |
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[adbaa61] | 100 | pageDirectory = (page_directory *) Tables; |
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| 101 | pageTable = (page_table *)((int)Tables + PG_SIZE); |
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| 102 | |
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| 103 | nbInitPages = 0; |
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| 104 | directoryEntry = 0; |
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| 105 | tableEntry = 0; |
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| 106 | physPage = 0; |
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| 107 | |
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| 108 | while ( nbInitPages != nbPages ){ |
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| 109 | if ( tableEntry == 0 ){ |
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| 110 | pageDirectory->pageDirEntry[directoryEntry].bits.page_frame_address = (unsigned int)pageTable >> 12; |
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| 111 | pageDirectory->pageDirEntry[directoryEntry].bits.available = 0; |
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| 112 | pageDirectory->pageDirEntry[directoryEntry].bits.page_size = 0; |
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| 113 | pageDirectory->pageDirEntry[directoryEntry].bits.accessed = 0; |
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| 114 | pageDirectory->pageDirEntry[directoryEntry].bits.cache_disable = 0; |
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| 115 | pageDirectory->pageDirEntry[directoryEntry].bits.write_through = 0; |
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| 116 | pageDirectory->pageDirEntry[directoryEntry].bits.user = 1; |
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| 117 | pageDirectory->pageDirEntry[directoryEntry].bits.writable = 1; |
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| 118 | pageDirectory->pageDirEntry[directoryEntry].bits.present = 1; |
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| 119 | } |
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| 120 | pageTable->pageTableEntry[tableEntry].bits.page_frame_address = physPage; |
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| 121 | pageTable->pageTableEntry[tableEntry].bits.available = 0; |
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| 122 | pageTable->pageTableEntry[tableEntry].bits.dirty = 0; |
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| 123 | pageTable->pageTableEntry[tableEntry].bits.accessed = 0; |
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| 124 | pageTable->pageTableEntry[tableEntry].bits.cache_disable = 0; |
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| 125 | pageTable->pageTableEntry[tableEntry].bits.write_through = 0; |
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| 126 | pageTable->pageTableEntry[tableEntry].bits.user = 1; |
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| 127 | pageTable->pageTableEntry[tableEntry].bits.writable = 1; |
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| 128 | pageTable->pageTableEntry[tableEntry].bits.present = 1; |
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| 129 | |
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| 130 | physPage ++; |
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| 131 | tableEntry ++; |
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| 132 | |
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| 133 | if (tableEntry >= MAX_ENTRY){ |
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| 134 | tableEntry = 0; |
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| 135 | directoryEntry ++; |
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| 136 | pageTable ++; |
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| 137 | } |
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| 138 | |
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| 139 | nbInitPages++; |
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| 140 | } |
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| 141 | |
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| 142 | regCr3.cr3.page_write_transparent = 0; |
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| 143 | regCr3.cr3.page_cache_disable = 0; |
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| 144 | regCr3.cr3.page_directory_base = (unsigned int)pageDirectory >> 12; |
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| 145 | |
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| 146 | i386_set_cr3( regCr3.i ); |
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| 147 | |
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| 148 | _CPU_enable_cache(); |
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| 149 | _CPU_enable_paging(); |
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| 150 | |
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| 151 | return 0; |
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| 152 | } |
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| 153 | |
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| 154 | /* |
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| 155 | * Is cache enable |
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| 156 | */ |
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| 157 | int _CPU_is_cache_enabled() { |
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| 158 | cr0 regCr0; |
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| 159 | |
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| 160 | regCr0.i = i386_get_cr0(); |
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| 161 | return( ~(regCr0.cr0.page_level_cache_disable) ); |
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| 162 | } |
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| 163 | |
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| 164 | /* |
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| 165 | * Is paging enable |
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| 166 | */ |
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| 167 | int _CPU_is_paging_enabled() { |
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| 168 | cr0 regCr0; |
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| 169 | |
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| 170 | regCr0.i = i386_get_cr0(); |
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| 171 | return(regCr0.cr0.paging); |
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| 172 | } |
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| 173 | |
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| 174 | |
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| 175 | /* |
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| 176 | * Translate the physical address in the virtual space and return |
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| 177 | * the translated address in mappedAddress |
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| 178 | */ |
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| 179 | |
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| 180 | int _CPU_map_phys_address |
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| 181 | (void **mappedAddress, void *physAddress, int size, int flag){ |
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| 182 | |
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| 183 | page_table *localPageTable; |
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| 184 | unsigned int lastAddress, countAddress; |
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| 185 | char *Tables; |
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| 186 | linear_address virtualAddress; |
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| 187 | unsigned char pagingWasEnabled; |
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| 188 | |
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| 189 | pagingWasEnabled = 0; |
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| 190 | |
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| 191 | if (_CPU_is_paging_enabled()){ |
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| 192 | pagingWasEnabled = 1; |
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| 193 | _CPU_disable_paging(); |
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| 194 | } |
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| 195 | |
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| 196 | countAddress = (unsigned int)physAddress; |
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| 197 | lastAddress = (unsigned int)physAddress + (size - 1); |
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| 198 | virtualAddress.address = 0; |
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| 199 | |
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| 200 | while (1){ |
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| 201 | |
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| 202 | if ((countAddress & ~MASK_OFFSET) > (lastAddress & ~MASK_OFFSET)) |
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| 203 | break; |
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| 204 | |
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| 205 | /* Need to allocate a new page table */ |
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| 206 | if (pageDirectory->pageDirEntry[directoryEntry].bits.page_frame_address == 0){ |
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| 207 | /* We allocate 2 pages to perform 4k-page alignement */ |
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| 208 | Tables = (char *)malloc(2*sizeof(page_table)); |
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| 209 | if ( Tables == NULL ){ |
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| 210 | if (pagingWasEnabled) |
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| 211 | _CPU_enable_paging(); |
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| 212 | return -1; /* unable to allocate memory */ |
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| 213 | } |
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| 214 | /* 4K-page alignement */ |
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| 215 | Tables += (PG_SIZE - (int)Tables) & 0xFFF; |
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| 216 | |
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| 217 | /* Reset Table */ |
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[c629812] | 218 | memset( Tables, 0, sizeof(page_table) ); |
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[adbaa61] | 219 | pageDirectory->pageDirEntry[directoryEntry].bits.page_frame_address = |
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| 220 | (unsigned int)Tables >> 12; |
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| 221 | pageDirectory->pageDirEntry[directoryEntry].bits.available = 0; |
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| 222 | pageDirectory->pageDirEntry[directoryEntry].bits.page_size = 0; |
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| 223 | pageDirectory->pageDirEntry[directoryEntry].bits.accessed = 0; |
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| 224 | pageDirectory->pageDirEntry[directoryEntry].bits.cache_disable = 0; |
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| 225 | pageDirectory->pageDirEntry[directoryEntry].bits.write_through = 0; |
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| 226 | pageDirectory->pageDirEntry[directoryEntry].bits.user = 1; |
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| 227 | pageDirectory->pageDirEntry[directoryEntry].bits.writable = 1; |
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| 228 | pageDirectory->pageDirEntry[directoryEntry].bits.present = 1; |
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| 229 | } |
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| 230 | |
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| 231 | |
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| 232 | localPageTable = (page_table *)(pageDirectory-> |
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| 233 | pageDirEntry[directoryEntry].bits. |
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| 234 | page_frame_address << 12); |
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| 235 | |
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| 236 | if (virtualAddress.address == 0){ |
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| 237 | virtualAddress.bits.directory = directoryEntry; |
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| 238 | virtualAddress.bits.page = tableEntry; |
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| 239 | virtualAddress.bits.offset = (unsigned int)physAddress & MASK_OFFSET; |
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| 240 | } |
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| 241 | |
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| 242 | localPageTable->pageTableEntry[tableEntry].bits.page_frame_address = |
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| 243 | ((unsigned int)countAddress & ~MASK_OFFSET) >> 12; |
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| 244 | localPageTable->pageTableEntry[tableEntry].bits.available = 0; |
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| 245 | localPageTable->pageTableEntry[tableEntry].bits.dirty = 0; |
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| 246 | localPageTable->pageTableEntry[tableEntry].bits.accessed = 0; |
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| 247 | localPageTable->pageTableEntry[tableEntry].bits.cache_disable = 0; |
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| 248 | localPageTable->pageTableEntry[tableEntry].bits.write_through = 0; |
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| 249 | localPageTable->pageTableEntry[tableEntry].bits.user = 1; |
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| 250 | localPageTable->pageTableEntry[tableEntry].bits.writable = 0; |
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| 251 | localPageTable->pageTableEntry[tableEntry].bits.present = 1; |
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| 252 | |
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| 253 | localPageTable->pageTableEntry[tableEntry].table_entry |= flag ; |
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| 254 | |
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| 255 | countAddress += PG_SIZE; |
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| 256 | tableEntry++; |
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| 257 | if (tableEntry >= MAX_ENTRY){ |
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| 258 | tableEntry = 0; |
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| 259 | directoryEntry++; |
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| 260 | } |
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| 261 | } |
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| 262 | |
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| 263 | if (mappedAddress != 0) |
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| 264 | *mappedAddress = (void *)(virtualAddress.address); |
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| 265 | if (pagingWasEnabled) |
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| 266 | _CPU_enable_paging(); |
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| 267 | return 0; |
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| 268 | } |
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| 269 | |
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| 270 | /* |
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| 271 | * "Compress" the Directory and Page tables to avoid |
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| 272 | * important loss of address range |
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| 273 | */ |
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| 274 | static void Paging_Table_Compress() { |
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| 275 | unsigned int dirCount, pageCount; |
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| 276 | page_table *localPageTable; |
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| 277 | |
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| 278 | if (tableEntry == 0){ |
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| 279 | dirCount = directoryEntry - 1; |
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| 280 | pageCount = MAX_ENTRY - 1; |
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| 281 | } |
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| 282 | else { |
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| 283 | dirCount = directoryEntry; |
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| 284 | pageCount = tableEntry - 1; |
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| 285 | } |
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| 286 | |
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| 287 | while (1){ |
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| 288 | |
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| 289 | localPageTable = (page_table *)(pageDirectory-> |
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| 290 | pageDirEntry[dirCount].bits. |
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| 291 | page_frame_address << 12); |
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| 292 | |
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| 293 | if (localPageTable->pageTableEntry[pageCount].bits.present == 1){ |
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| 294 | pageCount++; |
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| 295 | if (pageCount >= MAX_ENTRY){ |
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| 296 | pageCount = 0; |
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| 297 | dirCount++; |
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| 298 | } |
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| 299 | break; |
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| 300 | } |
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| 301 | |
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| 302 | |
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| 303 | if (pageCount == 0) { |
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| 304 | if (dirCount == 0){ |
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| 305 | break; |
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| 306 | } |
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| 307 | else { |
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| 308 | pageCount = MAX_ENTRY - 1; |
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| 309 | dirCount-- ; |
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| 310 | } |
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| 311 | } |
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| 312 | else |
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| 313 | pageCount-- ; |
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| 314 | } |
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| 315 | |
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| 316 | directoryEntry = dirCount; |
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| 317 | tableEntry = pageCount; |
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| 318 | } |
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| 319 | |
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| 320 | |
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| 321 | /* |
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| 322 | * Unmap the virtual address from the tables |
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| 323 | * (we do not deallocate the table already allocated) |
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| 324 | */ |
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| 325 | |
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| 326 | int _CPU_unmap_virt_address(void *mappedAddress, int size){ |
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| 327 | |
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| 328 | linear_address linearAddr; |
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| 329 | page_table *localPageTable; |
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| 330 | unsigned int lastAddr ; |
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| 331 | unsigned int dirCount ; |
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| 332 | unsigned char pagingWasEnabled; |
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| 333 | |
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| 334 | pagingWasEnabled = 0; |
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| 335 | |
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| 336 | if (_CPU_is_paging_enabled()){ |
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| 337 | pagingWasEnabled = 1; |
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| 338 | _CPU_disable_paging(); |
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| 339 | } |
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| 340 | |
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| 341 | linearAddr.address = (unsigned int)mappedAddress; |
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| 342 | lastAddr = (unsigned int)mappedAddress + (size - 1); |
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| 343 | dirCount = linearAddr.bits.directory; |
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| 344 | |
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| 345 | while (1){ |
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| 346 | |
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| 347 | if ((linearAddr.address & ~MASK_OFFSET) > (lastAddr & ~MASK_OFFSET)) |
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| 348 | break; |
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| 349 | |
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| 350 | if (pageDirectory->pageDirEntry[linearAddr.bits.directory].bits.present == 0){ |
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| 351 | if (pagingWasEnabled) |
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| 352 | _CPU_enable_paging(); |
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| 353 | return -1; |
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| 354 | } |
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| 355 | |
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| 356 | localPageTable = (page_table *)(pageDirectory-> |
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| 357 | pageDirEntry[linearAddr.bits.directory].bits. |
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| 358 | page_frame_address << 12); |
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| 359 | |
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| 360 | if (localPageTable->pageTableEntry[linearAddr.bits.page].bits.present == 0){ |
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| 361 | if (pagingWasEnabled) |
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| 362 | _CPU_enable_paging(); |
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| 363 | return -1; |
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| 364 | } |
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| 365 | |
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| 366 | localPageTable->pageTableEntry[linearAddr.bits.page].bits.present = 0; |
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| 367 | |
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| 368 | linearAddr.address += PG_SIZE ; |
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| 369 | } |
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| 370 | Paging_Table_Compress(); |
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| 371 | if (pagingWasEnabled) |
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| 372 | _CPU_enable_paging(); |
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| 373 | |
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| 374 | return 0; |
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| 375 | } |
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| 376 | |
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| 377 | /* |
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| 378 | * Modify the flags PRESENT, WRITABLE, USER, WRITE_TROUGH, CACHE_DISABLE |
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| 379 | * of the page's descriptor. |
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| 380 | */ |
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| 381 | |
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| 382 | int _CPU_change_memory_mapping_attribute |
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| 383 | (void **newAddress, void *mappedAddress, unsigned int size, unsigned int flag){ |
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| 384 | |
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| 385 | linear_address linearAddr; |
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| 386 | page_table *localPageTable; |
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| 387 | unsigned int lastAddr ; |
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| 388 | unsigned char pagingWasEnabled; |
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| 389 | |
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| 390 | pagingWasEnabled = 0; |
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| 391 | |
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| 392 | if (_CPU_is_paging_enabled()){ |
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| 393 | pagingWasEnabled = 1; |
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| 394 | _CPU_disable_paging(); |
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| 395 | } |
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| 396 | |
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| 397 | linearAddr.address = (unsigned int)mappedAddress; |
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| 398 | lastAddr = (unsigned int)mappedAddress + (size - 1); |
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| 399 | |
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| 400 | while (1){ |
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| 401 | |
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| 402 | if ((linearAddr.address & ~MASK_OFFSET) > (lastAddr & ~MASK_OFFSET)) |
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| 403 | break; |
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| 404 | |
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| 405 | if (pageDirectory->pageDirEntry[linearAddr.bits.directory].bits.present == 0){ |
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| 406 | if (pagingWasEnabled) |
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| 407 | _CPU_enable_paging(); |
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| 408 | return -1; |
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| 409 | } |
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| 410 | localPageTable = (page_table *)(pageDirectory-> |
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| 411 | pageDirEntry[linearAddr.bits.directory].bits. |
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| 412 | page_frame_address << 12); |
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| 413 | |
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| 414 | if (localPageTable->pageTableEntry[linearAddr.bits.page].bits.present == 0){ |
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| 415 | if (pagingWasEnabled) |
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| 416 | _CPU_enable_paging(); |
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| 417 | return -1; |
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| 418 | } |
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| 419 | |
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| 420 | localPageTable->pageTableEntry[linearAddr.bits.page].table_entry &= ~MASK_FLAGS ; |
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| 421 | localPageTable->pageTableEntry[linearAddr.bits.page].table_entry |= flag ; |
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| 422 | |
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| 423 | linearAddr.address += PG_SIZE ; |
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| 424 | } |
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| 425 | |
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| 426 | if (newAddress != NULL) |
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| 427 | *newAddress = mappedAddress ; |
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| 428 | |
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| 429 | if (pagingWasEnabled) |
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| 430 | _CPU_enable_paging(); |
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| 431 | |
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| 432 | return 0; |
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| 433 | } |
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| 434 | |
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| 435 | /* |
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| 436 | * Display the page descriptor flags |
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| 437 | * CACHE_DISABLE of the whole memory |
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| 438 | */ |
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| 439 | |
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[f43d7f7] | 440 | #include <bspIo.h> |
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[3dd7a72] | 441 | |
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[adbaa61] | 442 | int _CPU_display_memory_attribute(){ |
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| 443 | unsigned int dirCount, pageCount; |
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| 444 | cr0 regCr0; |
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| 445 | page_table *localPageTable; |
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| 446 | unsigned int prevCache; |
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| 447 | unsigned int prevPresent; |
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| 448 | unsigned int maxPage; |
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| 449 | unsigned char pagingWasEnabled; |
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| 450 | |
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| 451 | regCr0.i = i386_get_cr0(); |
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| 452 | |
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| 453 | printk("\n\n >>>>>>>>> MEMORY CACHE CONFIGURATION <<<<<<<<<<\n\n"); |
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| 454 | |
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| 455 | printk("CR0 -> paging : %s\n",(regCr0.cr0.paging ? "ENABLE ":"DISABLE")); |
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| 456 | printk(" page-level cache : %s\n\n",(regCr0.cr0.page_level_cache_disable ? "DISABLE":"ENABLE")); |
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| 457 | |
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| 458 | if (regCr0.cr0.paging == 0) |
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| 459 | return 0; |
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| 460 | |
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| 461 | prevPresent = 0; |
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| 462 | prevCache = 1; |
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| 463 | |
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| 464 | pagingWasEnabled = 0; |
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| 465 | |
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| 466 | if (_CPU_is_paging_enabled()){ |
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| 467 | pagingWasEnabled = 1; |
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| 468 | _CPU_disable_paging(); |
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| 469 | } |
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| 470 | |
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| 471 | for (dirCount = 0; dirCount < directoryEntry+1; dirCount++) { |
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| 472 | |
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| 473 | localPageTable = (page_table *)(pageDirectory-> |
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| 474 | pageDirEntry[dirCount].bits. |
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| 475 | page_frame_address << 12); |
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| 476 | |
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| 477 | maxPage = MAX_ENTRY; |
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| 478 | /*if ( dirCount == (directoryEntry-1)) |
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| 479 | maxPage = tableEntry;*/ |
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| 480 | for (pageCount = 0; pageCount < maxPage; pageCount++) { |
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| 481 | |
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| 482 | if (localPageTable->pageTableEntry[pageCount].bits.present != 0){ |
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| 483 | if (prevPresent == 0){ |
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| 484 | prevPresent = 1; |
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| 485 | printk ("present page from address %x \n", ((dirCount << 22)|(pageCount << 12))); |
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| 486 | } |
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| 487 | if (prevCache != localPageTable->pageTableEntry[pageCount].bits.cache_disable ) { |
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| 488 | prevCache = localPageTable->pageTableEntry[pageCount]. |
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| 489 | bits.cache_disable; |
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| 490 | printk (" cache %s from %x <phy %x>\n", |
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| 491 | (prevCache ? "DISABLE" : "ENABLE "), |
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| 492 | ((dirCount << 22)|(pageCount << 12)), |
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| 493 | localPageTable->pageTableEntry[pageCount].bits.page_frame_address << 12); |
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| 494 | } |
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| 495 | } |
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| 496 | else { |
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| 497 | if (prevPresent == 1){ |
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| 498 | prevPresent = 0; |
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| 499 | printk ("Absent from %x \n", ((dirCount << 22)|(pageCount << 12))); |
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| 500 | } |
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| 501 | } |
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| 502 | } |
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| 503 | } |
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| 504 | if (pagingWasEnabled) |
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| 505 | _CPU_enable_paging(); |
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| 506 | return 0; |
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| 507 | |
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| 508 | } |
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| 509 | |
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| 510 | |
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| 511 | |
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| 512 | |
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| 513 | |
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