source: rtems/c/src/lib/libcpu/i386/cpu.h @ 4cf920c4

4.104.114.84.95
Last change on this file since 4cf920c4 was 8ef3818, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 12, 2000 at 7:57:02 PM

Patch from John Cotton <john.cotton@…>, Charles-Antoine Gauthier
<charles.gauthier@…>, and Darlene A. Stewart
<Darlene.Stewart@…> to add support for a number of very
significant things:

+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040

and PowerPC

+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use

same code base.

+ Rework of eth_comm BSP to utiltize above.

John reports this works on the 821 and 860

  • Property mode set to 100644
File size: 11.7 KB
Line 
1/*
2 * cpu.h  - This file contains definitions for data structure related
3 *          to Intel system programming. More information can be found
4 *          on Intel site and more precisely in the following book :
5 *
6 *              Pentium Processor familly
7 *              Developper's Manual
8 *
9 *              Volume 3 : Architecture and Programming Manual
10 *
11 * Copyright (C) 1998  Eric Valette (valette@crf.canon.fr)
12 *                     Canon Centre Recherche France.
13 *
14 *  The license and distribution terms for this file may be
15 *  found in found in the file LICENSE in this distribution or at
16 *  http://www.OARcorp.com/rtems/license.html.
17 *
18 * $Id$
19 */
20
21#ifndef _LIBCPU_i386_CPU_H
22#define _LIBCPU_i386_CPU_H
23
24#include <libcpu/registers.h>
25
26
27#ifndef ASM
28
29/*
30 *  Interrupt Level Macros
31 */
32
33#define i386_disable_interrupts( _level ) \
34  { \
35    asm volatile ( "pushf ; \
36                    cli ; \
37                    pop %0" \
38                   : "=rm" ((_level)) \
39    ); \
40  }
41
42#define i386_enable_interrupts( _level )  \
43  { \
44    asm volatile ( "push %0 ; \
45                    popf" \
46                    : : "rm" ((_level)) : "cc" \
47    ); \
48  }
49
50#define i386_flash_interrupts( _level ) \
51  { \
52    asm volatile ( "push %0 ; \
53                    popf ; \
54                    cli" \
55                    : : "rm" ((_level)) : "cc" \
56    ); \
57  }
58
59#define i386_get_interrupt_level( _level ) \
60  do { \
61    register unsigned32 _eflags; \
62    \
63    asm volatile ( "pushf ; \
64                    pop %0" \
65                    : "=rm" ((_eflags)) \
66    ); \
67    \
68    _level = (_eflags & EFLAGS_INTR_ENABLE) ? 0 : 1; \
69  } while (0)
70
71#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level )
72#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level )
73     
74/*
75 *  Segment Access Routines
76 *
77 *  NOTE:  Unfortunately, these are still static inlines even when the
78 *         "macro" implementation of the generic code is used.
79 */
80
81static inline unsigned short i386_get_cs()
82{
83  register unsigned short segment = 0;
84
85  asm volatile ( "movw %%cs,%0" : "=r" (segment) : "0" (segment) );
86
87  return segment;
88}
89
90static inline unsigned short i386_get_ds()
91{
92  register unsigned short segment = 0;
93
94  asm volatile ( "movw %%ds,%0" : "=r" (segment) : "0" (segment) );
95
96  return segment;
97}
98
99static inline unsigned short i386_get_es()
100{
101  register unsigned short segment = 0;
102
103  asm volatile ( "movw %%es,%0" : "=r" (segment) : "0" (segment) );
104
105  return segment;
106}
107
108static inline unsigned short i386_get_ss()
109{
110  register unsigned short segment = 0;
111
112  asm volatile ( "movw %%ss,%0" : "=r" (segment) : "0" (segment) );
113
114  return segment;
115}
116
117static inline unsigned short i386_get_fs()
118{
119  register unsigned short segment = 0;
120
121  asm volatile ( "movw %%fs,%0" : "=r" (segment) : "0" (segment) );
122
123  return segment;
124}
125
126static inline unsigned short i386_get_gs()
127{
128  register unsigned short segment = 0;
129
130  asm volatile ( "movw %%gs,%0" : "=r" (segment) : "0" (segment) );
131
132  return segment;
133}
134
135/*
136 *  IO Port Access Routines
137 */
138
139#define i386_outport_byte( _port, _value ) \
140do { register unsigned short __port  = _port; \
141     register unsigned char  __value = _value; \
142     \
143     asm volatile ( "outb %0,%1" : : "a" (__value), "d" (__port) ); \
144   } while (0)
145
146#define i386_outport_word( _port, _value ) \
147do { register unsigned short __port  = _port; \
148     register unsigned short __value = _value; \
149     \
150     asm volatile ( "outw %0,%1" : : "a" (__value), "d" (__port) ); \
151   } while (0)
152
153#define i386_outport_long( _port, _value ) \
154do { register unsigned short __port  = _port; \
155     register unsigned int  __value = _value; \
156     \
157     asm volatile ( "outl %0,%1" : : "a" (__value), "d" (__port) ); \
158   } while (0)
159
160#define i386_inport_byte( _port, _value ) \
161do { register unsigned short __port  = _port; \
162     register unsigned char  __value = 0; \
163     \
164     asm volatile ( "inb %1,%0" : "=a" (__value) \
165                                : "d"  (__port) \
166                  ); \
167     _value = __value; \
168   } while (0)
169
170#define i386_inport_word( _port, _value ) \
171do { register unsigned short __port  = _port; \
172     register unsigned short __value = 0; \
173     \
174     asm volatile ( "inw %1,%0" : "=a" (__value) \
175                                : "d"  (__port) \
176                  ); \
177     _value = __value; \
178   } while (0)
179
180#define i386_inport_long( _port, _value ) \
181do { register unsigned short __port  = _port; \
182     register unsigned int  __value = 0; \
183     \
184     asm volatile ( "inl %1,%0" : "=a" (__value) \
185                                : "d"  (__port) \
186                  ); \
187     _value = __value; \
188   } while (0)
189
190/*
191 * Type definition for raw interrupts.
192 */
193
194typedef unsigned char  rtems_vector_offset;
195
196struct  __rtems_raw_irq_connect_data__;
197
198typedef void (*rtems_raw_irq_hdl)               (void);
199typedef void (*rtems_raw_irq_enable)            (const struct __rtems_raw_irq_connect_data__*);
200typedef void (*rtems_raw_irq_disable)           (const struct __rtems_raw_irq_connect_data__*);
201typedef int  (*rtems_raw_irq_is_enabled)        (const struct __rtems_raw_irq_connect_data__*);
202
203typedef struct __rtems_raw_irq_connect_data__{
204 /*
205  * IDT vector offset (IRQ line + PC386_IRQ_VECTOR_BASE)
206  */
207  rtems_vector_offset           idtIndex;
208  /*
209   * IDT raw handler. See comment on handler properties below in function prototype.
210   */
211  rtems_raw_irq_hdl             hdl;
212  /*
213   * function for enabling raw interrupts. In order to be consistent
214   * with the fact that the raw connexion can defined in the
215   * libcpu library, this library should have no knowledge of
216   * board specific hardware to manage interrupts and thus the
217   * "on" routine must enable the irq both at device and PIC level.
218   *
219   */
220    rtems_raw_irq_enable        on;     
221  /*
222   * function for disabling raw interrupts. In order to be consistent
223   * with the fact that the raw connexion can defined in the
224   * libcpu library, this library should have no knowledge of
225   * board specific hardware to manage interrupts and thus the
226   * "on" routine must disable the irq both at device and PIC level.
227   *
228   */
229  rtems_raw_irq_disable         off;
230  /*
231   * function enabling to know what interrupt may currently occur
232   */
233  rtems_raw_irq_is_enabled      isOn;
234}rtems_raw_irq_connect_data;
235
236typedef struct {
237  /*
238   * size of all the table fields (*Tbl) described below.
239   */
240  unsigned int                  idtSize;
241  /*
242   * Default handler used when disconnecting interrupts.
243   */
244  rtems_raw_irq_connect_data    defaultRawEntry;
245  /*
246   * Table containing initials/current value.
247   */
248  rtems_raw_irq_connect_data*   rawIrqHdlTbl;
249}rtems_raw_irq_global_settings;
250
251/*
252 * See page 14.9 Figure 14-2.
253 *
254 */
255typedef struct {
256  unsigned int low_offsets_bits : 16;
257  unsigned int segment_selector : 16;
258  unsigned int fixed_value_bits : 8;
259  unsigned int gate_type        : 5;
260  unsigned int privilege        : 2;
261  unsigned int present          : 1;
262  unsigned int high_offsets_bits: 16;
263}interrupt_gate_descriptor;
264
265
266/*
267 * C callable function enabling to create a interrupt_gate_descriptor
268 */
269void create_interrupt_gate_descriptor (interrupt_gate_descriptor*, rtems_raw_irq_hdl);
270
271/*
272 * C callable function enabling to get handler currently connected to a vector
273 *
274 */
275rtems_raw_irq_hdl get_hdl_from_vector(rtems_vector_offset);
276
277/*
278 * C callable function enabling to get easilly usable info from
279 * the actual value of IDT register.
280 */
281extern void i386_get_info_from_IDTR (interrupt_gate_descriptor** table,
282                                unsigned* limit);
283/*
284 * C callable function enabling to change the value of IDT register. Must be called
285 * with interrupts masked at processor level!!!.
286 */
287extern void i386_set_IDTR (interrupt_gate_descriptor* table,
288                      unsigned limit);
289
290/*
291 * C callable function enabling to set up one raw idt entry
292 */
293extern int i386_set_idt_entry (const rtems_raw_irq_connect_data*);
294
295/*
296 * C callable function enabling to get one current raw idt entry
297 */
298extern int i386_get_current_idt_entry (rtems_raw_irq_connect_data*);
299
300/*
301 * C callable function enabling to remove one current raw idt entry
302 */
303extern int i386_delete_idt_entry (const rtems_raw_irq_connect_data*);
304
305/*
306 * C callable function enabling to init idt.
307 *
308 * CAUTION : this function assumes that the IDTR register
309 * has been already set.
310 */
311extern int i386_init_idt (rtems_raw_irq_global_settings* config);
312
313/*
314 * C callable function enabling to get actual idt configuration
315 */
316extern int i386_get_idt_config (rtems_raw_irq_global_settings** config);
317
318
319/*
320 * See page 11.12 Figure 11-8.
321 *
322 */
323
324typedef struct {
325  unsigned int limit_15_0               : 16;
326  unsigned int base_address_15_0        : 16;
327  unsigned int base_address_23_16       : 8;
328  unsigned int type                     : 4;
329  unsigned int descriptor_type          : 1;
330  unsigned int privilege                : 2;
331  unsigned int present                  : 1;
332  unsigned int limit_19_16              : 4;
333  unsigned int available                : 1;
334  unsigned int fixed_value_bits         : 1;
335  unsigned int operation_size           : 1;
336  unsigned int granularity              : 1;
337  unsigned int base_address_31_24       : 8;
338}segment_descriptors;
339
340/*
341 * C callable function enabling to get easilly usable info from
342 * the actual value of GDT register.
343 */
344extern void i386_get_info_from_GDTR (segment_descriptors** table,
345                                     unsigned* limit);
346/*
347 * C callable function enabling to change the value of GDT register. Must be called
348 * with interrupts masked at processor level!!!.
349 */
350extern void i386_set_GDTR (segment_descriptors*,
351                           unsigned limit);
352
353/*
354 * C callable function enabling to set up one raw interrupt handler
355 */
356extern int i386_set_gdt_entry (unsigned short segment_selector, unsigned base,
357                                             unsigned limit);
358
359/*
360 * See page 11.18 Figure 11-12.
361 *
362 */
363
364typedef struct {
365  unsigned int offset                   : 12;
366  unsigned int page                     : 10;
367  unsigned int directory                : 10;
368}la_bits;
369
370typedef union {
371  la_bits       bits;
372  unsigned int  address;
373}linear_address;
374
375
376/*
377 * See page 11.20 Figure 11-14.
378 *
379 */
380
381typedef struct {
382  unsigned int present                  : 1;
383  unsigned int writable                 : 1;
384  unsigned int user                     : 1;
385  unsigned int write_through            : 1;
386  unsigned int cache_disable            : 1;
387  unsigned int accessed                 : 1;
388  unsigned int reserved1                : 1;
389  unsigned int page_size                : 1;
390  unsigned int reserved2                : 1;
391  unsigned int available                : 3;
392  unsigned int page_frame_address       : 20;
393}page_dir_bits;
394
395typedef union {
396  page_dir_bits bits;
397  unsigned int  dir_entry;
398}page_dir_entry;
399
400typedef struct {
401  unsigned int present                  : 1;
402  unsigned int writable                 : 1;
403  unsigned int user                     : 1;
404  unsigned int write_through            : 1;
405  unsigned int cache_disable            : 1;
406  unsigned int accessed                 : 1;
407  unsigned int dirty                    : 1;
408  unsigned int reserved2                : 2;
409  unsigned int available                : 3;
410  unsigned int page_frame_address       : 20;
411}page_table_bits;
412
413typedef union {
414  page_table_bits       bits;
415  unsigned int          table_entry;
416} page_table_entry;
417 
418/*
419 * definitions related to page table entry
420 */
421#define PG_SIZE 0x1000
422#define MASK_OFFSET 0xFFF
423#define MAX_ENTRY (PG_SIZE/sizeof(page_dir_entry))
424#define FOUR_MB       0x400000
425#define MASK_FLAGS 0x1A
426
427#define PTE_PRESENT             0x01
428#define PTE_WRITABLE            0x02
429#define PTE_USER                0x04
430#define PTE_WRITE_THROUGH       0x08
431#define PTE_CACHE_DISABLE       0x10
432
433typedef struct {
434  page_dir_entry pageDirEntry[MAX_ENTRY];
435} page_directory;
436
437typedef struct {
438  page_table_entry pageTableEntry[MAX_ENTRY];
439} page_table;
440
441
442/* C declaration for paging management */
443
444extern int      _CPU_is_cache_enabled();
445extern int      _CPU_is_paging_enabled();
446extern int      init_paging();
447extern void     _CPU_enable_paging();
448extern void     _CPU_disable_paging();
449extern void     _CPU_disable_cache();
450extern void     _CPU_enable_cache();
451extern int      _CPU_map_phys_address
452                      (void **mappedAddress, void *physAddress,
453                       int size, int flag); 
454extern int      _CPU_unmap_virt_address (void *mappedAddress, int size); 
455extern int      _CPU_change_memory_mapping_attribute
456                         (void **newAddress, void *mappedAddress,
457                          unsigned int size, unsigned int flag);
458extern int      _CPU_display_memory_attribute(); 
459
460# endif /* ASM */
461
462#endif
463
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