1 | /* |
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2 | * cpu.c - This file contains implementation of C function to |
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3 | * instantiate IDT entries. More detailled information can be found |
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4 | * on Intel site and more precisely in the following book : |
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5 | * |
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6 | * Pentium Processor family |
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7 | * Developper's Manual |
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8 | * |
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9 | * Volume 3 : Architecture and Programming Manual |
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10 | * |
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11 | * Copyright (C) 1998 Eric Valette (valette@crf.canon.fr) |
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12 | * Canon Centre Recherche France. |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in found in the file LICENSE in this distribution or at |
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16 | * http://www.OARcorp.com/rtems/license.html. |
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17 | * |
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18 | * $Id$ |
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19 | */ |
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20 | |
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21 | #include <libcpu/cpu.h> |
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22 | #include <irq.h> |
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23 | |
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24 | static rtems_raw_irq_connect_data* raw_irq_table; |
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25 | static rtems_raw_irq_connect_data default_raw_irq_entry; |
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26 | static interrupt_gate_descriptor default_idt_entry; |
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27 | static rtems_raw_irq_global_settings* local_settings; |
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28 | |
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29 | void create_interrupt_gate_descriptor (interrupt_gate_descriptor* idtEntry, |
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30 | rtems_raw_irq_hdl hdl) |
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31 | { |
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32 | idtEntry->low_offsets_bits = (((unsigned) hdl) & 0xffff); |
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33 | idtEntry->segment_selector = i386_get_cs(); |
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34 | idtEntry->fixed_value_bits = 0; |
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35 | idtEntry->gate_type = 0xe; |
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36 | idtEntry->privilege = 0; |
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37 | idtEntry->present = 1; |
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38 | idtEntry->high_offsets_bits = ((((unsigned) hdl) >> 16) & 0xffff); |
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39 | } |
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40 | |
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41 | rtems_raw_irq_hdl get_hdl_from_vector(rtems_vector_offset index) |
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42 | { |
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43 | rtems_raw_irq_hdl hdl; |
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44 | interrupt_gate_descriptor* idt_entry_tbl; |
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45 | unsigned limit; |
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46 | |
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47 | i386_get_info_from_IDTR (&idt_entry_tbl, &limit); |
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48 | |
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49 | /* Convert limit into number of entries */ |
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50 | limit = (limit + 1) / sizeof(interrupt_gate_descriptor); |
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51 | |
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52 | if(index >= limit) { |
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53 | return 0; |
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54 | } |
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55 | |
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56 | * ((unsigned int*) &hdl) = (idt_entry_tbl[index].low_offsets_bits | |
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57 | (idt_entry_tbl[index].high_offsets_bits << 16)); |
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58 | return hdl; |
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59 | } |
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60 | |
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61 | int i386_set_idt_entry (const rtems_raw_irq_connect_data* irq) |
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62 | { |
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63 | interrupt_gate_descriptor* idt_entry_tbl; |
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64 | unsigned limit; |
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65 | unsigned int level; |
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66 | |
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67 | |
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68 | i386_get_info_from_IDTR (&idt_entry_tbl, &limit); |
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69 | |
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70 | /* Convert limit into number of entries */ |
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71 | limit = (limit + 1) / sizeof(interrupt_gate_descriptor); |
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72 | |
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73 | if (irq->idtIndex >= limit) { |
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74 | return 0; |
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75 | } |
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76 | /* |
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77 | * Check if default handler is actually connected. If not issue an error. |
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78 | * You must first get the current handler via i386_get_current_idt_entry |
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79 | * and then disconnect it using i386_delete_idt_entry. |
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80 | * RATIONALE : to always have the same transition by forcing the user |
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81 | * to get the previous handler before accepting to disconnect. |
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82 | */ |
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83 | if (get_hdl_from_vector(irq->idtIndex) != default_raw_irq_entry.hdl) { |
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84 | return 0; |
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85 | } |
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86 | |
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87 | _CPU_ISR_Disable(level); |
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88 | |
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89 | raw_irq_table [irq->idtIndex] = *irq; |
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90 | create_interrupt_gate_descriptor (&idt_entry_tbl[irq->idtIndex], irq->hdl); |
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91 | irq->on(irq); |
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92 | |
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93 | _CPU_ISR_Enable(level); |
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94 | return 1; |
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95 | } |
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96 | |
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97 | void _CPU_ISR_install_vector (unsigned vector, |
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98 | void* hdl, |
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99 | void** oldHdl) |
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100 | { |
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101 | interrupt_gate_descriptor* idt_entry_tbl; |
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102 | unsigned limit; |
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103 | interrupt_gate_descriptor new; |
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104 | unsigned int level; |
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105 | |
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106 | i386_get_info_from_IDTR (&idt_entry_tbl, &limit); |
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107 | |
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108 | /* Convert limit into number of entries */ |
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109 | limit = (limit + 1) / sizeof(interrupt_gate_descriptor); |
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110 | |
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111 | if (vector >= limit) { |
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112 | return; |
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113 | } |
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114 | _CPU_ISR_Disable(level) |
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115 | * ((unsigned int *) oldHdl) = idt_entry_tbl[vector].low_offsets_bits | |
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116 | (idt_entry_tbl[vector].high_offsets_bits << 16); |
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117 | |
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118 | create_interrupt_gate_descriptor(&new, hdl); |
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119 | idt_entry_tbl[vector] = new; |
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120 | |
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121 | _CPU_ISR_Enable(level); |
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122 | } |
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123 | |
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124 | int i386_get_current_idt_entry (rtems_raw_irq_connect_data* irq) |
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125 | { |
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126 | interrupt_gate_descriptor* idt_entry_tbl; |
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127 | unsigned limit; |
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128 | |
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129 | i386_get_info_from_IDTR (&idt_entry_tbl, &limit); |
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130 | |
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131 | /* Convert limit into number of entries */ |
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132 | limit = (limit + 1) / sizeof(interrupt_gate_descriptor); |
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133 | |
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134 | if (irq->idtIndex >= limit) { |
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135 | return 0; |
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136 | } |
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137 | raw_irq_table [irq->idtIndex].hdl = get_hdl_from_vector(irq->idtIndex); |
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138 | |
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139 | *irq = raw_irq_table [irq->idtIndex]; |
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140 | |
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141 | return 1; |
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142 | } |
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143 | |
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144 | int i386_delete_idt_entry (const rtems_raw_irq_connect_data* irq) |
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145 | { |
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146 | interrupt_gate_descriptor* idt_entry_tbl; |
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147 | unsigned limit; |
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148 | unsigned int level; |
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149 | |
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150 | i386_get_info_from_IDTR (&idt_entry_tbl, &limit); |
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151 | |
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152 | /* Convert limit into number of entries */ |
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153 | limit = (limit + 1) / sizeof(interrupt_gate_descriptor); |
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154 | |
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155 | if (irq->idtIndex >= limit) { |
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156 | return 0; |
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157 | } |
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158 | /* |
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159 | * Check if handler passed is actually connected. If not issue an error. |
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160 | * You must first get the current handler via i386_get_current_idt_entry |
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161 | * and then disconnect it using i386_delete_idt_entry. |
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162 | * RATIONALE : to always have the same transition by forcing the user |
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163 | * to get the previous handler before accepting to disconnect. |
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164 | */ |
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165 | if (get_hdl_from_vector(irq->idtIndex) != irq->hdl){ |
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166 | return 0; |
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167 | } |
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168 | _CPU_ISR_Disable(level); |
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169 | |
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170 | idt_entry_tbl[irq->idtIndex] = default_idt_entry; |
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171 | |
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172 | irq->off(irq); |
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173 | |
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174 | raw_irq_table[irq->idtIndex] = default_raw_irq_entry; |
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175 | raw_irq_table[irq->idtIndex].idtIndex = irq->idtIndex; |
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176 | |
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177 | _CPU_ISR_Enable(level); |
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178 | |
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179 | return 1; |
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180 | } |
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181 | |
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182 | /* |
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183 | * Caution this function assumes the IDTR has been already set. |
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184 | */ |
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185 | int i386_init_idt (rtems_raw_irq_global_settings* config) |
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186 | { |
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187 | unsigned limit; |
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188 | unsigned i; |
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189 | unsigned level; |
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190 | interrupt_gate_descriptor* idt_entry_tbl; |
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191 | |
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192 | i386_get_info_from_IDTR (&idt_entry_tbl, &limit); |
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193 | |
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194 | /* Convert limit into number of entries */ |
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195 | limit = (limit + 1) / sizeof(interrupt_gate_descriptor); |
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196 | |
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197 | if (config->idtSize != limit) { |
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198 | return 0; |
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199 | } |
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200 | /* |
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201 | * store various accelarators |
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202 | */ |
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203 | raw_irq_table = config->rawIrqHdlTbl; |
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204 | local_settings = config; |
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205 | default_raw_irq_entry = config->defaultRawEntry; |
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206 | |
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207 | _CPU_ISR_Disable(level); |
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208 | |
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209 | create_interrupt_gate_descriptor (&default_idt_entry, default_raw_irq_entry.hdl); |
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210 | |
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211 | for (i=0; i < limit; i++) { |
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212 | interrupt_gate_descriptor new; |
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213 | create_interrupt_gate_descriptor (&new, raw_irq_table[i].hdl); |
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214 | idt_entry_tbl[i] = new; |
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215 | if (raw_irq_table[i].hdl != default_raw_irq_entry.hdl) { |
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216 | raw_irq_table[i].on(&raw_irq_table[i]); |
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217 | } |
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218 | else { |
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219 | raw_irq_table[i].off(&raw_irq_table[i]); |
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220 | } |
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221 | } |
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222 | _CPU_ISR_Enable(level); |
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223 | |
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224 | return 1; |
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225 | } |
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226 | |
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227 | int i386_get_idt_config (rtems_raw_irq_global_settings** config) |
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228 | { |
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229 | *config = local_settings; |
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230 | return 1; |
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231 | } |
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232 | |
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233 | /* |
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234 | * Caution this function assumes the GDTR has been already set. |
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235 | */ |
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236 | int i386_set_gdt_entry (unsigned short segment_selector, unsigned base, |
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237 | unsigned limit) |
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238 | { |
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239 | unsigned gdt_limit; |
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240 | unsigned short tmp_segment = 0; |
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241 | unsigned int limit_adjusted; |
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242 | segment_descriptors* gdt_entry_tbl; |
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243 | |
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244 | |
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245 | i386_get_info_from_GDTR (&gdt_entry_tbl, &gdt_limit); |
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246 | |
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247 | if (segment_selector > limit) { |
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248 | return 0; |
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249 | } |
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250 | /* |
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251 | * set up limit first |
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252 | */ |
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253 | limit_adjusted = limit; |
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254 | if ( limit > 4095 ) { |
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255 | gdt_entry_tbl[segment_selector].granularity = 1; |
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256 | limit_adjusted /= 4096; |
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257 | } |
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258 | gdt_entry_tbl[segment_selector].limit_15_0 = limit_adjusted & 0xffff; |
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259 | gdt_entry_tbl[segment_selector].limit_19_16 = (limit_adjusted >> 16) & 0xf; |
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260 | /* |
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261 | * set up base |
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262 | */ |
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263 | gdt_entry_tbl[segment_selector].base_address_15_0 = base & 0xffff; |
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264 | gdt_entry_tbl[segment_selector].base_address_23_16 = (base >> 16) & 0xff; |
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265 | gdt_entry_tbl[segment_selector].base_address_31_24 = (base >> 24) & 0xff; |
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266 | /* |
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267 | * set up descriptor type (this may well becomes a parameter if needed) |
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268 | */ |
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269 | gdt_entry_tbl[segment_selector].type = 2; /* Data R/W */ |
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270 | gdt_entry_tbl[segment_selector].descriptor_type = 1; /* Code or Data */ |
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271 | gdt_entry_tbl[segment_selector].privilege = 0; /* ring 0 */ |
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272 | gdt_entry_tbl[segment_selector].present = 1; /* not present */ |
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273 | |
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274 | /* |
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275 | * Now, reload all segment registers so the limit takes effect. |
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276 | */ |
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277 | |
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278 | asm volatile( "movw %%ds,%0 ; movw %0,%%ds |
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279 | movw %%es,%0 ; movw %0,%%es |
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280 | movw %%fs,%0 ; movw %0,%%fs |
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281 | movw %%gs,%0 ; movw %0,%%gs |
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282 | movw %%ss,%0 ; movw %0,%%ss" |
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283 | : "=r" (tmp_segment) |
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284 | : "0" (tmp_segment) |
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285 | ); |
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286 | |
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287 | return 1; |
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288 | } |
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