source: rtems/c/src/lib/libcpu/i386/cache.c @ cf1f72e

4.104.114.84.95
Last change on this file since cf1f72e was cf1f72e, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 13, 2000 at 9:53:38 PM

Moved i386 and m68k cache management code to libcpu. Everything
now is an implementation of the prototypes in rtems/rtems/cache.h.
The libcpu/i386/wrapup directory is no longer needed.
The PowerPC needs this done to it.

  • Property mode set to 100644
File size: 2.1 KB
Line 
1/*
2 *  Cache Management Support Routines for the i386
3 *
4 *  $Id$
5 */
6
7#include <rtems.h>
8#include <libcpu/registers.h>
9#include "cache_.h"
10
11void _CPU_disable_cache() {
12  cr0 regCr0;
13
14  regCr0.i = i386_get_cr0();
15  regCr0.cr0.page_level_cache_disable = 1;
16  regCr0.cr0.no_write_through = 1;
17  i386_set_cr0( regCr0.i );
18  rtems_flush_entire_data_cache();
19}
20
21/*
22 * Enable the entire cache
23 */
24
25void _CPU_enable_cache() {
26  cr0 regCr0;
27
28  regCr0.i = i386_get_cr0();
29  regCr0.cr0.page_level_cache_disable = 0;
30  regCr0.cr0.no_write_through = 0;
31  i386_set_cr0( regCr0.i );
32  /*rtems_flush_entire_data_cache();*/
33}
34
35/*
36 * CACHE MANAGER: The following functions are CPU-specific.
37 * They provide the basic implementation for the rtems_* cache
38 * management routines. If a given function has no meaning for the CPU,
39 * it does nothing by default.
40 *
41 * FIXME: Definitions for I386_CACHE_ALIGNMENT are missing above for
42 *        each CPU. The routines below should be implemented per CPU,
43 *        to accomodate the capabilities of each.
44 */
45
46/* FIXME: I don't belong here. */
47#define I386_CACHE_ALIGNMENT 16
48
49#if defined(I386_CACHE_ALIGNMENT)
50#define _CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
51#define _CPU_INST_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
52
53void _CPU_flush_1_data_cache_line(const void *d_addr) {}
54void _CPU_invalidate_1_data_cache_line(const void *d_addr) {}
55void _CPU_freeze_data_cache(void) {}
56void _CPU_unfreeze_data_cache(void) {}
57void _CPU_invalidate_1_inst_cache_line ( const void *d_addr ) {}
58void _CPU_freeze_inst_cache(void) {}
59void _CPU_unfreeze_inst_cache(void) {}
60
61void _CPU_flush_entire_data_cache(
62  const void * d_addr
63)
64{
65  asm volatile ("wbinvd");
66}
67void _CPU_invalidate_entire_data_cache(
68  const void * d_addr
69)
70{
71  asm volatile ("invd");
72}
73
74void _CPU_enable_data_cache(void)
75{
76        _CPU_enable_cache();
77}
78
79void _CPU_disable_data_cache(void)
80{
81        _CPU_disable_cache();
82}
83
84void _CPU_invalidate_entire_inst_cache(void)
85{
86  asm volatile ("invd");
87}
88
89void _CPU_enable_inst_cache(void)
90{
91  _CPU_enable_cache();
92}
93
94void _CPU_disable_inst_cache( void )
95{
96  _CPU_disable_cache();
97}
98#endif
99
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