source: rtems/c/src/lib/libcpu/i386/cache.c @ 5e77d129

4.104.114.84.95
Last change on this file since 5e77d129 was 5e77d129, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 14, 2000 at 8:32:44 PM

Patch from John Cotton <john.cotton@…> to correct cache
routine naming to follow RTEMS package/object.method rule.
This patch also eliminated calls to the obsolete routine
m68k_enable_caching.

  • Property mode set to 100644
File size: 1.8 KB
Line 
1/*
2 *  Cache Management Support Routines for the i386
3 *
4 *  $Id$
5 */
6
7#include <rtems.h>
8#include <libcpu/registers.h>
9#include "cache_.h"
10
11void _CPU_disable_cache() {
12  cr0 regCr0;
13
14  regCr0.i = i386_get_cr0();
15  regCr0.cr0.page_level_cache_disable = 1;
16  regCr0.cr0.no_write_through = 1;
17  i386_set_cr0( regCr0.i );
18  rtems_cache_flush_entire_data();
19}
20
21/*
22 * Enable the entire cache
23 */
24
25void _CPU_enable_cache() {
26  cr0 regCr0;
27
28  regCr0.i = i386_get_cr0();
29  regCr0.cr0.page_level_cache_disable = 0;
30  regCr0.cr0.no_write_through = 0;
31  i386_set_cr0( regCr0.i );
32  /*rtems_cache_flush_entire_data();*/
33}
34
35/*
36 * CACHE MANAGER: The following functions are CPU-specific.
37 * They provide the basic implementation for the rtems_* cache
38 * management routines. If a given function has no meaning for the CPU,
39 * it does nothing by default.
40 *
41 * FIXME: The routines below should be implemented per CPU,
42 *        to accomodate the capabilities of each.
43 */
44
45#if defined(I386_CACHE_ALIGNMENT)
46void _CPU_cache_flush_1_data_line(const void *d_addr) {}
47void _CPU_cache_invalidate_1_data_line(const void *d_addr) {}
48void _CPU_cache_freeze_data(void) {}
49void _CPU_cache_unfreeze_data(void) {}
50void _CPU_cache_invalidate_1_instruction_line ( const void *d_addr ) {}
51void _CPU_cache_freeze_instruction(void) {}
52void _CPU_cache_unfreeze_instruction(void) {}
53
54void _CPU_cache_flush_entire_data(void)
55{
56  asm volatile ("wbinvd");
57}
58void _CPU_cache_invalidate_entire_data(void)
59{
60  asm volatile ("invd");
61}
62
63void _CPU_cache_enable_data(void)
64{
65        _CPU_enable_cache();
66}
67
68void _CPU_cache_disable_data(void)
69{
70        _CPU_disable_cache();
71}
72
73void _CPU_cache_invalidate_entire_instruction(void)
74{
75  asm volatile ("invd");
76}
77
78void _CPU_cache_enable_instruction(void)
79{
80  _CPU_enable_cache();
81}
82
83void _CPU_cache_disable_instruction( void )
84{
85  _CPU_disable_cache();
86}
87#endif
88
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