[cf1f72e] | 1 | /* |
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| 2 | * Cache Management Support Routines for the i386 |
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| 3 | */ |
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| 4 | |
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| 5 | #include <rtems.h> |
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[43f67aa4] | 6 | #include <rtems/score/registers.h> |
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[cf1f72e] | 7 | #include "cache_.h" |
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| 8 | |
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[1b502424] | 9 | void _CPU_disable_cache(void) { |
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[665285f] | 10 | unsigned int regCr0; |
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[cf1f72e] | 11 | |
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[665285f] | 12 | regCr0 = i386_get_cr0(); |
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| 13 | regCr0 |= CR0_PAGE_LEVEL_CACHE_DISABLE; |
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| 14 | regCr0 |= CR0_NO_WRITE_THROUGH; |
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| 15 | i386_set_cr0( regCr0 ); |
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[5e77d129] | 16 | rtems_cache_flush_entire_data(); |
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[cf1f72e] | 17 | } |
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| 18 | |
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| 19 | /* |
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| 20 | * Enable the entire cache |
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| 21 | */ |
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| 22 | |
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[1b502424] | 23 | void _CPU_enable_cache(void) { |
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[665285f] | 24 | unsigned int regCr0; |
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[cf1f72e] | 25 | |
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[665285f] | 26 | regCr0 = i386_get_cr0(); |
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| 27 | regCr0 &= ~(CR0_PAGE_LEVEL_CACHE_DISABLE); |
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| 28 | regCr0 &= ~(CR0_NO_WRITE_THROUGH); |
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| 29 | i386_set_cr0( regCr0 ); |
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[5e77d129] | 30 | /*rtems_cache_flush_entire_data();*/ |
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[cf1f72e] | 31 | } |
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| 32 | |
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| 33 | /* |
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| 34 | * CACHE MANAGER: The following functions are CPU-specific. |
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| 35 | * They provide the basic implementation for the rtems_* cache |
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| 36 | * management routines. If a given function has no meaning for the CPU, |
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| 37 | * it does nothing by default. |
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| 38 | * |
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[5e77d129] | 39 | * FIXME: The routines below should be implemented per CPU, |
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[cf1f72e] | 40 | * to accomodate the capabilities of each. |
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| 41 | */ |
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| 42 | |
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| 43 | #if defined(I386_CACHE_ALIGNMENT) |
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[5e77d129] | 44 | void _CPU_cache_flush_1_data_line(const void *d_addr) {} |
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| 45 | void _CPU_cache_invalidate_1_data_line(const void *d_addr) {} |
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| 46 | void _CPU_cache_freeze_data(void) {} |
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| 47 | void _CPU_cache_unfreeze_data(void) {} |
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| 48 | void _CPU_cache_invalidate_1_instruction_line ( const void *d_addr ) {} |
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| 49 | void _CPU_cache_freeze_instruction(void) {} |
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| 50 | void _CPU_cache_unfreeze_instruction(void) {} |
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| 51 | |
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| 52 | void _CPU_cache_flush_entire_data(void) |
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[cf1f72e] | 53 | { |
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[550c1b23] | 54 | __asm__ volatile ("wbinvd"); |
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[cf1f72e] | 55 | } |
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[5e77d129] | 56 | void _CPU_cache_invalidate_entire_data(void) |
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[cf1f72e] | 57 | { |
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[550c1b23] | 58 | __asm__ volatile ("invd"); |
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[cf1f72e] | 59 | } |
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| 60 | |
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[5e77d129] | 61 | void _CPU_cache_enable_data(void) |
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[cf1f72e] | 62 | { |
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| 63 | _CPU_enable_cache(); |
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| 64 | } |
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| 65 | |
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[5e77d129] | 66 | void _CPU_cache_disable_data(void) |
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[cf1f72e] | 67 | { |
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| 68 | _CPU_disable_cache(); |
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| 69 | } |
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| 70 | |
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[5e77d129] | 71 | void _CPU_cache_invalidate_entire_instruction(void) |
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[cf1f72e] | 72 | { |
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[550c1b23] | 73 | __asm__ volatile ("invd"); |
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[cf1f72e] | 74 | } |
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| 75 | |
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[5e77d129] | 76 | void _CPU_cache_enable_instruction(void) |
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[cf1f72e] | 77 | { |
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| 78 | _CPU_enable_cache(); |
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| 79 | } |
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| 80 | |
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[5e77d129] | 81 | void _CPU_cache_disable_instruction( void ) |
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[cf1f72e] | 82 | { |
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| 83 | _CPU_disable_cache(); |
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| 84 | } |
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| 85 | #endif |
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