[cf1f72e] | 1 | /* |
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| 2 | * Cache Management Support Routines for the i386 |
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| 3 | * |
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| 4 | * $Id$ |
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| 5 | */ |
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| 6 | |
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| 7 | #include <rtems.h> |
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| 8 | #include <libcpu/registers.h> |
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| 9 | #include "cache_.h" |
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| 10 | |
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| 11 | void _CPU_disable_cache() { |
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| 12 | cr0 regCr0; |
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| 13 | |
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| 14 | regCr0.i = i386_get_cr0(); |
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| 15 | regCr0.cr0.page_level_cache_disable = 1; |
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| 16 | regCr0.cr0.no_write_through = 1; |
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| 17 | i386_set_cr0( regCr0.i ); |
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[5e77d129] | 18 | rtems_cache_flush_entire_data(); |
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[cf1f72e] | 19 | } |
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| 20 | |
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| 21 | /* |
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| 22 | * Enable the entire cache |
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| 23 | */ |
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| 24 | |
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| 25 | void _CPU_enable_cache() { |
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| 26 | cr0 regCr0; |
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| 27 | |
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| 28 | regCr0.i = i386_get_cr0(); |
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| 29 | regCr0.cr0.page_level_cache_disable = 0; |
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| 30 | regCr0.cr0.no_write_through = 0; |
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| 31 | i386_set_cr0( regCr0.i ); |
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[5e77d129] | 32 | /*rtems_cache_flush_entire_data();*/ |
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[cf1f72e] | 33 | } |
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| 34 | |
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| 35 | /* |
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| 36 | * CACHE MANAGER: The following functions are CPU-specific. |
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| 37 | * They provide the basic implementation for the rtems_* cache |
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| 38 | * management routines. If a given function has no meaning for the CPU, |
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| 39 | * it does nothing by default. |
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| 40 | * |
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[5e77d129] | 41 | * FIXME: The routines below should be implemented per CPU, |
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[cf1f72e] | 42 | * to accomodate the capabilities of each. |
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| 43 | */ |
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| 44 | |
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| 45 | #if defined(I386_CACHE_ALIGNMENT) |
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[5e77d129] | 46 | void _CPU_cache_flush_1_data_line(const void *d_addr) {} |
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| 47 | void _CPU_cache_invalidate_1_data_line(const void *d_addr) {} |
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| 48 | void _CPU_cache_freeze_data(void) {} |
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| 49 | void _CPU_cache_unfreeze_data(void) {} |
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| 50 | void _CPU_cache_invalidate_1_instruction_line ( const void *d_addr ) {} |
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| 51 | void _CPU_cache_freeze_instruction(void) {} |
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| 52 | void _CPU_cache_unfreeze_instruction(void) {} |
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| 53 | |
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| 54 | void _CPU_cache_flush_entire_data(void) |
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[cf1f72e] | 55 | { |
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| 56 | asm volatile ("wbinvd"); |
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| 57 | } |
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[5e77d129] | 58 | void _CPU_cache_invalidate_entire_data(void) |
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[cf1f72e] | 59 | { |
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| 60 | asm volatile ("invd"); |
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| 61 | } |
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| 62 | |
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[5e77d129] | 63 | void _CPU_cache_enable_data(void) |
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[cf1f72e] | 64 | { |
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| 65 | _CPU_enable_cache(); |
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| 66 | } |
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| 67 | |
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[5e77d129] | 68 | void _CPU_cache_disable_data(void) |
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[cf1f72e] | 69 | { |
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| 70 | _CPU_disable_cache(); |
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| 71 | } |
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| 72 | |
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[5e77d129] | 73 | void _CPU_cache_invalidate_entire_instruction(void) |
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[cf1f72e] | 74 | { |
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| 75 | asm volatile ("invd"); |
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| 76 | } |
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| 77 | |
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[5e77d129] | 78 | void _CPU_cache_enable_instruction(void) |
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[cf1f72e] | 79 | { |
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| 80 | _CPU_enable_cache(); |
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| 81 | } |
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| 82 | |
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[5e77d129] | 83 | void _CPU_cache_disable_instruction( void ) |
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[cf1f72e] | 84 | { |
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| 85 | _CPU_disable_cache(); |
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| 86 | } |
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| 87 | #endif |
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| 88 | |
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