source: rtems/c/src/lib/libcpu/i386/cache.c @ 328bd35

Last change on this file since 328bd35 was 328bd35, checked in by Joel Sherrill <joel@…>, on Jan 23, 2016 at 7:06:22 PM

i386: refactor libcpu/cpu.h into rtems/score/i386.h

Fixes #2515.

  • Property mode set to 100644
File size: 1.9 KB
RevLine 
[cf1f72e]1/*
2 *  Cache Management Support Routines for the i386
3 */
4
5#include <rtems.h>
6#include "cache_.h"
[328bd35]7#include <rtems/score/cpu.h>
8#include <libcpu/page.h>
[cf1f72e]9
[e6e63f8]10void _CPU_disable_cache(void)
11{
[665285f]12  unsigned int regCr0;
[cf1f72e]13
[665285f]14  regCr0 = i386_get_cr0();
15  regCr0 |= CR0_PAGE_LEVEL_CACHE_DISABLE;
16  regCr0 |= CR0_NO_WRITE_THROUGH;
17  i386_set_cr0( regCr0 );
[5e77d129]18  rtems_cache_flush_entire_data();
[cf1f72e]19}
20
21/*
22 * Enable the entire cache
23 */
24
[e6e63f8]25void _CPU_enable_cache(void)
26{
[665285f]27  unsigned int regCr0;
[cf1f72e]28
[665285f]29  regCr0 = i386_get_cr0();
30  regCr0 &= ~(CR0_PAGE_LEVEL_CACHE_DISABLE);
31  regCr0 &= ~(CR0_NO_WRITE_THROUGH);
32  i386_set_cr0( regCr0 );
[5e77d129]33  /*rtems_cache_flush_entire_data();*/
[cf1f72e]34}
35
36/*
37 * CACHE MANAGER: The following functions are CPU-specific.
38 * They provide the basic implementation for the rtems_* cache
39 * management routines. If a given function has no meaning for the CPU,
40 * it does nothing by default.
41 *
[5e77d129]42 * FIXME: The routines below should be implemented per CPU,
[cf1f72e]43 *        to accomodate the capabilities of each.
44 */
45
46#if defined(I386_CACHE_ALIGNMENT)
[5e77d129]47void _CPU_cache_flush_1_data_line(const void *d_addr) {}
48void _CPU_cache_invalidate_1_data_line(const void *d_addr) {}
49void _CPU_cache_freeze_data(void) {}
50void _CPU_cache_unfreeze_data(void) {}
51void _CPU_cache_invalidate_1_instruction_line ( const void *d_addr ) {}
52void _CPU_cache_freeze_instruction(void) {}
53void _CPU_cache_unfreeze_instruction(void) {}
54
55void _CPU_cache_flush_entire_data(void)
[cf1f72e]56{
[550c1b23]57  __asm__ volatile ("wbinvd");
[cf1f72e]58}
[5e77d129]59void _CPU_cache_invalidate_entire_data(void)
[cf1f72e]60{
[550c1b23]61  __asm__ volatile ("invd");
[cf1f72e]62}
63
[5e77d129]64void _CPU_cache_enable_data(void)
[cf1f72e]65{
66        _CPU_enable_cache();
67}
68
[5e77d129]69void _CPU_cache_disable_data(void)
[cf1f72e]70{
71        _CPU_disable_cache();
72}
73
[5e77d129]74void _CPU_cache_invalidate_entire_instruction(void)
[cf1f72e]75{
[550c1b23]76  __asm__ volatile ("invd");
[cf1f72e]77}
78
[5e77d129]79void _CPU_cache_enable_instruction(void)
[cf1f72e]80{
81  _CPU_enable_cache();
82}
83
[5e77d129]84void _CPU_cache_disable_instruction( void )
[cf1f72e]85{
86  _CPU_disable_cache();
87}
88#endif
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