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milli.S @ 34174c72

4.104.114.84.95

Last change on this file since 34174c72 was 34174c72, checked in by Joel Sherrill <joel.sherrill@…>, on 12/16/02 at 17:35:55

2002-12-16 Joel Sherrill <joel@…>

milli/milli.S: Per PR329, use GNU binutils assembler directives.

Property mode set to 100644

File size: 55.6 KB

Line
1	;
2	; (c) Copyright 1986 HEWLETT-PACKARD COMPANY
3	;
4	; To anyone who acknowledges that this file is provided "AS IS"
5	; without any express or implied warranty:
6	; permission to use, copy, modify, and distribute this file
7	; for any purpose is hereby granted without fee, provided that
8	; the above copyright notice and this notice appears in all
9	; copies, and that the name of Hewlett-Packard Company not be
10	; used in advertising or publicity pertaining to distribution
11	; of the software without specific, written prior permission.
12	; Hewlett-Packard Company makes no representations about the
13	; suitability of this software for any purpose.
14	;
15
16	; Standard Hardware Register Definitions for Use with Assembler
17	; version A.08.06
18	; - fr16-31 added at Utah
19	;
20	; $Id$
21	;
22	;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
23	; Hardware General Registers
24	r0: .equ 0
25
26	r1: .equ 1
27
28	r2: .equ 2
29
30	r3: .equ 3
31
32	r4: .equ 4
33
34	r5: .equ 5
35
36	r6: .equ 6
37
38	r7: .equ 7
39
40	r8: .equ 8
41
42	r9: .equ 9
43
44	r10: .equ 10
45
46	r11: .equ 11
47
48	r12: .equ 12
49
50	r13: .equ 13
51
52	r14: .equ 14
53
54	r15: .equ 15
55
56	r16: .equ 16
57
58	r17: .equ 17
59
60	r18: .equ 18
61
62	r19: .equ 19
63
64	r20: .equ 20
65
66	r21: .equ 21
67
68	r22: .equ 22
69
70	r23: .equ 23
71
72	r24: .equ 24
73
74	r25: .equ 25
75
76	r26: .equ 26
77
78	r27: .equ 27
79
80	r28: .equ 28
81
82	r29: .equ 29
83
84	r30: .equ 30
85
86	r31: .equ 31
87
88	; Hardware Space Registers
89	sr0: .equ 0
90
91	sr1: .equ 1
92
93	sr2: .equ 2
94
95	sr3: .equ 3
96
97	sr4: .equ 4
98
99	sr5: .equ 5
100
101	sr6: .equ 6
102
103	sr7: .equ 7
104
105	; Hardware Floating Point Registers
106	fr0: .equ 0
107
108	fr1: .equ 1
109
110	fr2: .equ 2
111
112	fr3: .equ 3
113
114	fr4: .equ 4
115
116	fr5: .equ 5
117
118	fr6: .equ 6
119
120	fr7: .equ 7
121
122	fr8: .equ 8
123
124	fr9: .equ 9
125
126	fr10: .equ 10
127
128	fr11: .equ 11
129
130	fr12: .equ 12
131
132	fr13: .equ 13
133
134	fr14: .equ 14
135
136	fr15: .equ 15
137
138	fr16: .equ 16
139
140	fr17: .equ 17
141
142	fr18: .equ 18
143
144	fr19: .equ 19
145
146	fr20: .equ 20
147
148	fr21: .equ 21
149
150	fr22: .equ 22
151
152	fr23: .equ 23
153
154	fr24: .equ 24
155
156	fr25: .equ 25
157
158	fr26: .equ 26
159
160	fr27: .equ 27
161
162	fr28: .equ 28
163
164	fr29: .equ 29
165
166	fr30: .equ 30
167
168	fr31: .equ 31
169
170	; Hardware Control Registers
171	cr0: .equ 0
172
173	rctr: .equ 0 ; Recovery Counter Register
174
175
176	cr8: .equ 8 ; Protection ID 1
177
178	pidr1: .equ 8
179
180
181	cr9: .equ 9 ; Protection ID 2
182
183	pidr2: .equ 9
184
185
186	cr10: .equ 10
187
188	ccr: .equ 10 ; Coprocessor Confiquration Register
189
190
191	cr11: .equ 11
192
193	sar: .equ 11 ; Shift Amount Register
194
195
196	cr12: .equ 12
197
198	pidr3: .equ 12 ; Protection ID 3
199
200
201	cr13: .equ 13
202
203	pidr4: .equ 13 ; Protection ID 4
204
205
206	cr14: .equ 14
207
208	iva: .equ 14 ; Interrupt Vector Address
209
210
211	cr15: .equ 15
212
213	eiem: .equ 15 ; External Interrupt Enable Mask
214
215
216	cr16: .equ 16
217
218	itmr: .equ 16 ; Interval Timer
219
220
221	cr17: .equ 17
222
223	pcsq: .equ 17 ; Program Counter Space queue
224
225
226	cr18: .equ 18
227
228	pcoq: .equ 18 ; Program Counter Offset queue
229
230
231	cr19: .equ 19
232
233	iir: .equ 19 ; Interruption Instruction Register
234
235
236	cr20: .equ 20
237
238	isr: .equ 20 ; Interruption Space Register
239
240
241	cr21: .equ 21
242
243	ior: .equ 21 ; Interruption Offset Register
244
245
246	cr22: .equ 22
247
248	ipsw: .equ 22 ; Interrpution Processor Status Word
249
250
251	cr23: .equ 23
252
253	eirr: .equ 23 ; External Interrupt Request
254
255
256	cr24: .equ 24
257
258	ppda: .equ 24 ; Physcial Page Directory Address
259
260	tr0: .equ 24 ; Temporary register 0
261
262
263	cr25: .equ 25
264
265	hta: .equ 25 ; Hash Table Address
266
267	tr1: .equ 25 ; Temporary register 1
268
269
270	cr26: .equ 26
271
272	tr2: .equ 26 ; Temporary register 2
273
274
275	cr27: .equ 27
276
277	tr3: .equ 27 ; Temporary register 3
278
279
280	cr28: .equ 28
281
282	tr4: .equ 28 ; Temporary register 4
283
284
285	cr29: .equ 29
286
287	tr5: .equ 29 ; Temporary register 5
288
289
290	cr30: .equ 30
291
292	tr6: .equ 30 ; Temporary register 6
293
294
295	cr31: .equ 31
296
297	tr7: .equ 31 ; Temporary register 7
298
299	;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
300	; Procedure Call Convention ~
301	; Register Definitions for Use with Assembler ~
302	; version A.08.06
303	;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
304	; Software Architecture General Registers
305	rp: .equ r2 ; return pointer
306
307	mrp: .equ r31 ; millicode return pointer
308
309	ret0: .equ r28 ; return value
310
311	ret1: .equ r29 ; return value (high part of double)
312
313	sl: .equ r29 ; static link
314
315	sp: .equ r30 ; stack pointer
316
317	dp: .equ r27 ; data pointer
318
319	arg0: .equ r26 ; argument
320
321	arg1: .equ r25 ; argument or high part of double argument
322
323	arg2: .equ r24 ; argument
324
325	arg3: .equ r23 ; argument or high part of double argument
326
327	;_____________________________________________________________________________
328	; Software Architecture Space Registers
329	; sr0 ; return link form BLE
330	sret: .equ sr1 ; return value
331
332	sarg: .equ sr1 ; argument
333
334	; sr4 ; PC SPACE tracker
335	; sr5 ; process private data
336	;_____________________________________________________________________________
337	; Software Architecture Pseudo Registers
338	previous_sp: .equ 64 ; old stack pointer (locates previous frame)
339
340	;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
341	;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
342	; Standard space and subspace definitions. version A.08.06
343	; These are generally suitable for programs on HP_UX and HPE.
344	; Statements commented out are used when building such things as operating
345	; system kernels.
346	;;;;;;;;;;;;;;;;
347	#if 0
348	.SPACE $TEXT$, SPNUM=0,SORT=8
349	.subspa $MILLICODE$, QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=8
350	.subspa $LIT$, QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=16
351	.subspa $CODE$, QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=24
352	#else
353	.text
354	#endif
355	; Additional code subspaces should have ALIGN=8 for an interspace BV
356	; and should have SORT=24.
357	;
358	; For an incomplete executable (program bound to shared libraries),
359	; sort keys $GLOBAL$ -1 and $GLOBAL$ -2 are reserved for the $DLT$
360	; and $PLT$ subspaces respectively.
361	;;;;;;;;;;;;;;;
362	#if 0
363	.SPACE $PRIVATE$, SPNUM=1,PRIVATE,SORT=16
364	.subspa $GLOBAL$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=40
365	.import $global$
366	.subspa $DATA$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=16
367	.subspa $BSS$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=82,ZERO
368
369	.SPACE $TEXT$
370	#else
371	.text
372	#endif
373	#if 0
374	.SUBSPA $MILLICODE$
375	#endif
376
377	.align 8
378	.EXPORT $$remI,millicode
379	; .IMPORT cerror
380	$$remI:
381	.PROC
382	.CALLINFO millicode
383	.ENTRY
384	addit,= 0,arg1,r0
385	add,>= r0,arg0,ret1
386	sub r0,ret1,ret1
387	sub r0,arg1,r1
388	ds r0,r1,r0
389	or r0,r0,r1
390	add ret1,ret1,ret1
391	ds r1,arg1,r1
392	addc ret1,ret1,ret1
393	ds r1,arg1,r1
394	addc ret1,ret1,ret1
395	ds r1,arg1,r1
396	addc ret1,ret1,ret1
397	ds r1,arg1,r1
398	addc ret1,ret1,ret1
399	ds r1,arg1,r1
400	addc ret1,ret1,ret1
401	ds r1,arg1,r1
402	addc ret1,ret1,ret1
403	ds r1,arg1,r1
404	addc ret1,ret1,ret1
405	ds r1,arg1,r1
406	addc ret1,ret1,ret1
407	ds r1,arg1,r1
408	addc ret1,ret1,ret1
409	ds r1,arg1,r1
410	addc ret1,ret1,ret1
411	ds r1,arg1,r1
412	addc ret1,ret1,ret1
413	ds r1,arg1,r1
414	addc ret1,ret1,ret1
415	ds r1,arg1,r1
416	addc ret1,ret1,ret1
417	ds r1,arg1,r1
418	addc ret1,ret1,ret1
419	ds r1,arg1,r1
420	addc ret1,ret1,ret1
421	ds r1,arg1,r1
422	addc ret1,ret1,ret1
423	ds r1,arg1,r1
424	addc ret1,ret1,ret1
425	ds r1,arg1,r1
426	addc ret1,ret1,ret1
427	ds r1,arg1,r1
428	addc ret1,ret1,ret1
429	ds r1,arg1,r1
430	addc ret1,ret1,ret1
431	ds r1,arg1,r1
432	addc ret1,ret1,ret1
433	ds r1,arg1,r1
434	addc ret1,ret1,ret1
435	ds r1,arg1,r1
436	addc ret1,ret1,ret1
437	ds r1,arg1,r1
438	addc ret1,ret1,ret1
439	ds r1,arg1,r1
440	addc ret1,ret1,ret1
441	ds r1,arg1,r1
442	addc ret1,ret1,ret1
443	ds r1,arg1,r1
444	addc ret1,ret1,ret1
445	ds r1,arg1,r1
446	addc ret1,ret1,ret1
447	ds r1,arg1,r1
448	addc ret1,ret1,ret1
449	ds r1,arg1,r1
450	addc ret1,ret1,ret1
451	ds r1,arg1,r1
452	addc ret1,ret1,ret1
453	ds r1,arg1,r1
454	addc ret1,ret1,ret1
455	movb,>=,n r1,ret1,remI300
456	add,< arg1,r0,r0
457	add,tr r1,arg1,ret1
458	sub r1,arg1,ret1
459	remI300: add,>= arg0,r0,r0
460
461	sub r0,ret1,ret1
462	bv r0(r31)
463	nop
464	.EXIT
465	.PROCEND
466
467	bit1: .equ 1
468
469	bit30: .equ 30
470	bit31: .equ 31
471
472	len2: .equ 2
473
474	len4: .equ 4
475
476
477	$$dyncall:
478	.proc
479	.callinfo NO_CALLS
480	.entry
481	.export $$dyncall,MILLICODE
482
483	bb,>=,n 22,bit30,noshlibs
484
485	depi 0,bit31,len2,22
486	ldw 4(22),19
487	ldw 0(22),22
488	noshlibs:
489	ldsid (22),r1
490	mtsp r1,sr0
491	be 0(sr0,r22)
492	stw rp,-24(sp)
493	.exit
494	.procend
495
496	temp: .EQU r1
497
498	retreg: .EQU ret1 ; r29
499
500
501	.export $$divU,millicode
502	.import $$divU_3,millicode
503	.import $$divU_5,millicode
504	.import $$divU_6,millicode
505	.import $$divU_7,millicode
506	.import $$divU_9,millicode
507	.import $$divU_10,millicode
508	.import $$divU_12,millicode
509	.import $$divU_14,millicode
510	.import $$divU_15,millicode
511	$$divU:
512	.proc
513	.callinfo millicode
514	.entry
515	; The subtract is not nullified since it does no harm and can be used
516	; by the two cases that branch back to "normal".
517	comib,>= 15,arg1,special_divisor
518	sub r0,arg1,temp ; clear carry, negate the divisor
519	ds r0,temp,r0 ; set V-bit to 1
520	normal:
521	add arg0,arg0,retreg ; shift msb bit into carry
522	ds r0,arg1,temp ; 1st divide step, if no carry
523	addc retreg,retreg,retreg ; shift retreg with/into carry
524	ds temp,arg1,temp ; 2nd divide step
525	addc retreg,retreg,retreg ; shift retreg with/into carry
526	ds temp,arg1,temp ; 3rd divide step
527	addc retreg,retreg,retreg ; shift retreg with/into carry
528	ds temp,arg1,temp ; 4th divide step
529	addc retreg,retreg,retreg ; shift retreg with/into carry
530	ds temp,arg1,temp ; 5th divide step
531	addc retreg,retreg,retreg ; shift retreg with/into carry
532	ds temp,arg1,temp ; 6th divide step
533	addc retreg,retreg,retreg ; shift retreg with/into carry
534	ds temp,arg1,temp ; 7th divide step
535	addc retreg,retreg,retreg ; shift retreg with/into carry
536	ds temp,arg1,temp ; 8th divide step
537	addc retreg,retreg,retreg ; shift retreg with/into carry
538	ds temp,arg1,temp ; 9th divide step
539	addc retreg,retreg,retreg ; shift retreg with/into carry
540	ds temp,arg1,temp ; 10th divide step
541	addc retreg,retreg,retreg ; shift retreg with/into carry
542	ds temp,arg1,temp ; 11th divide step
543	addc retreg,retreg,retreg ; shift retreg with/into carry
544	ds temp,arg1,temp ; 12th divide step
545	addc retreg,retreg,retreg ; shift retreg with/into carry
546	ds temp,arg1,temp ; 13th divide step
547	addc retreg,retreg,retreg ; shift retreg with/into carry
548	ds temp,arg1,temp ; 14th divide step
549	addc retreg,retreg,retreg ; shift retreg with/into carry
550	ds temp,arg1,temp ; 15th divide step
551	addc retreg,retreg,retreg ; shift retreg with/into carry
552	ds temp,arg1,temp ; 16th divide step
553	addc retreg,retreg,retreg ; shift retreg with/into carry
554	ds temp,arg1,temp ; 17th divide step
555	addc retreg,retreg,retreg ; shift retreg with/into carry
556	ds temp,arg1,temp ; 18th divide step
557	addc retreg,retreg,retreg ; shift retreg with/into carry
558	ds temp,arg1,temp ; 19th divide step
559	addc retreg,retreg,retreg ; shift retreg with/into carry
560	ds temp,arg1,temp ; 20th divide step
561	addc retreg,retreg,retreg ; shift retreg with/into carry
562	ds temp,arg1,temp ; 21st divide step
563	addc retreg,retreg,retreg ; shift retreg with/into carry
564	ds temp,arg1,temp ; 22nd divide step
565	addc retreg,retreg,retreg ; shift retreg with/into carry
566	ds temp,arg1,temp ; 23rd divide step
567	addc retreg,retreg,retreg ; shift retreg with/into carry
568	ds temp,arg1,temp ; 24th divide step
569	addc retreg,retreg,retreg ; shift retreg with/into carry
570	ds temp,arg1,temp ; 25th divide step
571	addc retreg,retreg,retreg ; shift retreg with/into carry
572	ds temp,arg1,temp ; 26th divide step
573	addc retreg,retreg,retreg ; shift retreg with/into carry
574	ds temp,arg1,temp ; 27th divide step
575	addc retreg,retreg,retreg ; shift retreg with/into carry
576	ds temp,arg1,temp ; 28th divide step
577	addc retreg,retreg,retreg ; shift retreg with/into carry
578	ds temp,arg1,temp ; 29th divide step
579	addc retreg,retreg,retreg ; shift retreg with/into carry
580	ds temp,arg1,temp ; 30th divide step
581	addc retreg,retreg,retreg ; shift retreg with/into carry
582	ds temp,arg1,temp ; 31st divide step
583	addc retreg,retreg,retreg ; shift retreg with/into carry
584	ds temp,arg1,temp ; 32nd divide step,
585	bv 0(r31)
586	addc retreg,retreg,retreg ; shift last retreg bit into retreg
587	;_____________________________________________________________________________
588	; handle the cases where divisor is a small constant or has high bit on
589	special_divisor:
590	comib,> 0,arg1,big_divisor
591	nop
592	blr arg1,r0
593	nop
594	zero_divisor: ; this label is here to provide external visibility
595
596	addit,= 0,arg1,0 ; trap for zero dvr
597	nop
598	bv 0(r31) ; divisor == 1
599	copy arg0,retreg
600	bv 0(r31) ; divisor == 2
601	extru arg0,30,31,retreg
602	b,n $$divU_3 ; divisor == 3
603	nop
604	bv 0(r31) ; divisor == 4
605	extru arg0,29,30,retreg
606	b,n $$divU_5 ; divisor == 5
607	nop
608	b,n $$divU_6 ; divisor == 6
609	nop
610	b,n $$divU_7 ; divisor == 7
611	nop
612	bv 0(r31) ; divisor == 8
613	extru arg0,28,29,retreg
614	b,n $$divU_9 ; divisor == 9
615	nop
616	b,n $$divU_10 ; divisor == 10
617	nop
618	b normal ; divisor == 11
619	ds r0,temp,r0 ; set V-bit to 1
620	b,n $$divU_12 ; divisor == 12
621	nop
622	b normal ; divisor == 13
623	ds r0,temp,r0 ; set V-bit to 1
624	b,n $$divU_14 ; divisor == 14
625	nop
626	b,n $$divU_15 ; divisor == 15
627	nop
628	;_____________________________________________________________________________
629	; Handle the case where the high bit is on in the divisor.
630	; Compute: if( dividend>=divisor) quotient=1; else quotient=0;
631	; Note: dividend>==divisor iff dividend-divisor does not borrow
632	; and not borrow iff carry
633	big_divisor:
634	sub arg0,arg1,r0
635	bv 0(r31)
636	addc r0,r0,retreg
637	.exit
638	.procend
639	.end
640
641	t2: .EQU r1
642
643	; x2 .EQU arg0 ; r26
644	t1: .EQU arg1 ; r25
645
646	; x1 .EQU ret1 ; r29
647	;_____________________________________________________________________________
648
649	$$divide_by_constant:
650	.PROC
651	.CALLINFO millicode
652	.entry
653
654
655	.export $$divide_by_constant,millicode
656	; Provides a "nice" label for the code covered by the unwind descriptor
657	; for things like gprof.
658
659
660
661
662
663
664
665
666
667	$$divI_2:
668	.EXPORT $$divI_2,MILLICODE
669	COMCLR,>= arg0,0,0
670	ADDI 1,arg0,arg0
671	bv 0(r31)
672	EXTRS arg0,30,31,ret1
673
674
675
676	$$divI_4:
677	.EXPORT $$divI_4,MILLICODE
678	COMCLR,>= arg0,0,0
679	ADDI 3,arg0,arg0
680	bv 0(r31)
681	EXTRS arg0,29,30,ret1
682
683
684
685	$$divI_8:
686	.EXPORT $$divI_8,MILLICODE
687	COMCLR,>= arg0,0,0
688	ADDI 7,arg0,arg0
689	bv 0(r31)
690	EXTRS arg0,28,29,ret1
691
692
693	$$divI_16:
694	.EXPORT $$divI_16,MILLICODE
695	COMCLR,>= arg0,0,0
696	ADDI 15,arg0,arg0
697	bv 0(r31)
698	EXTRS arg0,27,28,ret1
699
700
701
702
703
704
705
706
707
708
709
710	$$divI_3:
711	.EXPORT $$divI_3,MILLICODE
712	COMB,<,N arg0,0,$neg3
713
714	ADDI 1,arg0,arg0
715	EXTRU arg0,1,2,ret1
716	SH2ADD arg0,arg0,arg0
717	B $pos
718	ADDC ret1,0,ret1
719
720	$neg3:
721	SUBI 1,arg0,arg0
722	EXTRU arg0,1,2,ret1
723	SH2ADD arg0,arg0,arg0
724	B $neg
725	ADDC ret1,0,ret1
726
727	$$divU_3:
728	.EXPORT $$divU_3,MILLICODE
729	ADDI 1,arg0,arg0
730	ADDC 0,0,ret1
731	SHD ret1,arg0,30,t1
732	SH2ADD arg0,arg0,arg0
733	B $pos
734	ADDC ret1,t1,ret1
735
736
737
738	$$divI_5:
739	.EXPORT $$divI_5,MILLICODE
740	COMB,<,N arg0,0,$neg5
741	ADDI 3,arg0,t1
742	SH1ADD arg0,t1,arg0
743	B $pos
744	ADDC 0,0,ret1
745
746	$neg5:
747	SUB 0,arg0,arg0
748	ADDI 1,arg0,arg0
749	SHD 0,arg0,31,ret1
750	SH1ADD arg0,arg0,arg0
751	B $neg
752	ADDC ret1,0,ret1
753
754	$$divU_5:
755	.EXPORT $$divU_5,MILLICODE
756	ADDI 1,arg0,arg0
757	ADDC 0,0,ret1
758	SHD ret1,arg0,31,t1
759	SH1ADD arg0,arg0,arg0
760	B $pos
761	ADDC t1,ret1,ret1
762
763
764	$$divI_6:
765	.EXPORT $$divI_6,MILLICODE
766	COMB,<,N arg0,0,$neg6
767	EXTRU arg0,30,31,arg0
768	ADDI 5,arg0,t1
769	SH2ADD arg0,t1,arg0
770	B $pos
771	ADDC 0,0,ret1
772
773	$neg6:
774	SUBI 2,arg0,arg0
775
776
777	EXTRU arg0,30,31,arg0
778	SHD 0,arg0,30,ret1
779	SH2ADD arg0,arg0,arg0
780	B $neg
781	ADDC ret1,0,ret1
782
783	$$divU_6:
784	.EXPORT $$divU_6,MILLICODE
785	EXTRU arg0,30,31,arg0
786	ADDI 1,arg0,arg0
787	SHD 0,arg0,30,ret1
788	SH2ADD arg0,arg0,arg0
789	B $pos
790	ADDC ret1,0,ret1
791
792
793	$$divU_10:
794	.EXPORT $$divU_10,MILLICODE
795	EXTRU arg0,30,31,arg0
796	ADDI 3,arg0,t1
797	SH1ADD arg0,t1,arg0
798	ADDC 0,0,ret1
799	$pos:
800	SHD ret1,arg0,28,t1
801	SHD arg0,0,28,t2
802	ADD arg0,t2,arg0
803	ADDC ret1,t1,ret1
804	$pos_for_17:
805	SHD ret1,arg0,24,t1
806	SHD arg0,0,24,t2
807	ADD arg0,t2,arg0
808	ADDC ret1,t1,ret1
809
810	SHD ret1,arg0,16,t1
811	SHD arg0,0,16,t2
812	ADD arg0,t2,arg0
813	bv 0(r31)
814	ADDC ret1,t1,ret1
815
816	$$divI_10:
817	.EXPORT $$divI_10,MILLICODE
818	COMB,< arg0,0,$neg10
819	COPY 0,ret1
820	EXTRU arg0,30,31,arg0
821	ADDIB,TR 1,arg0,$pos
822	SH1ADD arg0,arg0,arg0
823
824	$neg10:
825	SUBI 2,arg0,arg0
826
827
828	EXTRU arg0,30,31,arg0
829	SH1ADD arg0,arg0,arg0
830	$neg:
831	SHD ret1,arg0,28,t1
832	SHD arg0,0,28,t2
833	ADD arg0,t2,arg0
834	ADDC ret1,t1,ret1
835	$neg_for_17:
836	SHD ret1,arg0,24,t1
837	SHD arg0,0,24,t2
838	ADD arg0,t2,arg0
839	ADDC ret1,t1,ret1
840
841	SHD ret1,arg0,16,t1
842	SHD arg0,0,16,t2
843	ADD arg0,t2,arg0
844	ADDC ret1,t1,ret1
845	bv 0(r31)
846	SUB 0,ret1,ret1
847
848
849	$$divI_12:
850	.EXPORT $$divI_12,MILLICODE
851	COMB,< arg0,0,$neg12
852	COPY 0,ret1
853	EXTRU arg0,29,30,arg0
854	ADDIB,TR 1,arg0,$pos
855	SH2ADD arg0,arg0,arg0
856
857	$neg12:
858	SUBI 4,arg0,arg0
859
860
861	EXTRU arg0,29,30,arg0
862	B $neg
863	SH2ADD arg0,arg0,arg0
864
865	$$divU_12:
866	.EXPORT $$divU_12,MILLICODE
867	EXTRU arg0,29,30,arg0
868	ADDI 5,arg0,t1
869	SH2ADD arg0,t1,arg0
870	B $pos
871	ADDC 0,0,ret1
872
873
874	$$divI_15:
875	.EXPORT $$divI_15,MILLICODE
876	COMB,< arg0,0,$neg15
877	COPY 0,ret1
878	ADDIB,TR 1,arg0,$pos+4
879	SHD ret1,arg0,28,t1
880
881	$neg15:
882	B $neg
883	SUBI 1,arg0,arg0
884
885	$$divU_15:
886	.EXPORT $$divU_15,MILLICODE
887	ADDI 1,arg0,arg0
888	B $pos
889	ADDC 0,0,ret1
890
891
892	$$divI_17:
893	.EXPORT $$divI_17,MILLICODE
894	COMB,<,N arg0,0,$neg17
895	ADDI 1,arg0,arg0
896	SHD 0,arg0,28,t1
897	SHD arg0,0,28,t2
898	SUB t2,arg0,arg0
899	B $pos_for_17
900	SUBB t1,0,ret1
901
902	$neg17:
903	SUBI 1,arg0,arg0
904	SHD 0,arg0,28,t1
905	SHD arg0,0,28,t2
906	SUB t2,arg0,arg0
907	B $neg_for_17
908	SUBB t1,0,ret1
909
910	$$divU_17:
911	.EXPORT $$divU_17,MILLICODE
912	ADDI 1,arg0,arg0
913	ADDC 0,0,ret1
914	SHD ret1,arg0,28,t1
915	$u17:
916	SHD arg0,0,28,t2
917	SUB t2,arg0,arg0
918	B $pos_for_17
919	SUBB t1,ret1,ret1
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956	$$divI_7:
957	.EXPORT $$divI_7,MILLICODE
958	COMB,<,N arg0,0,$neg7
959	$7:
960	ADDI 1,arg0,arg0
961	SHD 0,arg0,29,ret1
962	SH3ADD arg0,arg0,arg0
963	ADDC ret1,0,ret1
964	$pos7:
965	SHD ret1,arg0,26,t1
966	SHD arg0,0,26,t2
967	ADD arg0,t2,arg0
968	ADDC ret1,t1,ret1
969
970	SHD ret1,arg0,20,t1
971	SHD arg0,0,20,t2
972	ADD arg0,t2,arg0
973	ADDC ret1,t1,t1
974
975
976
977	COPY 0,ret1
978	SHD,= t1,arg0,24,t1
979	$1:
980	ADDB,TR t1,ret1,$2
981	EXTRU arg0,31,24,arg0
982
983	bv,n 0(r31)
984
985	$2:
986	ADDB,TR t1,arg0,$1
987	EXTRU,= arg0,7,8,t1
988
989	$neg7:
990	SUBI 1,arg0,arg0
991	$8:
992	SHD 0,arg0,29,ret1
993	SH3ADD arg0,arg0,arg0
994	ADDC ret1,0,ret1
995
996	$neg7_shift:
997	SHD ret1,arg0,26,t1
998	SHD arg0,0,26,t2
999	ADD arg0,t2,arg0
1000	ADDC ret1,t1,ret1
1001
1002	SHD ret1,arg0,20,t1
1003	SHD arg0,0,20,t2
1004	ADD arg0,t2,arg0
1005	ADDC ret1,t1,t1
1006
1007
1008
1009	COPY 0,ret1
1010	SHD,= t1,arg0,24,t1
1011	$3:
1012	ADDB,TR t1,ret1,$4
1013	EXTRU arg0,31,24,arg0
1014
1015	bv 0(r31)
1016	SUB 0,ret1,ret1
1017
1018	$4:
1019	ADDB,TR t1,arg0,$3
1020	EXTRU,= arg0,7,8,t1
1021
1022	$$divU_7:
1023	.EXPORT $$divU_7,MILLICODE
1024	ADDI 1,arg0,arg0
1025	ADDC 0,0,ret1
1026	SHD ret1,arg0,29,t1
1027	SH3ADD arg0,arg0,arg0
1028	B $pos7
1029	ADDC t1,ret1,ret1
1030
1031
1032	$$divI_9:
1033	.EXPORT $$divI_9,MILLICODE
1034	COMB,<,N arg0,0,$neg9
1035	ADDI 1,arg0,arg0
1036	SHD 0,arg0,29,t1
1037	SHD arg0,0,29,t2
1038	SUB t2,arg0,arg0
1039	B $pos7
1040	SUBB t1,0,ret1
1041
1042	$neg9:
1043	SUBI 1,arg0,arg0
1044	SHD 0,arg0,29,t1
1045	SHD arg0,0,29,t2
1046	SUB t2,arg0,arg0
1047	B $neg7_shift
1048	SUBB t1,0,ret1
1049
1050	$$divU_9:
1051	.EXPORT $$divU_9,MILLICODE
1052	ADDI 1,arg0,arg0
1053	ADDC 0,0,ret1
1054	SHD ret1,arg0,29,t1
1055	SHD arg0,0,29,t2
1056	SUB t2,arg0,arg0
1057	B $pos7
1058	SUBB t1,ret1,ret1
1059
1060
1061	$$divI_14:
1062	.EXPORT $$divI_14,MILLICODE
1063	COMB,<,N arg0,0,$neg14
1064	$$divU_14:
1065	.EXPORT $$divU_14,MILLICODE
1066	B $7
1067	EXTRU arg0,30,31,arg0
1068
1069	$neg14:
1070	SUBI 2,arg0,arg0
1071	B $8
1072	EXTRU arg0,30,31,arg0
1073
1074	.exit
1075	.PROCEND
1076	.END
1077
1078	rmndr: .EQU ret1 ; r29
1079
1080
1081	.export $$remU,millicode
1082	$$remU:
1083	.proc
1084	.callinfo millicode
1085	.entry
1086
1087	comib,>=,n 0,arg1,special_case
1088	sub r0,arg1,rmndr ; clear carry, negate the divisor
1089	ds r0,rmndr,r0 ; set V-bit to 1
1090	add arg0,arg0,temp ; shift msb bit into carry
1091	ds r0,arg1,rmndr ; 1st divide step, if no carry
1092	addc temp,temp,temp ; shift temp with/into carry
1093	ds rmndr,arg1,rmndr ; 2nd divide step
1094	addc temp,temp,temp ; shift temp with/into carry
1095	ds rmndr,arg1,rmndr ; 3rd divide step
1096	addc temp,temp,temp ; shift temp with/into carry
1097	ds rmndr,arg1,rmndr ; 4th divide step
1098	addc temp,temp,temp ; shift temp with/into carry
1099	ds rmndr,arg1,rmndr ; 5th divide step
1100	addc temp,temp,temp ; shift temp with/into carry
1101	ds rmndr,arg1,rmndr ; 6th divide step
1102	addc temp,temp,temp ; shift temp with/into carry
1103	ds rmndr,arg1,rmndr ; 7th divide step
1104	addc temp,temp,temp ; shift temp with/into carry
1105	ds rmndr,arg1,rmndr ; 8th divide step
1106	addc temp,temp,temp ; shift temp with/into carry
1107	ds rmndr,arg1,rmndr ; 9th divide step
1108	addc temp,temp,temp ; shift temp with/into carry
1109	ds rmndr,arg1,rmndr ; 10th divide step
1110	addc temp,temp,temp ; shift temp with/into carry
1111	ds rmndr,arg1,rmndr ; 11th divide step
1112	addc temp,temp,temp ; shift temp with/into carry
1113	ds rmndr,arg1,rmndr ; 12th divide step
1114	addc temp,temp,temp ; shift temp with/into carry
1115	ds rmndr,arg1,rmndr ; 13th divide step
1116	addc temp,temp,temp ; shift temp with/into carry
1117	ds rmndr,arg1,rmndr ; 14th divide step
1118	addc temp,temp,temp ; shift temp with/into carry
1119	ds rmndr,arg1,rmndr ; 15th divide step
1120	addc temp,temp,temp ; shift temp with/into carry
1121	ds rmndr,arg1,rmndr ; 16th divide step
1122	addc temp,temp,temp ; shift temp with/into carry
1123	ds rmndr,arg1,rmndr ; 17th divide step
1124	addc temp,temp,temp ; shift temp with/into carry
1125	ds rmndr,arg1,rmndr ; 18th divide step
1126	addc temp,temp,temp ; shift temp with/into carry
1127	ds rmndr,arg1,rmndr ; 19th divide step
1128	addc temp,temp,temp ; shift temp with/into carry
1129	ds rmndr,arg1,rmndr ; 20th divide step
1130	addc temp,temp,temp ; shift temp with/into carry
1131	ds rmndr,arg1,rmndr ; 21st divide step
1132	addc temp,temp,temp ; shift temp with/into carry
1133	ds rmndr,arg1,rmndr ; 22nd divide step
1134	addc temp,temp,temp ; shift temp with/into carry
1135	ds rmndr,arg1,rmndr ; 23rd divide step
1136	addc temp,temp,temp ; shift temp with/into carry
1137	ds rmndr,arg1,rmndr ; 24th divide step
1138	addc temp,temp,temp ; shift temp with/into carry
1139	ds rmndr,arg1,rmndr ; 25th divide step
1140	addc temp,temp,temp ; shift temp with/into carry
1141	ds rmndr,arg1,rmndr ; 26th divide step
1142	addc temp,temp,temp ; shift temp with/into carry
1143	ds rmndr,arg1,rmndr ; 27th divide step
1144	addc temp,temp,temp ; shift temp with/into carry
1145	ds rmndr,arg1,rmndr ; 28th divide step
1146	addc temp,temp,temp ; shift temp with/into carry
1147	ds rmndr,arg1,rmndr ; 29th divide step
1148	addc temp,temp,temp ; shift temp with/into carry
1149	ds rmndr,arg1,rmndr ; 30th divide step
1150	addc temp,temp,temp ; shift temp with/into carry
1151	ds rmndr,arg1,rmndr ; 31st divide step
1152	addc temp,temp,temp ; shift temp with/into carry
1153	ds rmndr,arg1,rmndr ; 32nd divide step,
1154	comiclr,<= 0,rmndr,r0
1155	add rmndr,arg1,rmndr ; correction
1156	; .exit
1157	bv,n 0(r31)
1158	nop
1159	; Putting >= on the last DS and deleting COMICLR does not work!
1160	;_____________________________________________________________________________
1161	special_case:
1162	addit,= 0,arg1,r0 ; trap on div by zero
1163	sub,>>= arg0,arg1,rmndr
1164	copy arg0,rmndr
1165	bv,n 0(r31)
1166	nop
1167	.exit
1168	.procend
1169	.end
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207	; Use bv 0(r31) and bv,n 0(r31) instead.
1208	; #define return bv 0(%mrp)
1209	; #define return_n bv,n 0(%mrp)
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237	#if 0
1238	.subspa $MILLICODE$
1239	#else
1240	.text
1241	#endif
1242	.align 16
1243	$$mulI:
1244
1245	.proc
1246	.callinfo millicode
1247	.entry
1248	.export $$mulI, millicode
1249	combt,<<= %r25,%r26,l4 ; swap args if unsigned %r25>%r26
1250	copy 0,%r29 ; zero out the result
1251	xor %r26,%r25,%r26 ; swap %r26 & %r25 using the
1252	xor %r26,%r25,%r25 ; old xor trick
1253	xor %r26,%r25,%r26
1254	l4: combt,<= 0,%r26,l3 ; if %r26>=0 then proceed like unsigned
1255
1256	zdep %r25,30,8,%r1 ; %r1 = (%r25&0xff)<<1 *********
1257	sub,> 0,%r25,%r1 ; otherwise negate both and
1258	combt,<=,n %r26,%r1,l2 ; swap back if \|%r26\|<\|%r25\|
1259	sub 0,%r26,%r25
1260	movb,tr,n %r1,%r26,l2 ; 10th inst.
1261
1262	l0: add %r29,%r1,%r29 ; add in this partial product
1263
1264	l1: zdep %r26,23,24,%r26 ; %r26 <<= 8 ******************
1265
1266	l2: zdep %r25,30,8,%r1 ; %r1 = (%r25&0xff)<<1 *********
1267
1268	l3: blr %r1,0 ; case on these 8 bits ******
1269
1270	extru %r25,23,24,%r25 ; %r25 >>= 8 ******************
1271
1272	;16 insts before this.
1273	; %r26 <<= 8 **************************
1274	x0: comb,<> %r25,0,l2 ! zdep %r26,23,24,%r26 ! bv,n 0(r31) ! nop
1275
1276	x1: comb,<> %r25,0,l1 ! add %r29,%r26,%r29 ! bv,n 0(r31) ! nop
1277
1278	x2: comb,<> %r25,0,l1 ! sh1add %r26,%r29,%r29 ! bv,n 0(r31) ! nop
1279
1280	x3: comb,<> %r25,0,l0 ! sh1add %r26,%r26,%r1 ! bv 0(r31) ! add %r29,%r1,%r29
1281
1282	x4: comb,<> %r25,0,l1 ! sh2add %r26,%r29,%r29 ! bv,n 0(r31) ! nop
1283
1284	x5: comb,<> %r25,0,l0 ! sh2add %r26,%r26,%r1 ! bv 0(r31) ! add %r29,%r1,%r29
1285
1286	x6: sh1add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh1add %r1,%r29,%r29 ! bv,n 0(r31)
1287
1288	x7: sh1add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh2add %r26,%r29,%r29 ! b,n ret_t0
1289
1290	x8: comb,<> %r25,0,l1 ! sh3add %r26,%r29,%r29 ! bv,n 0(r31) ! nop
1291
1292	x9: comb,<> %r25,0,l0 ! sh3add %r26,%r26,%r1 ! bv 0(r31) ! add %r29,%r1,%r29
1293
1294	x10: sh2add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh1add %r1,%r29,%r29 ! bv,n 0(r31)
1295
1296	x11: sh1add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh3add %r26,%r29,%r29 ! b,n ret_t0
1297
1298	x12: sh1add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh2add %r1,%r29,%r29 ! bv,n 0(r31)
1299
1300	x13: sh2add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh3add %r26,%r29,%r29 ! b,n ret_t0
1301
1302	x14: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1303
1304	x15: sh2add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh1add %r1,%r1,%r1 ! b,n ret_t0
1305
1306	x16: zdep %r26,27,28,%r1 ! comb,<> %r25,0,l1 ! add %r29,%r1,%r29 ! bv,n 0(r31)
1307
1308	x17: sh3add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh3add %r26,%r1,%r1 ! b,n ret_t0
1309
1310	x18: sh3add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh1add %r1,%r29,%r29 ! bv,n 0(r31)
1311
1312	x19: sh3add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh1add %r1,%r26,%r1 ! b,n ret_t0
1313
1314	x20: sh2add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh2add %r1,%r29,%r29 ! bv,n 0(r31)
1315
1316	x21: sh2add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh2add %r1,%r26,%r1 ! b,n ret_t0
1317
1318	x22: sh2add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1319
1320	x23: sh2add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
1321
1322	x24: sh1add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh3add %r1,%r29,%r29 ! bv,n 0(r31)
1323
1324	x25: sh2add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh2add %r1,%r1,%r1 ! b,n ret_t0
1325
1326	x26: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1327
1328	x27: sh1add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh3add %r1,%r1,%r1 ! b,n ret_t0
1329
1330	x28: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
1331
1332	x29: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
1333
1334	x30: sh2add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1335
1336	x31: zdep %r26,26,27,%r1 ! comb,<> %r25,0,l0 ! sub %r1,%r26,%r1 ! b,n ret_t0
1337
1338	x32: zdep %r26,26,27,%r1 ! comb,<> %r25,0,l1 ! add %r29,%r1,%r29 ! bv,n 0(r31)
1339
1340	x33: sh3add %r26,0,%r1 ! comb,<> %r25,0,l0 ! sh2add %r1,%r26,%r1 ! b,n ret_t0
1341
1342	x34: zdep %r26,27,28,%r1 ! add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1343
1344	x35: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh3add %r26,%r1,%r1
1345
1346	x36: sh3add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh2add %r1,%r29,%r29 ! bv,n 0(r31)
1347
1348	x37: sh3add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh2add %r1,%r26,%r1 ! b,n ret_t0
1349
1350	x38: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1351
1352	x39: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
1353
1354	x40: sh2add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh3add %r1,%r29,%r29 ! bv,n 0(r31)
1355
1356	x41: sh2add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh3add %r1,%r26,%r1 ! b,n ret_t0
1357
1358	x42: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1359
1360	x43: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
1361
1362	x44: sh2add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
1363
1364	x45: sh3add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh2add %r1,%r1,%r1 ! b,n ret_t0
1365
1366	x46: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! add %r1,%r26,%r1
1367
1368	x47: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh1add %r26,%r1,%r1
1369
1370	x48: sh1add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! zdep %r1,27,28,%r1 ! b,n ret_t0
1371
1372	x49: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh2add %r26,%r1,%r1
1373
1374	x50: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1375
1376	x51: sh3add %r26,%r26,%r1 ! sh3add %r26,%r1,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
1377
1378	x52: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
1379
1380	x53: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
1381
1382	x54: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1383
1384	x55: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
1385
1386	x56: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
1387
1388	x57: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
1389
1390	x58: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0 ! sh2add %r1,%r26,%r1
1391
1392	x59: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t02a0 ! sh1add %r1,%r1,%r1
1393
1394	x60: sh2add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
1395
1396	x61: sh2add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
1397
1398	x62: zdep %r26,26,27,%r1 ! sub %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1399
1400	x63: zdep %r26,25,26,%r1 ! comb,<> %r25,0,l0 ! sub %r1,%r26,%r1 ! b,n ret_t0
1401
1402	x64: zdep %r26,25,26,%r1 ! comb,<> %r25,0,l1 ! add %r29,%r1,%r29 ! bv,n 0(r31)
1403
1404	x65: sh3add %r26,0,%r1 ! comb,<> %r25,0,l0 ! sh3add %r1,%r26,%r1 ! b,n ret_t0
1405
1406	x66: zdep %r26,26,27,%r1 ! add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1407
1408	x67: sh3add %r26,0,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
1409
1410	x68: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
1411
1412	x69: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
1413
1414	x70: zdep %r26,25,26,%r1 ! sh2add %r26,%r1,%r1 ! b e_t0 ! sh1add %r26,%r1,%r1
1415
1416	x71: sh3add %r26,%r26,%r1 ! sh3add %r1,0,%r1 ! b e_t0 ! sub %r1,%r26,%r1
1417
1418	x72: sh3add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh3add %r1,%r29,%r29 ! bv,n 0(r31)
1419
1420	x73: sh3add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_shift ! add %r29,%r1,%r29
1421
1422	x74: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1423
1424	x75: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
1425
1426	x76: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
1427
1428	x77: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
1429
1430	x78: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r26,%r1
1431
1432	x79: zdep %r26,27,28,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sub %r1,%r26,%r1
1433
1434	x80: zdep %r26,27,28,%r1 ! sh2add %r1,%r1,%r1 ! b e_shift ! add %r29,%r1,%r29
1435
1436	x81: sh3add %r26,%r26,%r1 ! sh3add %r1,%r1,%r1 ! b e_shift ! add %r29,%r1,%r29
1437
1438	x82: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1439
1440	x83: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
1441
1442	x84: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
1443
1444	x85: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
1445
1446	x86: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r26,%r1
1447
1448	x87: sh3add %r26,%r26,%r1 ! sh3add %r1,%r1,%r1 ! b e_t02a0 ! sh2add %r26,%r1,%r1
1449
1450	x88: sh2add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
1451
1452	x89: sh2add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
1453
1454	x90: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1455
1456	x91: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
1457
1458	x92: sh2add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_4t0 ! sh1add %r1,%r26,%r1
1459
1460	x93: zdep %r26,26,27,%r1 ! sub %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
1461
1462	x94: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_2t0 ! sh1add %r26,%r1,%r1
1463
1464	x95: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
1465
1466	x96: sh3add %r26,0,%r1 ! sh1add %r1,%r1,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
1467
1468	x97: sh3add %r26,0,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
1469
1470	x98: zdep %r26,26,27,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh1add %r26,%r1,%r1
1471
1472	x99: sh3add %r26,0,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
1473
1474	x100: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
1475
1476	x101: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
1477
1478	x102: zdep %r26,26,27,%r1 ! sh1add %r26,%r1,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
1479
1480	x103: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t02a0 ! sh2add %r1,%r26,%r1
1481
1482	x104: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
1483
1484	x105: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
1485
1486	x106: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0 ! sh2add %r1,%r26,%r1
1487
1488	x107: sh3add %r26,%r26,%r1 ! sh2add %r26,%r1,%r1 ! b e_t02a0 ! sh3add %r1,%r26,%r1
1489
1490	x108: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
1491
1492	x109: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
1493
1494	x110: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_2t0 ! sh1add %r1,%r26,%r1
1495
1496	x111: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
1497
1498	x112: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! zdep %r1,27,28,%r1
1499
1500	x113: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t02a0 ! sh1add %r1,%r1,%r1
1501
1502	x114: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r1,%r1
1503
1504	x115: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0a0 ! sh1add %r1,%r1,%r1
1505
1506	x116: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_4t0 ! sh2add %r1,%r26,%r1
1507
1508	x117: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh3add %r1,%r1,%r1
1509
1510	x118: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0a0 ! sh3add %r1,%r1,%r1
1511
1512	x119: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t02a0 ! sh3add %r1,%r1,%r1
1513
1514	x120: sh2add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
1515
1516	x121: sh2add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
1517
1518	x122: sh2add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_2t0 ! sh2add %r1,%r26,%r1
1519
1520	x123: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
1521
1522	x124: zdep %r26,26,27,%r1 ! sub %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
1523
1524	x125: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
1525
1526	x126: zdep %r26,25,26,%r1 ! sub %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1527
1528	x127: zdep %r26,24,25,%r1 ! comb,<> %r25,0,l0 ! sub %r1,%r26,%r1 ! b,n ret_t0
1529
1530	x128: zdep %r26,24,25,%r1 ! comb,<> %r25,0,l1 ! add %r29,%r1,%r29 ! bv,n 0(r31)
1531
1532	x129: zdep %r26,24,25,%r1 ! comb,<> %r25,0,l0 ! add %r1,%r26,%r1 ! b,n ret_t0
1533
1534	x130: zdep %r26,25,26,%r1 ! add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1535
1536	x131: sh3add %r26,0,%r1 ! sh3add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
1537
1538	x132: sh3add %r26,0,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
1539
1540	x133: sh3add %r26,0,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
1541
1542	x134: sh3add %r26,0,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r26,%r1
1543
1544	x135: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
1545
1546	x136: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
1547
1548	x137: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
1549
1550	x138: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0 ! sh2add %r1,%r26,%r1
1551
1552	x139: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0a0 ! sh2add %r1,%r26,%r1
1553
1554	x140: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_4t0 ! sh2add %r1,%r1,%r1
1555
1556	x141: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_4t0a0 ! sh1add %r1,%r26,%r1
1557
1558	x142: sh3add %r26,%r26,%r1 ! sh3add %r1,0,%r1 ! b e_2t0 ! sub %r1,%r26,%r1
1559
1560	x143: zdep %r26,27,28,%r1 ! sh3add %r1,%r1,%r1 ! b e_t0 ! sub %r1,%r26,%r1
1561
1562	x144: sh3add %r26,%r26,%r1 ! sh3add %r1,0,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1563
1564	x145: sh3add %r26,%r26,%r1 ! sh3add %r1,0,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
1565
1566	x146: sh3add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1567
1568	x147: sh3add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
1569
1570	x148: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
1571
1572	x149: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
1573
1574	x150: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r26,%r1
1575
1576	x151: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0a0 ! sh1add %r1,%r26,%r1
1577
1578	x152: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
1579
1580	x153: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
1581
1582	x154: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0 ! sh2add %r1,%r26,%r1
1583
1584	x155: zdep %r26,26,27,%r1 ! sub %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
1585
1586	x156: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_4t0 ! sh1add %r1,%r26,%r1
1587
1588	x157: zdep %r26,26,27,%r1 ! sub %r1,%r26,%r1 ! b e_t02a0 ! sh2add %r1,%r1,%r1
1589
1590	x158: zdep %r26,27,28,%r1 ! sh2add %r1,%r1,%r1 ! b e_2t0 ! sub %r1,%r26,%r1
1591
1592	x159: zdep %r26,26,27,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sub %r1,%r26,%r1
1593
1594	x160: sh2add %r26,%r26,%r1 ! sh2add %r1,0,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
1595
1596	x161: sh3add %r26,0,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
1597
1598	x162: sh3add %r26,%r26,%r1 ! sh3add %r1,%r1,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1599
1600	x163: sh3add %r26,%r26,%r1 ! sh3add %r1,%r1,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
1601
1602	x164: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
1603
1604	x165: sh3add %r26,0,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
1605
1606	x166: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r26,%r1
1607
1608	x167: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_2t0a0 ! sh1add %r1,%r26,%r1
1609
1610	x168: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
1611
1612	x169: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
1613
1614	x170: zdep %r26,26,27,%r1 ! sh1add %r26,%r1,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
1615
1616	x171: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh3add %r1,%r1,%r1
1617
1618	x172: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_4t0 ! sh1add %r1,%r26,%r1
1619
1620	x173: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t02a0 ! sh3add %r1,%r1,%r1
1621
1622	x174: zdep %r26,26,27,%r1 ! sh1add %r26,%r1,%r1 ! b e_t04a0 ! sh2add %r1,%r1,%r1
1623
1624	x175: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_5t0 ! sh1add %r1,%r26,%r1
1625
1626	x176: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_8t0 ! add %r1,%r26,%r1
1627
1628	x177: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_8t0a0 ! add %r1,%r26,%r1
1629
1630	x178: sh2add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0 ! sh3add %r1,%r26,%r1
1631
1632	x179: sh2add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0a0 ! sh3add %r1,%r26,%r1
1633
1634	x180: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
1635
1636	x181: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
1637
1638	x182: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_2t0 ! sh1add %r1,%r26,%r1
1639
1640	x183: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_2t0a0 ! sh1add %r1,%r26,%r1
1641
1642	x184: sh2add %r26,%r26,%r1 ! sh3add %r1,%r1,%r1 ! b e_4t0 ! add %r1,%r26,%r1
1643
1644	x185: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
1645
1646	x186: zdep %r26,26,27,%r1 ! sub %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r1,%r1
1647
1648	x187: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t02a0 ! sh2add %r1,%r1,%r1
1649
1650	x188: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_4t0 ! sh1add %r26,%r1,%r1
1651
1652	x189: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh3add %r1,%r1,%r1
1653
1654	x190: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0 ! sh2add %r1,%r1,%r1
1655
1656	x191: zdep %r26,25,26,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sub %r1,%r26,%r1
1657
1658	x192: sh3add %r26,0,%r1 ! sh1add %r1,%r1,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
1659
1660	x193: sh3add %r26,0,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
1661
1662	x194: sh3add %r26,0,%r1 ! sh1add %r1,%r1,%r1 ! b e_2t0 ! sh2add %r1,%r26,%r1
1663
1664	x195: sh3add %r26,0,%r1 ! sh3add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
1665
1666	x196: sh3add %r26,0,%r1 ! sh1add %r1,%r1,%r1 ! b e_4t0 ! sh1add %r1,%r26,%r1
1667
1668	x197: sh3add %r26,0,%r1 ! sh1add %r1,%r1,%r1 ! b e_4t0a0 ! sh1add %r1,%r26,%r1
1669
1670	x198: zdep %r26,25,26,%r1 ! sh1add %r26,%r1,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
1671
1672	x199: sh3add %r26,0,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0a0 ! sh1add %r1,%r1,%r1
1673
1674	x200: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
1675
1676	x201: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
1677
1678	x202: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_2t0 ! sh2add %r1,%r26,%r1
1679
1680	x203: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_2t0a0 ! sh2add %r1,%r26,%r1
1681
1682	x204: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_4t0 ! sh1add %r1,%r1,%r1
1683
1684	x205: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
1685
1686	x206: zdep %r26,25,26,%r1 ! sh2add %r26,%r1,%r1 ! b e_t02a0 ! sh1add %r1,%r1,%r1
1687
1688	x207: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_3t0 ! sh2add %r1,%r26,%r1
1689
1690	x208: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_8t0 ! add %r1,%r26,%r1
1691
1692	x209: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_8t0a0 ! add %r1,%r26,%r1
1693
1694	x210: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0 ! sh2add %r1,%r1,%r1
1695
1696	x211: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0a0 ! sh2add %r1,%r1,%r1
1697
1698	x212: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_4t0 ! sh2add %r1,%r26,%r1
1699
1700	x213: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_4t0a0 ! sh2add %r1,%r26,%r1
1701
1702	x214: sh3add %r26,%r26,%r1 ! sh2add %r26,%r1,%r1 ! b e2t04a0 ! sh3add %r1,%r26,%r1
1703
1704	x215: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_5t0 ! sh1add %r1,%r26,%r1
1705
1706	x216: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
1707
1708	x217: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
1709
1710	x218: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_2t0 ! sh2add %r1,%r26,%r1
1711
1712	x219: sh3add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
1713
1714	x220: sh1add %r26,%r26,%r1 ! sh3add %r1,%r1,%r1 ! b e_4t0 ! sh1add %r1,%r26,%r1
1715
1716	x221: sh1add %r26,%r26,%r1 ! sh3add %r1,%r1,%r1 ! b e_4t0a0 ! sh1add %r1,%r26,%r1
1717
1718	x222: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r1,%r1
1719
1720	x223: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0a0 ! sh1add %r1,%r1,%r1
1721
1722	x224: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_8t0 ! add %r1,%r26,%r1
1723
1724	x225: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
1725
1726	x226: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t02a0 ! zdep %r1,26,27,%r1
1727
1728	x227: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t02a0 ! sh2add %r1,%r1,%r1
1729
1730	x228: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_4t0 ! sh1add %r1,%r1,%r1
1731
1732	x229: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_4t0a0 ! sh1add %r1,%r1,%r1
1733
1734	x230: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_5t0 ! add %r1,%r26,%r1
1735
1736	x231: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_3t0 ! sh2add %r1,%r26,%r1
1737
1738	x232: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_8t0 ! sh2add %r1,%r26,%r1
1739
1740	x233: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_8t0a0 ! sh2add %r1,%r26,%r1
1741
1742	x234: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0 ! sh3add %r1,%r1,%r1
1743
1744	x235: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0a0 ! sh3add %r1,%r1,%r1
1745
1746	x236: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e4t08a0 ! sh1add %r1,%r1,%r1
1747
1748	x237: zdep %r26,27,28,%r1 ! sh2add %r1,%r1,%r1 ! b e_3t0 ! sub %r1,%r26,%r1
1749
1750	x238: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e2t04a0 ! sh3add %r1,%r1,%r1
1751
1752	x239: zdep %r26,27,28,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0ma0 ! sh1add %r1,%r1,%r1
1753
1754	x240: sh3add %r26,%r26,%r1 ! add %r1,%r26,%r1 ! b e_8t0 ! sh1add %r1,%r1,%r1
1755
1756	x241: sh3add %r26,%r26,%r1 ! add %r1,%r26,%r1 ! b e_8t0a0 ! sh1add %r1,%r1,%r1
1757
1758	x242: sh2add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_2t0 ! sh3add %r1,%r26,%r1
1759
1760	x243: sh3add %r26,%r26,%r1 ! sh3add %r1,%r1,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
1761
1762	x244: sh2add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_4t0 ! sh2add %r1,%r26,%r1
1763
1764	x245: sh3add %r26,0,%r1 ! sh1add %r1,%r1,%r1 ! b e_5t0 ! sh1add %r1,%r26,%r1
1765
1766	x246: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r1,%r1
1767
1768	x247: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_2t0a0 ! sh1add %r1,%r1,%r1
1769
1770	x248: zdep %r26,26,27,%r1 ! sub %r1,%r26,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
1771
1772	x249: zdep %r26,26,27,%r1 ! sub %r1,%r26,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
1773
1774	x250: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_2t0 ! sh2add %r1,%r1,%r1
1775
1776	x251: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_2t0a0 ! sh2add %r1,%r1,%r1
1777
1778	x252: zdep %r26,25,26,%r1 ! sub %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
1779
1780	x253: zdep %r26,25,26,%r1 ! sub %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
1781
1782	x254: zdep %r26,24,25,%r1 ! sub %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
1783
1784	x255: zdep %r26,23,24,%r1 ! comb,<> %r25,0,l0 ! sub %r1,%r26,%r1 ! b,n ret_t0
1785
1786	;1040 insts before this.
1787	ret_t0: bv 0(r31)
1788
1789	e_t0: add %r29,%r1,%r29
1790
1791	e_shift: comb,<> %r25,0,l2
1792
1793	zdep %r26,23,24,%r26 ; %r26 <<= 8 ***********
1794	bv,n 0(r31)
1795	e_t0ma0: comb,<> %r25,0,l0
1796
1797	sub %r1,%r26,%r1
1798	bv 0(r31)
1799	add %r29,%r1,%r29
1800	e_t0a0: comb,<> %r25,0,l0
1801
1802	add %r1,%r26,%r1
1803	bv 0(r31)
1804	add %r29,%r1,%r29
1805	e_t02a0: comb,<> %r25,0,l0
1806
1807	sh1add %r26,%r1,%r1
1808	bv 0(r31)
1809	add %r29,%r1,%r29
1810	e_t04a0: comb,<> %r25,0,l0
1811
1812	sh2add %r26,%r1,%r1
1813	bv 0(r31)
1814	add %r29,%r1,%r29
1815	e_2t0: comb,<> %r25,0,l1
1816
1817	sh1add %r1,%r29,%r29
1818	bv,n 0(r31)
1819	e_2t0a0: comb,<> %r25,0,l0
1820
1821	sh1add %r1,%r26,%r1
1822	bv 0(r31)
1823	add %r29,%r1,%r29
1824	e2t04a0: sh1add %r26,%r1,%r1
1825
1826	comb,<> %r25,0,l1
1827	sh1add %r1,%r29,%r29
1828	bv,n 0(r31)
1829	e_3t0: comb,<> %r25,0,l0
1830
1831	sh1add %r1,%r1,%r1
1832	bv 0(r31)
1833	add %r29,%r1,%r29
1834	e_4t0: comb,<> %r25,0,l1
1835
1836	sh2add %r1,%r29,%r29
1837	bv,n 0(r31)
1838	e_4t0a0: comb,<> %r25,0,l0
1839
1840	sh2add %r1,%r26,%r1
1841	bv 0(r31)
1842	add %r29,%r1,%r29
1843	e4t08a0: sh1add %r26,%r1,%r1
1844
1845	comb,<> %r25,0,l1
1846	sh2add %r1,%r29,%r29
1847	bv,n 0(r31)
1848	e_5t0: comb,<> %r25,0,l0
1849
1850	sh2add %r1,%r1,%r1
1851	bv 0(r31)
1852	add %r29,%r1,%r29
1853	e_8t0: comb,<> %r25,0,l1
1854
1855	sh3add %r1,%r29,%r29
1856	bv,n 0(r31)
1857	e_8t0a0: comb,<> %r25,0,l0
1858
1859	sh3add %r1,%r26,%r1
1860	bv 0(r31)
1861	add %r29,%r1,%r29
1862
1863	.exit
1864	.procend
1865	.end
1866
1867	.import $$divI_2,millicode
1868	.import $$divI_3,millicode
1869	.import $$divI_4,millicode
1870	.import $$divI_5,millicode
1871	.import $$divI_6,millicode
1872	.import $$divI_7,millicode
1873	.import $$divI_8,millicode
1874	.import $$divI_9,millicode
1875	.import $$divI_10,millicode
1876	.import $$divI_12,millicode
1877	.import $$divI_14,millicode
1878	.import $$divI_15,millicode
1879	.export $$divI,millicode
1880	.export $$divoI,millicode
1881	$$divoI:
1882	.proc
1883	.callinfo millicode
1884	.entry
1885	comib,=,n -1,arg1,negative1 ; when divisor == -1
1886	$$divI:
1887	comib,>>=,n 15,arg1,small_divisor
1888	add,>= 0,arg0,retreg ; move dividend, if retreg < 0,
1889	normal1:
1890	sub 0,retreg,retreg ; make it positive
1891	sub 0,arg1,temp ; clear carry,
1892	; negate the divisor
1893	ds 0,temp,0 ; set V-bit to the comple-
1894	; ment of the divisor sign
1895	add retreg,retreg,retreg ; shift msb bit into carry
1896	ds r0,arg1,temp ; 1st divide step, if no carry
1897	addc retreg,retreg,retreg ; shift retreg with/into carry
1898	ds temp,arg1,temp ; 2nd divide step
1899	addc retreg,retreg,retreg ; shift retreg with/into carry
1900	ds temp,arg1,temp ; 3rd divide step
1901	addc retreg,retreg,retreg ; shift retreg with/into carry
1902	ds temp,arg1,temp ; 4th divide step
1903	addc retreg,retreg,retreg ; shift retreg with/into carry
1904	ds temp,arg1,temp ; 5th divide step
1905	addc retreg,retreg,retreg ; shift retreg with/into carry
1906	ds temp,arg1,temp ; 6th divide step
1907	addc retreg,retreg,retreg ; shift retreg with/into carry
1908	ds temp,arg1,temp ; 7th divide step
1909	addc retreg,retreg,retreg ; shift retreg with/into carry
1910	ds temp,arg1,temp ; 8th divide step
1911	addc retreg,retreg,retreg ; shift retreg with/into carry
1912	ds temp,arg1,temp ; 9th divide step
1913	addc retreg,retreg,retreg ; shift retreg with/into carry
1914	ds temp,arg1,temp ; 10th divide step
1915	addc retreg,retreg,retreg ; shift retreg with/into carry
1916	ds temp,arg1,temp ; 11th divide step
1917	addc retreg,retreg,retreg ; shift retreg with/into carry
1918	ds temp,arg1,temp ; 12th divide step
1919	addc retreg,retreg,retreg ; shift retreg with/into carry
1920	ds temp,arg1,temp ; 13th divide step
1921	addc retreg,retreg,retreg ; shift retreg with/into carry
1922	ds temp,arg1,temp ; 14th divide step
1923	addc retreg,retreg,retreg ; shift retreg with/into carry
1924	ds temp,arg1,temp ; 15th divide step
1925	addc retreg,retreg,retreg ; shift retreg with/into carry
1926	ds temp,arg1,temp ; 16th divide step
1927	addc retreg,retreg,retreg ; shift retreg with/into carry
1928	ds temp,arg1,temp ; 17th divide step
1929	addc retreg,retreg,retreg ; shift retreg with/into carry
1930	ds temp,arg1,temp ; 18th divide step
1931	addc retreg,retreg,retreg ; shift retreg with/into carry
1932	ds temp,arg1,temp ; 19th divide step
1933	addc retreg,retreg,retreg ; shift retreg with/into carry
1934	ds temp,arg1,temp ; 20th divide step
1935	addc retreg,retreg,retreg ; shift retreg with/into carry
1936	ds temp,arg1,temp ; 21st divide step
1937	addc retreg,retreg,retreg ; shift retreg with/into carry
1938	ds temp,arg1,temp ; 22nd divide step
1939	addc retreg,retreg,retreg ; shift retreg with/into carry
1940	ds temp,arg1,temp ; 23rd divide step
1941	addc retreg,retreg,retreg ; shift retreg with/into carry
1942	ds temp,arg1,temp ; 24th divide step
1943	addc retreg,retreg,retreg ; shift retreg with/into carry
1944	ds temp,arg1,temp ; 25th divide step
1945	addc retreg,retreg,retreg ; shift retreg with/into carry
1946	ds temp,arg1,temp ; 26th divide step
1947	addc retreg,retreg,retreg ; shift retreg with/into carry
1948	ds temp,arg1,temp ; 27th divide step
1949	addc retreg,retreg,retreg ; shift retreg with/into carry
1950	ds temp,arg1,temp ; 28th divide step
1951	addc retreg,retreg,retreg ; shift retreg with/into carry
1952	ds temp,arg1,temp ; 29th divide step
1953	addc retreg,retreg,retreg ; shift retreg with/into carry
1954	ds temp,arg1,temp ; 30th divide step
1955	addc retreg,retreg,retreg ; shift retreg with/into carry
1956	ds temp,arg1,temp ; 31st divide step
1957	addc retreg,retreg,retreg ; shift retreg with/into carry
1958	ds temp,arg1,temp ; 32nd divide step,
1959	addc retreg,retreg,retreg ; shift last retreg bit into retreg
1960	xor,>= arg0,arg1,0 ; get correct sign of quotient
1961	sub 0,retreg,retreg ; based on operand signs
1962	bv,n 0(r31)
1963	nop
1964	;______________________________________________________________________
1965	small_divisor:
1966	blr,n arg1,r0
1967	nop
1968	; table for divisor == 0,1, ... ,15
1969	addit,= 0,arg1,r0 ; trap if divisor == 0
1970	nop
1971	bv 0(r31) ; divisor == 1
1972	copy arg0,retreg
1973	b,n $$divI_2 ; divisor == 2
1974	nop
1975	b,n $$divI_3 ; divisor == 3
1976	nop
1977	b,n $$divI_4 ; divisor == 4
1978	nop
1979	b,n $$divI_5 ; divisor == 5
1980	nop
1981	b,n $$divI_6 ; divisor == 6
1982	nop
1983	b,n $$divI_7 ; divisor == 7
1984	nop
1985	b,n $$divI_8 ; divisor == 8
1986	nop
1987	b,n $$divI_9 ; divisor == 9
1988	nop
1989	b,n $$divI_10 ; divisor == 10
1990	nop
1991	b normal1 ; divisor == 11
1992	add,>= 0,arg0,retreg
1993	b,n $$divI_12 ; divisor == 12
1994	nop
1995	b normal1 ; divisor == 13
1996	add,>= 0,arg0,retreg
1997	b,n $$divI_14 ; divisor == 14
1998	nop
1999	b,n $$divI_15 ; divisor == 15
2000	nop
2001	;______________________________________________________________________
2002	negative1:
2003	sub 0,arg0,retreg ; result is negation of dividend
2004	bv 0(r31)
2005	addo arg0,arg1,r0 ; trap iff dividend==0x80000000 && divisor==-1
2006	.exit
2007	.procend
2008
2009	#if 0
2010	.subspa $LIT$
2011	#else
2012	.data
2013	#endif
2014	___hp_free_copyright:
2015	.export ___hp_free_copyright,data
2016	.align 4
2017	.string "(c) Copyright 1986 HEWLETT-PACKARD COMPANY\x0aTo anyone who acknowledges that this file is provided \"AS IS\"\x0awithout any express or implied warranty:\x0a permission to use, copy, modify, and distribute this file\x0afor any purpose is hereby granted without fee, provided that\x0athe above copyright notice and this notice appears in all\x0acopies, and that the name of Hewlett-Packard Company not be\x0aused in advertising or publicity pertaining to distribution\x0aof the software without specific, written prior permission.\x0aHewlett-Packard Company makes no representations about the\x0asuitability of this software for any purpose.\x0a\x00"
2018	.align 4
2019	.end

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