1 | /* UART driver for Blackfin |
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2 | * |
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3 | * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA |
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4 | * written by Allan Hessenflow <allanh@kallisti.com> |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.com/license/LICENSE. |
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9 | */ |
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10 | |
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11 | |
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12 | #include <rtems.h> |
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13 | #include <rtems/libio.h> |
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14 | #include <rtems/termiostypes.h> |
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15 | #include <termios.h> |
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16 | #include <stdlib.h> |
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17 | |
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18 | #include <libcpu/uartRegs.h> |
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19 | #include <libcpu/dmaRegs.h> |
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20 | #include "uart.h" |
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21 | |
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22 | /* flags */ |
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23 | #define BFIN_UART_XMIT_BUSY 0x01 |
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24 | |
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25 | |
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26 | static bfin_uart_config_t *uartsConfig; |
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27 | |
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28 | |
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29 | static int pollRead(int minor) { |
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30 | int c; |
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31 | uint32_t base; |
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32 | |
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33 | base = uartsConfig->channels[minor].uart_baseAddress; |
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34 | |
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35 | /* check to see if driver is using interrupts so this call will be |
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36 | harmless (though non-functional) in case some debug code tries to |
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37 | use it */ |
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38 | if (!uartsConfig->channels[minor].uart_useInterrupts && |
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39 | *((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_DR) |
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40 | c = *((uint16_t volatile *) (base + UART_RBR_OFFSET)); |
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41 | else |
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42 | c = -1; |
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43 | |
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44 | return c; |
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45 | } |
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46 | |
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47 | char bfin_uart_poll_read(rtems_device_minor_number minor) { |
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48 | int c; |
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49 | |
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50 | do { |
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51 | c = pollRead(minor); |
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52 | } while (c == -1); |
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53 | |
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54 | return c; |
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55 | } |
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56 | |
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57 | void bfin_uart_poll_write(int minor, char c) { |
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58 | uint32_t base; |
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59 | |
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60 | base = uartsConfig->channels[minor].uart_baseAddress; |
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61 | |
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62 | while (!(*((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_THRE)) |
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63 | ; |
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64 | *(uint16_t volatile *) (base + UART_THR_OFFSET) = c; |
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65 | } |
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66 | |
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67 | /* begin BISON */ |
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68 | void debug_write_char(char c) { |
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69 | bfin_uart_poll_write(0, c); |
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70 | } |
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71 | |
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72 | void debug_write_string(char *s) { |
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73 | |
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74 | while (s && *s) { |
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75 | if (*s == '\n') |
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76 | debug_write_char('\r'); |
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77 | debug_write_char(*s++); |
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78 | } |
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79 | } |
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80 | |
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81 | void debug_write_crlf(void) { |
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82 | |
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83 | debug_write_char('\r'); |
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84 | debug_write_char('\n'); |
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85 | } |
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86 | |
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87 | void debug_write_nybble(int nybble) { |
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88 | |
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89 | nybble &= 0x0f; |
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90 | debug_write_char((nybble > 9) ? 'a' + (nybble - 10) : '0' + nybble); |
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91 | } |
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92 | |
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93 | void debug_write_byte(int byte) { |
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94 | |
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95 | byte &= 0xff; |
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96 | debug_write_nybble(byte >> 4); |
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97 | debug_write_nybble(byte & 0x0f); |
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98 | } |
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99 | |
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100 | void debug_write_half(int half) { |
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101 | |
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102 | half &= 0xffff; |
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103 | debug_write_byte(half >> 8); |
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104 | debug_write_byte(half & 0xff); |
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105 | } |
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106 | |
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107 | void debug_write_word(int word) { |
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108 | |
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109 | word &= 0xffffffff; |
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110 | debug_write_half(word >> 16); |
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111 | debug_write_half(word & 0xffff); |
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112 | } |
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113 | /* end BISON */ |
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114 | |
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115 | /* |
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116 | * Console Termios Support Entry Points |
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117 | * |
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118 | */ |
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119 | |
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120 | static ssize_t pollWrite(int minor, const char *buf, size_t len) { |
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121 | |
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122 | size_t count; |
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123 | for ( count = 0; count < len; count++ ) |
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124 | bfin_uart_poll_write(minor, *buf++); |
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125 | |
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126 | return count; |
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127 | } |
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128 | |
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129 | |
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130 | /** |
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131 | * Routine to initialize the hardware. It initialize the DMA, |
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132 | * interrupt if required. |
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133 | * @param channel channel information |
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134 | */ |
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135 | static void initializeHardware(bfin_uart_channel_t *channel) { |
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136 | uint16_t divisor = 0; |
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137 | uint32_t base = 0; |
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138 | uint32_t tx_dma_base = 0; |
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139 | |
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140 | if ( NULL == channel ) { |
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141 | return; |
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142 | } |
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143 | |
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144 | base = channel->uart_baseAddress; |
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145 | tx_dma_base = channel->uart_txDmaBaseAddress; |
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146 | /** |
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147 | * RX based DMA and interrupt is not supported yet |
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148 | * uint32_t tx_dma_base = 0; |
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149 | * |
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150 | * rx_dma_base = channel->uart_rxDmaBaseAddress; |
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151 | */ |
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152 | |
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153 | |
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154 | *(uint16_t volatile *) (base + UART_IER_OFFSET) = 0; |
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155 | |
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156 | if ( 0 != channel->uart_baud) { |
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157 | divisor = (uint16_t) (uartsConfig->freq / |
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158 | (channel->uart_baud * 16)); |
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159 | } else { |
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160 | divisor = (uint16_t) (uartsConfig->freq / (9600 * 16)); |
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161 | } |
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162 | |
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163 | *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_DLAB; |
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164 | *(uint16_t volatile *) (base + UART_DLL_OFFSET) = (divisor & 0xff); |
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165 | *(uint16_t volatile *) (base + UART_DLH_OFFSET) = ((divisor >> 8) & 0xff); |
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166 | |
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167 | *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_WLS_8; |
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168 | |
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169 | *(uint16_t volatile *) (base + UART_GCTL_OFFSET) = UART_GCTL_UCEN; |
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170 | |
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171 | /** |
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172 | * To clear previous status |
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173 | * divisor is a temp variable here |
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174 | */ |
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175 | divisor = *(uint16_t volatile *) (base + UART_LSR_OFFSET); |
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176 | divisor = *(uint16_t volatile *) (base + UART_RBR_OFFSET); |
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177 | divisor = *(uint16_t volatile *) (base + UART_IIR_OFFSET); |
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178 | |
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179 | if ( channel->uart_useDma ) { |
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180 | *(uint16_t volatile *)(tx_dma_base + DMA_CONFIG_OFFSET) = 0; |
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181 | *(uint16_t volatile *)(tx_dma_base + DMA_CONFIG_OFFSET) = DMA_CONFIG_DI_EN |
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182 | | DMA_CONFIG_SYNC ; |
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183 | *(uint16_t volatile *)(tx_dma_base + DMA_IRQ_STATUS_OFFSET) |= |
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184 | DMA_IRQ_STATUS_DMA_DONE | DMA_IRQ_STATUS_DMA_ERR; |
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185 | |
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186 | } else { |
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187 | /** |
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188 | * We use polling or interrupts only sending one char at a time :( |
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189 | */ |
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190 | } |
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191 | |
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192 | return; |
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193 | } |
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194 | |
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195 | |
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196 | /** |
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197 | * Set the UART attributes. |
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198 | * @param minor |
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199 | * @param termios |
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200 | * @return |
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201 | */ |
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202 | static int setAttributes(int minor, const struct termios *termios) { |
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203 | uint32_t base; |
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204 | int baud; |
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205 | uint16_t divisor; |
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206 | uint16_t lcr; |
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207 | |
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208 | base = uartsConfig->channels[minor].uart_baseAddress; |
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209 | switch (termios->c_cflag & CBAUD) { |
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210 | case B0: |
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211 | baud = 0; |
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212 | break; |
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213 | case B50: |
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214 | baud = 50; |
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215 | break; |
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216 | case B75: |
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217 | baud = 75; |
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218 | break; |
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219 | case B110: |
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220 | baud = 110; |
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221 | break; |
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222 | case B134: |
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223 | baud = 134; |
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224 | break; |
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225 | case B150: |
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226 | baud = 150; |
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227 | break; |
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228 | case B200: |
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229 | baud = 200; |
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230 | break; |
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231 | case B300: |
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232 | baud = 300; |
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233 | break; |
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234 | case B600: |
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235 | baud = 600; |
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236 | break; |
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237 | case B1200: |
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238 | baud = 1200; |
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239 | break; |
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240 | case B1800: |
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241 | baud = 1800; |
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242 | break; |
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243 | case B2400: |
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244 | baud = 2400; |
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245 | break; |
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246 | case B4800: |
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247 | baud = 4800; |
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248 | break; |
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249 | case B9600: |
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250 | baud = 9600; |
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251 | break; |
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252 | case B19200: |
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253 | baud = 19200; |
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254 | break; |
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255 | case B38400: |
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256 | baud = 38400; |
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257 | break; |
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258 | case B57600: |
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259 | baud = 57600; |
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260 | break; |
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261 | case B115200: |
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262 | baud = 115200; |
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263 | break; |
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264 | case B230400: |
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265 | baud = 230400; |
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266 | break; |
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267 | case B460800: |
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268 | baud = 460800; |
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269 | break; |
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270 | default: |
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271 | baud = -1; |
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272 | break; |
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273 | } |
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274 | if (baud > 0 && uartsConfig->channels[minor].uart_baud) |
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275 | baud = uartsConfig->channels[minor].uart_baud; |
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276 | switch (termios->c_cflag & CSIZE) { |
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277 | case CS5: |
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278 | lcr = UART_LCR_WLS_5; |
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279 | break; |
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280 | case CS6: |
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281 | lcr = UART_LCR_WLS_6; |
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282 | break; |
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283 | case CS7: |
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284 | lcr = UART_LCR_WLS_7; |
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285 | break; |
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286 | case CS8: |
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287 | default: |
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288 | lcr = UART_LCR_WLS_8; |
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289 | break; |
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290 | } |
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291 | switch (termios->c_cflag & (PARENB | PARODD)) { |
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292 | case PARENB: |
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293 | lcr |= UART_LCR_PEN | UART_LCR_EPS; |
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294 | break; |
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295 | case PARENB | PARODD: |
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296 | lcr |= UART_LCR_PEN; |
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297 | break; |
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298 | default: |
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299 | break; |
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300 | } |
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301 | if (termios->c_cflag & CSTOPB) |
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302 | lcr |= UART_LCR_STB; |
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303 | |
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304 | if (baud > 0) { |
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305 | divisor = (uint16_t) (uartsConfig->freq / (baud * 16)); |
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306 | *(uint16_t volatile *) (base + UART_LCR_OFFSET) = lcr | UART_LCR_DLAB; |
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307 | *(uint16_t volatile *) (base + UART_DLL_OFFSET) = (divisor & 0xff); |
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308 | *(uint16_t volatile *) (base + UART_DLH_OFFSET) = ((divisor >> 8) & 0xff); |
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309 | } |
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310 | *(uint16_t volatile *) (base + UART_LCR_OFFSET) = lcr; |
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311 | |
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312 | return 0; |
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313 | } |
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314 | |
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315 | /** |
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316 | * Interrupt based uart tx routine. The routine writes one character at a time. |
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317 | * |
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318 | * @param minor Minor number to indicate uart number |
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319 | * @param buf Character buffer which stores characters to be transmitted. |
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320 | * @param len Length of buffer to be transmitted. |
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321 | * @return |
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322 | */ |
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323 | static ssize_t uart_interruptWrite(int minor, const char *buf, size_t len) { |
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324 | uint32_t base = 0; |
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325 | bfin_uart_channel_t* channel = NULL; |
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326 | rtems_interrupt_level isrLevel; |
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327 | |
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328 | /** |
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329 | * Sanity Check |
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330 | */ |
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331 | if (NULL == buf || NULL == channel || NULL == uartsConfig || minor < 0) { |
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332 | return 0; |
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333 | } |
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334 | |
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335 | channel = &(uartsConfig->channels[minor]); |
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336 | |
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337 | if ( NULL == channel || channel->flags & BFIN_UART_XMIT_BUSY ) { |
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338 | return 0; |
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339 | } |
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340 | |
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341 | rtems_interrupt_disable(isrLevel); |
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342 | |
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343 | base = channel->uart_baseAddress; |
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344 | |
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345 | channel->flags |= BFIN_UART_XMIT_BUSY; |
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346 | channel->length = 1; |
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347 | *(uint16_t volatile *) (base + UART_THR_OFFSET) = *buf; |
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348 | *(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI; |
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349 | |
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350 | rtems_interrupt_enable(isrLevel); |
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351 | |
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352 | return 0; |
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353 | } |
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354 | |
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355 | /** |
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356 | * This function implements RX ISR |
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357 | */ |
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358 | void bfinUart_rxIsr(void *_arg) |
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359 | { |
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360 | /** |
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361 | * TODO: UART RX ISR implementation. |
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362 | */ |
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363 | |
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364 | } |
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365 | |
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366 | |
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367 | /** |
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368 | * This function implements TX ISR. The function gets called when the TX FIFO is |
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369 | * empty. It clears the interrupt and dequeues the character. It only tx one |
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370 | * character at a time. |
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371 | * |
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372 | * TODO: error handling. |
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373 | * @param _arg gets the channel information. |
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374 | */ |
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375 | void bfinUart_txIsr(void *_arg) { |
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376 | bfin_uart_channel_t* channel = NULL; |
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377 | uint32_t base = 0; |
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378 | |
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379 | /** |
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380 | * Sanity check |
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381 | */ |
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382 | if (NULL == _arg) { |
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383 | /** It should never be NULL */ |
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384 | return; |
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385 | } |
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386 | |
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387 | channel = (bfin_uart_channel_t *) _arg; |
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388 | |
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389 | base = channel->uart_baseAddress; |
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390 | |
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391 | *(uint16_t volatile *) (base + UART_IER_OFFSET) &= ~UART_IER_ETBEI; |
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392 | channel->flags &= ~BFIN_UART_XMIT_BUSY; |
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393 | |
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394 | rtems_termios_dequeue_characters(channel->termios, channel->length); |
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395 | |
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396 | return; |
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397 | } |
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398 | |
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399 | |
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400 | |
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401 | |
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402 | /** |
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403 | * interrupt based DMA write Routine. It configure the DMA to write len bytes. |
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404 | * The DMA supports 64K data only. |
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405 | * |
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406 | * @param minor Identification number of the UART. |
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407 | * @param buf Character buffer pointer |
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408 | * @param len length of data items to be written |
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409 | * @return data already written |
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410 | */ |
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411 | static ssize_t uart_DmaWrite(int minor, const char *buf, size_t len) { |
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412 | uint32_t base = 0; |
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413 | bfin_uart_channel_t* channel = NULL; |
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414 | uint32_t tx_dma_base = 0; |
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415 | rtems_interrupt_level isrLevel; |
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416 | |
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417 | /** |
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418 | * Sanity Check |
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419 | */ |
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420 | if ( NULL == buf || 0 > minor || NULL == uartsConfig ) { |
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421 | return 0; |
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422 | } |
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423 | |
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424 | channel = &(uartsConfig->channels[minor]); |
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425 | |
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426 | /** |
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427 | * Sanity Check and check for transmit busy. |
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428 | */ |
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429 | if ( NULL == channel || BFIN_UART_XMIT_BUSY & channel->flags ) { |
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430 | return 0; |
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431 | } |
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432 | |
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433 | rtems_interrupt_disable(isrLevel); |
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434 | |
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435 | base = channel->uart_baseAddress; |
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436 | tx_dma_base = channel->uart_txDmaBaseAddress; |
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437 | |
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438 | channel->flags |= BFIN_UART_XMIT_BUSY; |
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439 | channel->length = len; |
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440 | |
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441 | *(uint16_t volatile *) (tx_dma_base + DMA_CONFIG_OFFSET) &= ~DMA_CONFIG_DMAEN; |
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442 | *(uint32_t volatile *) (tx_dma_base + DMA_START_ADDR_OFFSET) = (uint32_t)buf; |
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443 | *(uint16_t volatile *) (tx_dma_base + DMA_X_COUNT_OFFSET) = channel->length; |
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444 | *(uint16_t volatile *) (tx_dma_base + DMA_X_MODIFY_OFFSET) = 1; |
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445 | *(uint16_t volatile *) (tx_dma_base + DMA_CONFIG_OFFSET) |= DMA_CONFIG_DMAEN; |
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446 | *(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI; |
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447 | |
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448 | rtems_interrupt_enable(isrLevel); |
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449 | |
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450 | return 0; |
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451 | } |
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452 | |
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453 | |
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454 | /** |
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455 | * RX DMA ISR. |
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456 | * The polling route is used for receiving the characters. This is a place |
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457 | * holder for future implementation. |
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458 | * @param _arg |
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459 | */ |
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460 | void bfinUart_rxDmaIsr(void *_arg) { |
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461 | /** |
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462 | * TODO: Implementation of RX DMA |
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463 | */ |
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464 | } |
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465 | |
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466 | /** |
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467 | * This function implements TX dma ISR. It clears the IRQ and dequeues a char |
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468 | * The channel argument will have the base address. Since there are two uart |
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469 | * and both the uarts can use the same tx dma isr. |
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470 | * |
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471 | * TODO: 1. Error checking 2. sending correct length ie after looking at the |
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472 | * number of elements the uart transmitted. |
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473 | * |
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474 | * @param _arg argument passed to the interrupt handler. It contains the |
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475 | * channel argument. |
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476 | */ |
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477 | void bfinUart_txDmaIsr(void *_arg) { |
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478 | bfin_uart_channel_t* channel = NULL; |
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479 | uint32_t tx_dma_base = 0; |
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480 | |
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481 | /** |
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482 | * Sanity check |
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483 | */ |
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484 | if (NULL == _arg) { |
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485 | /** It should never be NULL */ |
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486 | return; |
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487 | } |
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488 | |
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489 | channel = (bfin_uart_channel_t *) _arg; |
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490 | |
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491 | tx_dma_base = channel->uart_txDmaBaseAddress; |
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492 | |
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493 | if ((*(uint16_t volatile *) (tx_dma_base + DMA_IRQ_STATUS_OFFSET) |
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494 | & DMA_IRQ_STATUS_DMA_DONE)) { |
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495 | |
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496 | *(uint16_t volatile *) (tx_dma_base + DMA_IRQ_STATUS_OFFSET) |
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497 | |= DMA_IRQ_STATUS_DMA_DONE | DMA_IRQ_STATUS_DMA_ERR; |
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498 | channel->flags &= ~BFIN_UART_XMIT_BUSY; |
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499 | rtems_termios_dequeue_characters(channel->termios, channel->length); |
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500 | } else { |
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501 | /* UART DMA did not generate interrupt. |
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502 | * This routine must not be called. |
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503 | */ |
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504 | } |
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505 | |
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506 | return; |
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507 | } |
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508 | |
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509 | /** |
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510 | * Function called during exit |
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511 | */ |
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512 | void uart_exit(void) |
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513 | { |
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514 | /** |
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515 | * TODO: Flushing of quques |
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516 | */ |
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517 | |
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518 | } |
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519 | |
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520 | /** |
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521 | * Opens the device in different modes. The supported modes are |
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522 | * 1. Polling |
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523 | * 2. Interrupt |
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524 | * 3. DMA |
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525 | * At exit the uart_Exit function will be called to flush the device. |
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526 | * |
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527 | * @param major Major number of the device |
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528 | * @param minor Minor number of the device |
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529 | * @param arg |
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530 | * @return |
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531 | */ |
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532 | rtems_device_driver bfin_uart_open(rtems_device_major_number major, |
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533 | rtems_device_minor_number minor, void *arg) { |
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534 | rtems_status_code sc = RTEMS_NOT_DEFINED;; |
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535 | rtems_libio_open_close_args_t *args = NULL; |
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536 | |
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537 | /** |
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538 | * Callback function for polling |
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539 | */ |
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540 | static const rtems_termios_callbacks pollCallbacks = { |
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541 | NULL, /* firstOpen */ |
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542 | NULL, /* lastClose */ |
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543 | pollRead, /* pollRead */ |
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544 | pollWrite, /* write */ |
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545 | setAttributes, /* setAttributes */ |
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546 | NULL, /* stopRemoteTx */ |
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547 | NULL, /* startRemoteTx */ |
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548 | TERMIOS_POLLED /* outputUsesInterrupts */ |
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549 | }; |
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550 | |
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551 | /** |
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552 | * Callback function for interrupt based transfers without DMA. |
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553 | * We use interrupts for writing only. For reading we use polling. |
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554 | */ |
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555 | static const rtems_termios_callbacks interruptCallbacks = { |
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556 | NULL, /* firstOpen */ |
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557 | NULL, /* lastClose */ |
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558 | pollRead, /* pollRead */ |
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559 | uart_interruptWrite, /* write */ |
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560 | setAttributes, /* setAttributes */ |
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561 | NULL, /* stopRemoteTx */ |
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562 | NULL, /* startRemoteTx */ |
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563 | TERMIOS_IRQ_DRIVEN /* outputUsesInterrupts */ |
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564 | }; |
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565 | |
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566 | /** |
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567 | * Callback function for interrupt based DMA transfers. |
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568 | * We use interrupts for writing only. For reading we use polling. |
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569 | */ |
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570 | static const rtems_termios_callbacks interruptDmaCallbacks = { |
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571 | NULL, /* firstOpen */ |
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572 | NULL, /* lastClose */ |
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573 | NULL, /* pollRead */ |
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574 | uart_DmaWrite, /* write */ |
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575 | setAttributes, /* setAttributes */ |
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576 | NULL, /* stopRemoteTx */ |
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577 | NULL, /* startRemoteTx */ |
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578 | TERMIOS_IRQ_DRIVEN /* outputUsesInterrupts */ |
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579 | }; |
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580 | |
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581 | |
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582 | if ( NULL == uartsConfig || 0 > minor || minor >= uartsConfig->num_channels) { |
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583 | return RTEMS_INVALID_NUMBER; |
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584 | } |
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585 | |
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586 | /** |
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587 | * Opens device for handling uart send request either by |
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588 | * 1. interrupt with DMA |
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589 | * 2. interrupt based |
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590 | * 3. Polling |
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591 | */ |
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592 | if ( uartsConfig->channels[minor].uart_useDma ) { |
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593 | sc = rtems_termios_open(major, minor, arg, &interruptDmaCallbacks); |
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594 | } else { |
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595 | sc = rtems_termios_open(major, minor, arg, |
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596 | uartsConfig->channels[minor].uart_useInterrupts ? |
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597 | &interruptCallbacks : &pollCallbacks); |
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598 | } |
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599 | |
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600 | args = arg; |
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601 | uartsConfig->channels[minor].termios = args->iop->data1; |
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602 | |
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603 | atexit(uart_exit); |
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604 | |
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605 | return sc; |
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606 | } |
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607 | |
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608 | |
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609 | /** |
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610 | * Uart initialization function. |
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611 | * @param major major number of the device |
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612 | * @param config configuration parameters |
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613 | * @return rtems status code |
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614 | */ |
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615 | rtems_status_code bfin_uart_initialize(rtems_device_major_number major, |
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616 | bfin_uart_config_t *config) { |
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617 | rtems_status_code sc = RTEMS_NOT_DEFINED; |
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618 | int i = 0; |
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619 | |
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620 | rtems_termios_initialize(); |
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621 | |
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622 | /* |
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623 | * Register Device Names |
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624 | */ |
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625 | uartsConfig = config; |
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626 | for (i = 0; i < config->num_channels; i++) { |
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627 | config->channels[i].termios = NULL; |
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628 | config->channels[i].flags = 0; |
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629 | initializeHardware(&(config->channels[i])); |
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630 | sc = rtems_io_register_name(config->channels[i].name, major, i); |
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631 | if (RTEMS_SUCCESSFUL != sc) { |
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632 | return sc; |
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633 | } |
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634 | } |
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635 | |
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636 | return sc; |
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637 | } |
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