1 | /* UART driver for Blackfin |
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2 | */ |
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3 | |
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4 | /* |
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5 | * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA |
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6 | * written by Allan Hessenflow <allanh@kallisti.com> |
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7 | * |
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8 | * The license and distribution terms for this file may be |
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9 | * found in the file LICENSE in this distribution or at |
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10 | * http://www.rtems.org/license/LICENSE. |
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11 | */ |
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12 | |
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13 | #include <rtems.h> |
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14 | #include <rtems/libio.h> |
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15 | #include <rtems/termiostypes.h> |
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16 | #include <termios.h> |
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17 | #include <stdlib.h> |
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18 | |
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19 | #include <libcpu/uartRegs.h> |
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20 | #include <libcpu/dmaRegs.h> |
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21 | #include "uart.h" |
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22 | |
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23 | /* flags */ |
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24 | #define BFIN_UART_XMIT_BUSY 0x01 |
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25 | |
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26 | static bfin_uart_config_t *uartsConfig; |
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27 | |
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28 | static int pollRead(int minor) |
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29 | { |
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30 | int c; |
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31 | uint32_t base; |
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32 | |
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33 | base = uartsConfig->channels[minor].uart_baseAddress; |
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34 | |
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35 | /* check to see if driver is using interrupts so this call will be |
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36 | harmless (though non-functional) in case some debug code tries to |
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37 | use it */ |
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38 | if (!uartsConfig->channels[minor].uart_useInterrupts && |
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39 | *((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_DR) |
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40 | c = *((uint16_t volatile *) (base + UART_RBR_OFFSET)); |
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41 | else |
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42 | c = -1; |
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43 | |
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44 | return c; |
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45 | } |
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46 | |
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47 | char bfin_uart_poll_read(rtems_device_minor_number minor) |
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48 | { |
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49 | int c; |
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50 | |
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51 | do { |
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52 | c = pollRead(minor); |
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53 | } while (c == -1); |
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54 | |
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55 | return c; |
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56 | } |
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57 | |
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58 | void bfin_uart_poll_write(int minor, char c) |
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59 | { |
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60 | uint32_t base; |
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61 | |
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62 | base = uartsConfig->channels[minor].uart_baseAddress; |
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63 | |
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64 | while (!(*((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_THRE)) |
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65 | ; |
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66 | *(uint16_t volatile *) (base + UART_THR_OFFSET) = c; |
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67 | } |
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68 | |
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69 | /* |
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70 | * Console Termios Support Entry Points |
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71 | * |
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72 | */ |
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73 | |
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74 | static ssize_t pollWrite(int minor, const char *buf, size_t len) |
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75 | { |
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76 | size_t count; |
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77 | for ( count = 0; count < len; count++ ) |
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78 | bfin_uart_poll_write(minor, *buf++); |
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79 | |
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80 | return count; |
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81 | } |
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82 | |
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83 | /** |
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84 | * Routine to initialize the hardware. It initialize the DMA, |
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85 | * interrupt if required. |
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86 | * @param channel channel information |
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87 | */ |
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88 | static void initializeHardware(bfin_uart_channel_t *channel) |
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89 | { |
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90 | uint16_t divisor = 0; |
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91 | uint32_t base = 0; |
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92 | uint32_t tx_dma_base = 0; |
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93 | |
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94 | if ( NULL == channel ) { |
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95 | return; |
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96 | } |
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97 | |
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98 | base = channel->uart_baseAddress; |
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99 | tx_dma_base = channel->uart_txDmaBaseAddress; |
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100 | /** |
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101 | * RX based DMA and interrupt is not supported yet |
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102 | * uint32_t tx_dma_base = 0; |
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103 | * |
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104 | * rx_dma_base = channel->uart_rxDmaBaseAddress; |
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105 | */ |
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106 | |
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107 | |
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108 | *(uint16_t volatile *) (base + UART_IER_OFFSET) = 0; |
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109 | |
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110 | if ( 0 != channel->uart_baud) { |
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111 | divisor = (uint16_t) (uartsConfig->freq / |
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112 | (channel->uart_baud * 16)); |
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113 | } else { |
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114 | divisor = (uint16_t) (uartsConfig->freq / (9600 * 16)); |
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115 | } |
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116 | |
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117 | *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_DLAB; |
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118 | *(uint16_t volatile *) (base + UART_DLL_OFFSET) = (divisor & 0xff); |
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119 | *(uint16_t volatile *) (base + UART_DLH_OFFSET) = ((divisor >> 8) & 0xff); |
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120 | |
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121 | *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_WLS_8; |
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122 | |
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123 | *(uint16_t volatile *) (base + UART_GCTL_OFFSET) = UART_GCTL_UCEN; |
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124 | |
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125 | /** |
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126 | * To clear previous status |
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127 | * divisor is a temp variable here |
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128 | */ |
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129 | divisor = *(uint16_t volatile *) (base + UART_LSR_OFFSET); |
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130 | divisor = *(uint16_t volatile *) (base + UART_RBR_OFFSET); |
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131 | divisor = *(uint16_t volatile *) (base + UART_IIR_OFFSET); |
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132 | |
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133 | if ( channel->uart_useDma ) { |
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134 | *(uint16_t volatile *)(tx_dma_base + DMA_CONFIG_OFFSET) = 0; |
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135 | *(uint16_t volatile *)(tx_dma_base + DMA_CONFIG_OFFSET) = DMA_CONFIG_DI_EN |
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136 | | DMA_CONFIG_SYNC ; |
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137 | *(uint16_t volatile *)(tx_dma_base + DMA_IRQ_STATUS_OFFSET) |= |
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138 | DMA_IRQ_STATUS_DMA_DONE | DMA_IRQ_STATUS_DMA_ERR; |
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139 | |
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140 | } else { |
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141 | /** |
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142 | * We use polling or interrupts only sending one char at a time :( |
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143 | */ |
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144 | } |
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145 | } |
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146 | |
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147 | |
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148 | /** |
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149 | * Set the UART attributes. |
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150 | * @param minor |
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151 | * @param termios |
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152 | * @return |
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153 | */ |
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154 | static int setAttributes(int minor, const struct termios *termios) |
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155 | { |
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156 | uint32_t base; |
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157 | int baud; |
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158 | uint16_t divisor; |
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159 | uint16_t lcr; |
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160 | |
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161 | base = uartsConfig->channels[minor].uart_baseAddress; |
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162 | switch (termios->c_ospeed) { |
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163 | case B0: baud = 0; break; |
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164 | case B50: baud = 50; break; |
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165 | case B75: baud = 75; break; |
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166 | case B110: baud = 110; break; |
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167 | case B134: baud = 134; break; |
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168 | case B150: baud = 150; break; |
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169 | case B200: baud = 200; break; |
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170 | case B300: baud = 300; break; |
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171 | case B600: baud = 600; break; |
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172 | case B1200: baud = 1200; break; |
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173 | case B1800: baud = 1800; break; |
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174 | case B2400: baud = 2400; break; |
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175 | case B4800: baud = 4800; break; |
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176 | case B9600: baud = 9600; break; |
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177 | case B19200: baud = 19200; break; |
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178 | case B38400: baud = 38400; break; |
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179 | case B57600: baud = 57600; break; |
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180 | case B115200: baud = 115200; break; |
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181 | case B230400: baud = 230400; break; |
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182 | case B460800: baud = 460800; break; |
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183 | default: baud = -1; break; |
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184 | } |
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185 | if (baud > 0 && uartsConfig->channels[minor].uart_baud) |
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186 | baud = uartsConfig->channels[minor].uart_baud; |
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187 | switch (termios->c_cflag & CSIZE) { |
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188 | case CS5: lcr = UART_LCR_WLS_5; break; |
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189 | case CS6: lcr = UART_LCR_WLS_6; break; |
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190 | case CS7: lcr = UART_LCR_WLS_7; break; |
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191 | default: |
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192 | case CS8: lcr = UART_LCR_WLS_8; break; |
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193 | } |
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194 | switch (termios->c_cflag & (PARENB | PARODD)) { |
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195 | case PARENB: |
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196 | lcr |= UART_LCR_PEN | UART_LCR_EPS; |
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197 | break; |
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198 | case PARENB | PARODD: |
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199 | lcr |= UART_LCR_PEN; |
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200 | break; |
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201 | default: |
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202 | break; |
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203 | } |
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204 | if (termios->c_cflag & CSTOPB) |
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205 | lcr |= UART_LCR_STB; |
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206 | |
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207 | if (baud > 0) { |
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208 | divisor = (uint16_t) (uartsConfig->freq / (baud * 16)); |
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209 | *(uint16_t volatile *) (base + UART_LCR_OFFSET) = lcr | UART_LCR_DLAB; |
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210 | *(uint16_t volatile *) (base + UART_DLL_OFFSET) = (divisor & 0xff); |
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211 | *(uint16_t volatile *) (base + UART_DLH_OFFSET) = ((divisor >> 8) & 0xff); |
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212 | } |
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213 | *(uint16_t volatile *) (base + UART_LCR_OFFSET) = lcr; |
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214 | |
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215 | return 0; |
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216 | } |
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217 | |
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218 | /** |
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219 | * Interrupt based uart tx routine. The routine writes one character at a time. |
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220 | * |
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221 | * @param minor Minor number to indicate uart number |
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222 | * @param buf Character buffer which stores characters to be transmitted. |
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223 | * @param len Length of buffer to be transmitted. |
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224 | * @return |
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225 | */ |
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226 | static ssize_t uart_interruptWrite(int minor, const char *buf, size_t len) |
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227 | { |
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228 | uint32_t base = 0; |
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229 | bfin_uart_channel_t* channel = NULL; |
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230 | |
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231 | /** |
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232 | * Sanity Check |
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233 | */ |
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234 | if ( |
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235 | NULL == buf || NULL == channel || NULL == uartsConfig |
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236 | || minor < 0 || 0 == len |
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237 | ) { |
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238 | return 0; |
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239 | } |
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240 | |
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241 | channel = &(uartsConfig->channels[minor]); |
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242 | |
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243 | if ( NULL == channel || channel->flags & BFIN_UART_XMIT_BUSY ) { |
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244 | return 0; |
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245 | } |
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246 | |
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247 | base = channel->uart_baseAddress; |
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248 | |
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249 | channel->flags |= BFIN_UART_XMIT_BUSY; |
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250 | channel->length = 1; |
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251 | *(uint16_t volatile *) (base + UART_THR_OFFSET) = *buf; |
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252 | *(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI; |
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253 | |
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254 | return 0; |
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255 | } |
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256 | |
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257 | /** |
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258 | * This function implements RX ISR |
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259 | */ |
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260 | void bfinUart_rxIsr(void *_arg) |
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261 | { |
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262 | /** |
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263 | * TODO: UART RX ISR implementation. |
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264 | */ |
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265 | } |
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266 | |
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267 | /** |
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268 | * This function implements TX ISR. The function gets called when the TX FIFO is |
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269 | * empty. It clears the interrupt and dequeues the character. It only tx one |
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270 | * character at a time. |
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271 | * |
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272 | * TODO: error handling. |
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273 | * @param _arg gets the channel information. |
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274 | */ |
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275 | void bfinUart_txIsr(void *_arg) |
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276 | { |
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277 | bfin_uart_channel_t* channel = NULL; |
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278 | uint32_t base = 0; |
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279 | |
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280 | /** |
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281 | * Sanity check |
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282 | */ |
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283 | if (NULL == _arg) { |
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284 | /** It should never be NULL */ |
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285 | return; |
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286 | } |
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287 | |
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288 | channel = (bfin_uart_channel_t *) _arg; |
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289 | |
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290 | base = channel->uart_baseAddress; |
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291 | |
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292 | *(uint16_t volatile *) (base + UART_IER_OFFSET) &= ~UART_IER_ETBEI; |
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293 | channel->flags &= ~BFIN_UART_XMIT_BUSY; |
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294 | |
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295 | rtems_termios_dequeue_characters(channel->termios, channel->length); |
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296 | } |
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297 | |
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298 | /** |
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299 | * interrupt based DMA write Routine. It configure the DMA to write len bytes. |
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300 | * The DMA supports 64K data only. |
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301 | * |
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302 | * @param minor Identification number of the UART. |
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303 | * @param buf Character buffer pointer |
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304 | * @param len length of data items to be written |
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305 | * @return data already written |
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306 | */ |
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307 | static ssize_t uart_DmaWrite(int minor, const char *buf, size_t len) |
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308 | { |
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309 | uint32_t base = 0; |
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310 | bfin_uart_channel_t* channel = NULL; |
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311 | uint32_t tx_dma_base = 0; |
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312 | |
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313 | /** |
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314 | * Sanity Check |
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315 | */ |
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316 | if ( NULL == buf || 0 > minor || NULL == uartsConfig || 0 == len ) { |
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317 | return 0; |
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318 | } |
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319 | |
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320 | channel = &(uartsConfig->channels[minor]); |
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321 | |
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322 | /** |
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323 | * Sanity Check and check for transmit busy. |
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324 | */ |
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325 | if ( NULL == channel || BFIN_UART_XMIT_BUSY & channel->flags ) { |
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326 | return 0; |
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327 | } |
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328 | |
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329 | base = channel->uart_baseAddress; |
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330 | tx_dma_base = channel->uart_txDmaBaseAddress; |
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331 | |
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332 | channel->flags |= BFIN_UART_XMIT_BUSY; |
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333 | channel->length = len; |
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334 | |
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335 | *(uint16_t volatile *) (tx_dma_base + DMA_CONFIG_OFFSET) &= ~DMA_CONFIG_DMAEN; |
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336 | *(uint32_t volatile *) (tx_dma_base + DMA_START_ADDR_OFFSET) = (uint32_t)buf; |
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337 | *(uint16_t volatile *) (tx_dma_base + DMA_X_COUNT_OFFSET) = channel->length; |
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338 | *(uint16_t volatile *) (tx_dma_base + DMA_X_MODIFY_OFFSET) = 1; |
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339 | *(uint16_t volatile *) (tx_dma_base + DMA_CONFIG_OFFSET) |= DMA_CONFIG_DMAEN; |
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340 | *(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI; |
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341 | |
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342 | return 0; |
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343 | } |
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344 | |
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345 | /** |
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346 | * RX DMA ISR. |
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347 | * The polling route is used for receiving the characters. This is a place |
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348 | * holder for future implementation. |
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349 | * @param _arg |
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350 | */ |
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351 | void bfinUart_rxDmaIsr(void *_arg) |
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352 | { |
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353 | /** |
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354 | * TODO: Implementation of RX DMA |
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355 | */ |
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356 | } |
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357 | |
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358 | /** |
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359 | * This function implements TX dma ISR. It clears the IRQ and dequeues a char |
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360 | * The channel argument will have the base address. Since there are two uart |
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361 | * and both the uarts can use the same tx dma isr. |
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362 | * |
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363 | * TODO: 1. Error checking 2. sending correct length ie after looking at the |
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364 | * number of elements the uart transmitted. |
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365 | * |
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366 | * @param _arg argument passed to the interrupt handler. It contains the |
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367 | * channel argument. |
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368 | */ |
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369 | void bfinUart_txDmaIsr(void *_arg) |
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370 | { |
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371 | bfin_uart_channel_t* channel = NULL; |
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372 | uint32_t tx_dma_base = 0; |
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373 | |
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374 | /** |
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375 | * Sanity check |
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376 | */ |
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377 | if (NULL == _arg) { |
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378 | /** It should never be NULL */ |
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379 | return; |
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380 | } |
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381 | |
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382 | channel = (bfin_uart_channel_t *) _arg; |
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383 | |
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384 | tx_dma_base = channel->uart_txDmaBaseAddress; |
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385 | |
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386 | if ((*(uint16_t volatile *) (tx_dma_base + DMA_IRQ_STATUS_OFFSET) |
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387 | & DMA_IRQ_STATUS_DMA_DONE)) { |
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388 | |
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389 | *(uint16_t volatile *) (tx_dma_base + DMA_IRQ_STATUS_OFFSET) |
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390 | |= DMA_IRQ_STATUS_DMA_DONE | DMA_IRQ_STATUS_DMA_ERR; |
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391 | channel->flags &= ~BFIN_UART_XMIT_BUSY; |
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392 | rtems_termios_dequeue_characters(channel->termios, channel->length); |
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393 | } else { |
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394 | /* UART DMA did not generate interrupt. |
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395 | * This routine must not be called. |
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396 | */ |
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397 | } |
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398 | } |
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399 | |
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400 | /** |
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401 | * Function called during exit |
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402 | */ |
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403 | static void uart_exit(void) |
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404 | { |
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405 | /** |
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406 | * TODO: Flushing of quques |
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407 | */ |
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408 | } |
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409 | |
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410 | /** |
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411 | * Opens the device in different modes. The supported modes are |
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412 | * 1. Polling |
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413 | * 2. Interrupt |
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414 | * 3. DMA |
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415 | * At exit the uart_Exit function will be called to flush the device. |
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416 | * |
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417 | * @param major Major number of the device |
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418 | * @param minor Minor number of the device |
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419 | * @param arg |
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420 | * @return |
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421 | */ |
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422 | rtems_device_driver bfin_uart_open(rtems_device_major_number major, |
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423 | rtems_device_minor_number minor, void *arg) { |
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424 | rtems_status_code sc = RTEMS_NOT_DEFINED; |
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425 | rtems_libio_open_close_args_t *args = NULL; |
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426 | |
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427 | /** |
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428 | * Callback function for polling |
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429 | */ |
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430 | static const rtems_termios_callbacks pollCallbacks = { |
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431 | NULL, /* firstOpen */ |
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432 | NULL, /* lastClose */ |
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433 | pollRead, /* pollRead */ |
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434 | pollWrite, /* write */ |
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435 | setAttributes, /* setAttributes */ |
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436 | NULL, /* stopRemoteTx */ |
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437 | NULL, /* startRemoteTx */ |
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438 | TERMIOS_POLLED /* outputUsesInterrupts */ |
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439 | }; |
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440 | |
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441 | /** |
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442 | * Callback function for interrupt based transfers without DMA. |
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443 | * We use interrupts for writing only. For reading we use polling. |
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444 | */ |
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445 | static const rtems_termios_callbacks interruptCallbacks = { |
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446 | NULL, /* firstOpen */ |
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447 | NULL, /* lastClose */ |
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448 | pollRead, /* pollRead */ |
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449 | uart_interruptWrite, /* write */ |
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450 | setAttributes, /* setAttributes */ |
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451 | NULL, /* stopRemoteTx */ |
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452 | NULL, /* startRemoteTx */ |
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453 | TERMIOS_IRQ_DRIVEN /* outputUsesInterrupts */ |
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454 | }; |
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455 | |
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456 | /** |
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457 | * Callback function for interrupt based DMA transfers. |
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458 | * We use interrupts for writing only. For reading we use polling. |
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459 | */ |
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460 | static const rtems_termios_callbacks interruptDmaCallbacks = { |
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461 | NULL, /* firstOpen */ |
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462 | NULL, /* lastClose */ |
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463 | NULL, /* pollRead */ |
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464 | uart_DmaWrite, /* write */ |
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465 | setAttributes, /* setAttributes */ |
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466 | NULL, /* stopRemoteTx */ |
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467 | NULL, /* startRemoteTx */ |
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468 | TERMIOS_IRQ_DRIVEN /* outputUsesInterrupts */ |
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469 | }; |
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470 | |
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471 | if ( NULL == uartsConfig || 0 > minor || minor >= uartsConfig->num_channels) { |
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472 | return RTEMS_INVALID_NUMBER; |
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473 | } |
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474 | |
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475 | /** |
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476 | * Opens device for handling uart send request either by |
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477 | * 1. interrupt with DMA |
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478 | * 2. interrupt based |
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479 | * 3. Polling |
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480 | */ |
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481 | if ( uartsConfig->channels[minor].uart_useDma ) { |
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482 | sc = rtems_termios_open(major, minor, arg, &interruptDmaCallbacks); |
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483 | } else { |
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484 | sc = rtems_termios_open(major, minor, arg, |
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485 | uartsConfig->channels[minor].uart_useInterrupts ? |
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486 | &interruptCallbacks : &pollCallbacks); |
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487 | } |
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488 | |
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489 | args = arg; |
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490 | uartsConfig->channels[minor].termios = args->iop->data1; |
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491 | |
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492 | atexit(uart_exit); |
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493 | |
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494 | return sc; |
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495 | } |
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496 | |
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497 | /** |
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498 | * Uart initialization function. |
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499 | * @param major major number of the device |
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500 | * @param config configuration parameters |
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501 | * @return rtems status code |
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502 | */ |
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503 | rtems_status_code bfin_uart_initialize( |
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504 | rtems_device_major_number major, |
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505 | bfin_uart_config_t *config |
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506 | ) |
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507 | { |
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508 | rtems_status_code sc = RTEMS_NOT_DEFINED; |
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509 | int i = 0; |
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510 | |
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511 | rtems_termios_initialize(); |
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512 | |
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513 | /* |
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514 | * Register Device Names |
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515 | */ |
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516 | uartsConfig = config; |
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517 | for (i = 0; i < config->num_channels; i++) { |
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518 | config->channels[i].termios = NULL; |
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519 | config->channels[i].flags = 0; |
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520 | initializeHardware(&(config->channels[i])); |
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521 | sc = rtems_io_register_name(config->channels[i].name, major, i); |
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522 | if (RTEMS_SUCCESSFUL != sc) { |
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523 | return sc; |
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524 | } |
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525 | } |
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526 | |
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527 | return sc; |
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528 | } |
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