1 | /* this is not much more than a shell; it does not do anything useful yet */ |
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2 | |
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3 | /* TWI (I2C) driver for Blackfin |
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4 | * |
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5 | * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA |
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6 | * written by Allan Hessenflow <allanh@kallisti.com> |
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7 | * |
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8 | * The license and distribution terms for this file may be |
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9 | * found in the file LICENSE in this distribution or at |
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10 | * http://www.rtems.com/license/LICENSE. |
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11 | * |
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12 | * $Id$ |
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13 | */ |
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14 | |
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15 | |
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16 | #include <stdlib.h> |
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17 | #include <rtems.h> |
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18 | |
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19 | #include <libcpu/twiRegs.h> |
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20 | #include "twi.h" |
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21 | |
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22 | |
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23 | #ifndef N_BFIN_TWI |
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24 | #define N_BFIN_TWI 1 |
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25 | #endif |
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26 | |
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27 | #define BFIN_REG16(base, offset) \ |
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28 | (*((uint16_t volatile *) ((char *)(base) + (offset)))) |
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29 | |
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30 | |
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31 | static struct { |
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32 | void *base; |
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33 | rtems_id irqSem; |
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34 | rtems_id mutex; |
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35 | bfin_twi_callback_t callback; |
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36 | void *callbackArg; |
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37 | bfin_twi_request_t volatile *req; |
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38 | uint8_t volatile *dataPtr; |
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39 | int volatile count; |
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40 | bool volatile masterActive; |
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41 | rtems_status_code volatile masterResult; |
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42 | bool volatile slaveActive; |
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43 | } twi[N_BFIN_TWI]; |
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44 | |
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45 | |
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46 | rtems_status_code bfin_twi_init(int channel, bfin_twi_config_t *config) { |
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47 | rtems_status_code result; |
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48 | void *base; |
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49 | |
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50 | if (channel < 0 || channel >= N_BFIN_TWI) |
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51 | return RTEMS_INVALID_NUMBER; |
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52 | |
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53 | base = config->base; |
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54 | twi[channel].base = base; |
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55 | |
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56 | result = rtems_semaphore_create(rtems_build_name('t','w','i','s'), |
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57 | 0, |
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58 | RTEMS_FIFO | |
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59 | RTEMS_SIMPLE_BINARY_SEMAPHORE | |
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60 | RTEMS_NO_INHERIT_PRIORITY | |
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61 | RTEMS_NO_PRIORITY_CEILING | |
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62 | RTEMS_LOCAL, |
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63 | 0, |
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64 | &twi[channel].irqSem); |
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65 | result = rtems_semaphore_create(rtems_build_name('t','w','i','m'), |
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66 | 1, |
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67 | RTEMS_PRIORITY | |
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68 | RTEMS_SIMPLE_BINARY_SEMAPHORE | |
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69 | RTEMS_INHERIT_PRIORITY | |
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70 | RTEMS_NO_PRIORITY_CEILING | |
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71 | RTEMS_LOCAL, |
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72 | 0, |
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73 | &twi[channel].mutex); |
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74 | BFIN_REG16(base, TWI_CONTROL_OFFSET) = |
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75 | (uint16_t) (((config->sclk +9999999) / 10000000) << |
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76 | TWI_CONTROL_PRESCALE_SHIFT) | |
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77 | TWI_CONTROL_TWI_ENA; |
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78 | BFIN_REG16(base, TWI_CLKDIV_OFFSET) = config->fast ? |
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79 | ((8 << TWI_CLKDIV_CLKHI_SHIFT) | |
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80 | (17 << TWI_CLKDIV_CLKLOW_SHIFT)) : |
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81 | ((33 << TWI_CLKDIV_CLKHI_SHIFT) | |
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82 | (67 << TWI_CLKDIV_CLKLOW_SHIFT)); |
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83 | BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET) = 0; |
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84 | BFIN_REG16(base, TWI_MASTER_CTL_OFFSET) = config->fast ? |
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85 | TWI_MASTER_CTL_FAST : |
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86 | 0; |
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87 | BFIN_REG16(base, TWI_SLAVE_ADDR_OFFSET) = (uint16_t) config->slave_address << |
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88 | TWI_SLAVE_ADDR_SADDR_SHIFT; |
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89 | BFIN_REG16(base, TWI_MASTER_STAT_OFFSET) = TWI_MASTER_STAT_BUFWRERR | |
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90 | TWI_MASTER_STAT_BUFRDERR | |
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91 | TWI_MASTER_STAT_DNAK | |
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92 | TWI_MASTER_STAT_ANAK | |
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93 | TWI_MASTER_STAT_LOSTARB; |
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94 | BFIN_REG16(base, TWI_FIFO_CTL_OFFSET) = TWI_FIFO_CTL_XMTFLUSH | |
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95 | TWI_FIFO_CTL_RCVFLUSH; |
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96 | BFIN_REG16(base, TWI_FIFO_CTL_OFFSET) = 0; |
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97 | BFIN_REG16(base, TWI_INT_STAT_OFFSET) = TWI_INT_STAT_RCVSERV | |
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98 | TWI_INT_STAT_XMTSERV | |
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99 | TWI_INT_STAT_MERR | |
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100 | TWI_INT_STAT_MCOMP | |
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101 | TWI_INT_STAT_SOVF | |
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102 | TWI_INT_STAT_SERR | |
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103 | TWI_INT_STAT_SCOMP | |
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104 | TWI_INT_STAT_SINIT; |
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105 | BFIN_REG16(base, TWI_INT_MASK_OFFSET) = TWI_INT_MASK_RCVSERVM | |
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106 | TWI_INT_MASK_XMTSERVM; |
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107 | |
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108 | return result; |
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109 | } |
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110 | |
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111 | rtems_status_code bfin_twi_register_callback(int channel, |
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112 | bfin_twi_callback_t callback, |
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113 | void *arg) { |
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114 | void *base; |
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115 | int level; |
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116 | |
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117 | if (channel < 0 || channel >= N_BFIN_TWI) |
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118 | return RTEMS_INVALID_NUMBER; |
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119 | |
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120 | base = twi[channel].base; |
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121 | if (callback == NULL) |
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122 | BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET) = 0; |
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123 | rtems_interrupt_disable(level); |
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124 | twi[channel].callback = callback; |
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125 | twi[channel].callbackArg = arg; |
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126 | rtems_interrupt_enable(level); |
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127 | if (callback != NULL) |
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128 | BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET) = TWI_SLAVE_CTL_GEN | |
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129 | TWI_SLAVE_CTL_SEN; |
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130 | |
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131 | return RTEMS_SUCCESSFUL; |
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132 | } |
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133 | |
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134 | void bfin_twi_isr(int source) { |
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135 | void *base; |
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136 | int i; |
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137 | uint16_t r; |
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138 | uint16_t stat; |
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139 | |
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140 | for (i = 0; i < N_BFIN_TWI; i++) { |
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141 | base = twi[i].base; |
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142 | if (base) { |
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143 | stat = BFIN_REG16(base, TWI_INT_STAT_OFFSET); |
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144 | if (stat) { |
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145 | BFIN_REG16(base, TWI_INT_STAT_OFFSET) = stat; |
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146 | if ((stat & TWI_INT_STAT_SINIT) && !twi[i].slaveActive) { |
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147 | twi[i].slaveActive = true; |
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148 | r = BFIN_REG16(base, TWI_FIFO_CTL_OFFSET); |
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149 | BFIN_REG16(base, TWI_FIFO_CTL_OFFSET) = r | TWI_FIFO_CTL_XMTFLUSH; |
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150 | BFIN_REG16(base, TWI_FIFO_CTL_OFFSET) = r; |
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151 | r = BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET); |
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152 | BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET) = r | TWI_SLAVE_CTL_STDVAL; |
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153 | } |
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154 | if (twi[i].slaveActive) { |
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155 | |
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156 | |
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157 | if (stat & (TWI_INT_STAT_SCOMP | TWI_INT_STAT_SERR)) { |
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158 | |
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159 | |
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160 | r = BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET); |
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161 | BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET) = r & ~TWI_SLAVE_CTL_STDVAL; |
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162 | twi[i].slaveActive = false; |
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163 | |
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164 | |
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165 | } |
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166 | } |
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167 | if (twi[i].masterActive && !twi[i].slaveActive) { |
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168 | |
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169 | |
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170 | if (stat & (TWI_INT_STAT_MCOMP | TWI_INT_STAT_MERR)) { |
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171 | if (!(stat & TWI_INT_STAT_MERR)) { |
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172 | |
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173 | |
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174 | rtems_semaphore_release(twi[i].irqSem); |
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175 | |
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176 | |
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177 | } else |
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178 | rtems_semaphore_release(twi[i].irqSem); |
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179 | } |
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180 | } |
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181 | } |
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182 | } |
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183 | } |
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184 | } |
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185 | |
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186 | rtems_status_code bfin_twi_request(int channel, uint8_t address, |
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187 | bfin_twi_request_t *request, |
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188 | rtems_interval timeout) { |
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189 | rtems_status_code result; |
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190 | void *base; |
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191 | rtems_interrupt_level level; |
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192 | uint16_t r; |
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193 | uint16_t masterMode; |
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194 | |
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195 | if (channel < 0 || channel >= N_BFIN_TWI) |
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196 | return RTEMS_INVALID_NUMBER; |
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197 | result = rtems_semaphore_obtain(twi[channel].mutex, |
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198 | RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
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199 | if (result == RTEMS_SUCCESSFUL) { |
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200 | base = twi[channel].base; |
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201 | twi[channel].req = request; |
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202 | |
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203 | if (request->write) { |
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204 | twi[channel].dataPtr = request->data; |
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205 | twi[channel].count = request->count; |
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206 | } else |
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207 | twi[channel].count = 0; |
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208 | |
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209 | BFIN_REG16(base, TWI_MASTER_ADDR_OFFSET) = (uint16_t) address << |
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210 | TWI_MASTER_ADDR_MADDR_SHIFT; |
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211 | masterMode = BFIN_REG16(base, TWI_MASTER_CTL_OFFSET); |
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212 | masterMode |= (request->count << TWI_MASTER_CTL_DCNT_SHIFT); |
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213 | if (request->next) |
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214 | masterMode |= TWI_MASTER_CTL_RSTART; |
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215 | if (!request->write) |
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216 | masterMode |= TWI_MASTER_CTL_MDIR; |
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217 | masterMode |= TWI_MASTER_CTL_MEN; |
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218 | rtems_interrupt_disable(level); |
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219 | if (!twi[channel].slaveActive) { |
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220 | r = BFIN_REG16(base, TWI_FIFO_CTL_OFFSET); |
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221 | BFIN_REG16(base, TWI_FIFO_CTL_OFFSET) = r | TWI_FIFO_CTL_XMTFLUSH; |
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222 | BFIN_REG16(base, TWI_FIFO_CTL_OFFSET) = r; |
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223 | if (request->write) { |
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224 | while (twi[channel].count && |
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225 | (BFIN_REG16(base, TWI_FIFO_STAT_OFFSET) & |
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226 | TWI_FIFO_STAT_XMTSTAT_MASK) != |
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227 | TWI_FIFO_STAT_XMTSTAT_FULL) { |
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228 | BFIN_REG16(base, TWI_XMT_DATA8_OFFSET) = |
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229 | (uint16_t) *twi[channel].dataPtr++; |
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230 | twi[channel].count--; |
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231 | } |
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232 | } |
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233 | twi[channel].masterActive = true; |
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234 | BFIN_REG16(base, TWI_MASTER_CTL_OFFSET) = masterMode; |
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235 | } else { |
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236 | twi[channel].masterActive = false; |
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237 | twi[channel].masterResult = -1; /* BISON (code should be equiv to lost arbitration) */ |
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238 | } |
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239 | rtems_interrupt_enable(level); |
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240 | while (result == RTEMS_SUCCESSFUL && twi[channel].masterActive) |
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241 | result = rtems_semaphore_obtain(twi[channel].irqSem, |
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242 | RTEMS_WAIT, timeout); |
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243 | if (result == RTEMS_SUCCESSFUL) |
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244 | result = twi[channel].masterResult; |
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245 | else { |
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246 | /* BISON abort */ |
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247 | |
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248 | |
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249 | |
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250 | } |
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251 | rtems_semaphore_release(twi[channel].mutex); |
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252 | } |
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253 | return result; |
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254 | } |
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255 | |
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