1 | /* |
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2 | * RTEMS network driver for Blackfin ethernet controller |
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3 | * |
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4 | * COPYRIGHT (c) 2008 Kallisti Labs, Los Gatos, CA, USA |
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5 | * written by Allan Hessenflow <allanh@kallisti.com> |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * http://www.rtems.org/license/LICENSE. |
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10 | * |
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11 | */ |
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12 | |
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13 | #include <rtems.h> |
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14 | #include <rtems/rtems_bsdnet.h> |
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15 | #include <rtems/rtems/cache.h> |
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16 | |
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17 | #include <stdio.h> |
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18 | #include <inttypes.h> |
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19 | #include <string.h> |
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20 | |
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21 | #include <errno.h> |
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22 | #include <rtems/error.h> |
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23 | |
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24 | #include <sys/param.h> |
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25 | #include <sys/mbuf.h> |
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26 | #include <sys/socket.h> |
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27 | #include <sys/sockio.h> |
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28 | #include <sys/sockio.h> |
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29 | |
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30 | #include <net/if.h> |
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31 | |
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32 | #include <netinet/in.h> |
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33 | #include <netinet/if_ether.h> |
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34 | |
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35 | #include <libcpu/dmaRegs.h> |
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36 | #include <libcpu/ethernetRegs.h> |
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37 | #include "ethernet.h" |
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38 | |
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39 | #if (BFIN_ETHERNET_DEBUG & BFIN_ETHERNET_DEBUG_DUMP_MBUFS) |
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40 | #include <rtems/dumpbuf.h> |
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41 | #endif |
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42 | |
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43 | /* |
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44 | * Number of devices supported by this driver |
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45 | */ |
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46 | #ifndef N_BFIN_ETHERNET |
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47 | # define N_BFIN_ETHERNET 1 |
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48 | #endif |
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49 | |
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50 | |
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51 | /* #define BFIN_IPCHECKSUMS */ |
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52 | |
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53 | |
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54 | /* |
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55 | * RTEMS event used by interrupt handler to signal daemons. |
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56 | */ |
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57 | #define INTERRUPT_EVENT RTEMS_EVENT_1 |
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58 | |
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59 | /* |
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60 | * RTEMS event used to start transmit daemon. |
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61 | */ |
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62 | #define START_TRANSMIT_EVENT RTEMS_EVENT_2 |
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63 | |
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64 | |
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65 | /* largest Ethernet frame MAC will handle */ |
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66 | #define BFIN_ETHERNET_MAX_FRAME_LENGTH 1556 |
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67 | |
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68 | #if MCLBYTES < (BFIN_ETHERNET_MAX_FRAME_LENGTH + 2) |
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69 | #error MCLBYTES too small |
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70 | #endif |
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71 | |
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72 | #define BFIN_REG16(base, offset) \ |
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73 | (*((uint16_t volatile *) ((char *)(base) + (offset)))) |
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74 | #define BFIN_REG32(base, offset) \ |
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75 | (*((uint32_t volatile *) ((char *)(base) + (offset)))) |
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76 | |
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77 | |
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78 | #define DMA_MODE_RX (DMA_CONFIG_FLOW_DESC_LARGE | \ |
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79 | (5 << DMA_CONFIG_NDSIZE_SHIFT) | \ |
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80 | DMA_CONFIG_WDSIZE_32 | \ |
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81 | DMA_CONFIG_WNR | \ |
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82 | DMA_CONFIG_DMAEN) |
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83 | |
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84 | #define DMA_MODE_TX (DMA_CONFIG_FLOW_DESC_LARGE | \ |
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85 | (5 << DMA_CONFIG_NDSIZE_SHIFT) | \ |
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86 | DMA_CONFIG_WDSIZE_32 | \ |
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87 | DMA_CONFIG_DMAEN) |
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88 | |
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89 | #define DMA_MODE_STATUS (DMA_CONFIG_FLOW_DESC_LARGE | \ |
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90 | (5 << DMA_CONFIG_NDSIZE_SHIFT) | \ |
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91 | DMA_CONFIG_DI_EN | \ |
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92 | DMA_CONFIG_WDSIZE_32 | \ |
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93 | DMA_CONFIG_WNR | \ |
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94 | DMA_CONFIG_DMAEN) |
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95 | |
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96 | #define DMA_MODE_STATUS_NO_INT (DMA_CONFIG_FLOW_DESC_LARGE | \ |
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97 | (5 << DMA_CONFIG_NDSIZE_SHIFT) | \ |
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98 | DMA_CONFIG_WDSIZE_32 | \ |
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99 | DMA_CONFIG_WNR | \ |
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100 | DMA_CONFIG_DMAEN) |
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101 | |
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102 | #define DMA_MODE_STATUS_LAST (DMA_CONFIG_FLOW_STOP | \ |
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103 | (0 << DMA_CONFIG_NDSIZE_SHIFT) | \ |
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104 | DMA_CONFIG_DI_EN | \ |
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105 | DMA_CONFIG_WDSIZE_32 | \ |
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106 | DMA_CONFIG_WNR | \ |
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107 | DMA_CONFIG_DMAEN) |
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108 | |
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109 | /* five 16 bit words */ |
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110 | typedef struct dmaDescS { |
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111 | struct dmaDescS *next; |
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112 | void *addr; |
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113 | uint16_t dmaConfig; |
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114 | } dmaDescT; |
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115 | |
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116 | typedef struct { |
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117 | uint32_t status; |
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118 | } txStatusT; |
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119 | |
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120 | #ifdef BFIN_IPCHECKSUMS |
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121 | typedef struct { |
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122 | uint16_t ipHeaderChecksum; |
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123 | uint16_t ipPayloadChecksum; |
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124 | uint32_t status; |
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125 | } rxStatusT; |
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126 | #else |
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127 | typedef struct { |
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128 | uint32_t status; |
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129 | } rxStatusT; |
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130 | #endif |
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131 | |
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132 | typedef struct { |
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133 | dmaDescT data; |
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134 | dmaDescT status; |
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135 | struct mbuf *m; |
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136 | } rxPacketDescT; |
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137 | |
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138 | typedef struct { |
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139 | dmaDescT data; |
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140 | dmaDescT status; |
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141 | bool inUse; |
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142 | union { |
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143 | uint32_t dummy; /* try to force 32 bit alignment */ |
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144 | struct { |
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145 | uint16_t length; |
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146 | char data[BFIN_ETHERNET_MAX_FRAME_LENGTH]; |
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147 | } packet; |
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148 | } buffer; |
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149 | } txPacketDescT; |
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150 | |
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151 | |
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152 | /* hardware-specific storage */ |
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153 | struct bfin_ethernetSoftc { |
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154 | struct arpcom arpcom; /* this entry must be first */ |
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155 | |
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156 | uint32_t sclk; |
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157 | |
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158 | void *ethBase; |
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159 | void *rxdmaBase; |
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160 | void *txdmaBase; |
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161 | |
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162 | int acceptBroadcast; |
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163 | |
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164 | rtems_id rxDaemonTid; |
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165 | rtems_id txDaemonTid; |
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166 | |
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167 | void *status; |
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168 | int rxDescCount; |
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169 | rxPacketDescT *rx; |
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170 | int txDescCount; |
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171 | txPacketDescT *tx; |
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172 | |
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173 | bool rmii; |
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174 | int phyAddr; |
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175 | |
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176 | /* statistics */ |
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177 | #ifdef BISON |
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178 | unsigned long Interrupts; |
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179 | unsigned long rxInterrupts; |
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180 | unsigned long rxMissed; |
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181 | unsigned long rxGiant; |
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182 | unsigned long rxNonOctet; |
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183 | unsigned long rxBadCRC; |
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184 | unsigned long rxCollision; |
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185 | |
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186 | unsigned long txInterrupts; |
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187 | unsigned long txSingleCollision; |
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188 | unsigned long txMultipleCollision; |
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189 | unsigned long txCollision; |
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190 | unsigned long txDeferred; |
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191 | unsigned long txUnderrun; |
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192 | unsigned long txLateCollision; |
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193 | unsigned long txExcessiveCollision; |
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194 | unsigned long txExcessiveDeferral; |
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195 | unsigned long txLostCarrier; |
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196 | unsigned long txRawWait; |
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197 | #endif |
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198 | }; |
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199 | |
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200 | static struct bfin_ethernetSoftc ethernetSoftc[N_BFIN_ETHERNET]; |
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201 | |
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202 | |
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203 | /* Shut down the interface. */ |
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204 | static void ethernetStop(struct bfin_ethernetSoftc *sc) { |
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205 | struct ifnet *ifp; |
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206 | void *ethBase; |
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207 | |
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208 | ifp = &sc->arpcom.ac_if; |
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209 | ethBase = sc->ethBase; |
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210 | |
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211 | ifp->if_flags &= ~IFF_RUNNING; |
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212 | |
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213 | /* stop the transmitter and receiver. */ |
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214 | BFIN_REG32(ethBase, EMAC_OPMODE_OFFSET) &= ~(EMAC_OPMODE_TE | |
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215 | EMAC_OPMODE_RE); |
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216 | } |
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217 | |
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218 | /* Show interface statistics */ |
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219 | static void bfin_ethernetStats(struct bfin_ethernetSoftc *sc) { |
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220 | #ifdef BISON |
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221 | printf(" Total Interrupts:%-8lu", sc->Interrupts); |
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222 | printf(" Rx Interrupts:%-8lu", sc->rxInterrupts); |
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223 | printf(" Giant:%-8lu", sc->rxGiant); |
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224 | printf(" Non-octet:%-8lu\n", sc->rxNonOctet); |
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225 | printf(" Bad CRC:%-8lu", sc->rxBadCRC); |
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226 | printf(" Collision:%-8lu", sc->rxCollision); |
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227 | printf(" Missed:%-8lu\n", sc->rxMissed); |
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228 | |
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229 | printf( " Tx Interrupts:%-8lu", sc->txInterrupts); |
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230 | printf( " Deferred:%-8lu", sc->txDeferred); |
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231 | printf(" Lost Carrier:%-8lu\n", sc->txLostCarrier); |
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232 | printf( "Single Collisions:%-8lu", sc->txSingleCollision); |
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233 | printf( "Multiple Collisions:%-8lu", sc->txMultipleCollision); |
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234 | printf("Excessive Collisions:%-8lu\n", sc->txExcessiveCollision); |
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235 | printf( " Total Collisions:%-8lu", sc->txCollision); |
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236 | printf( " Late Collision:%-8lu", sc->txLateCollision); |
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237 | printf(" Underrun:%-8lu\n", sc->txUnderrun); |
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238 | printf( " Raw output wait:%-8lu\n", sc->txRawWait); |
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239 | #endif /*BISON*/ |
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240 | } |
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241 | |
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242 | void bfin_ethernet_rxdma_isr(int vector) { |
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243 | struct bfin_ethernetSoftc *sc; |
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244 | void *rxdmaBase; |
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245 | uint16_t status; |
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246 | int i; |
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247 | |
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248 | for (i = 0; i < N_BFIN_ETHERNET; i++) { |
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249 | sc = ðernetSoftc[i]; |
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250 | rxdmaBase = sc->rxdmaBase; |
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251 | status = BFIN_REG16(rxdmaBase, DMA_IRQ_STATUS_OFFSET); |
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252 | if (status & DMA_IRQ_STATUS_DMA_DONE) |
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253 | rtems_bsdnet_event_send (sc->rxDaemonTid, INTERRUPT_EVENT); |
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254 | BFIN_REG16(rxdmaBase, DMA_IRQ_STATUS_OFFSET) = status; |
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255 | } |
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256 | } |
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257 | |
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258 | void bfin_ethernet_txdma_isr(int vector) { |
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259 | struct bfin_ethernetSoftc *sc; |
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260 | void *txdmaBase; |
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261 | uint16_t status; |
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262 | int i; |
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263 | |
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264 | for (i = 0; i < N_BFIN_ETHERNET; i++) { |
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265 | sc = ðernetSoftc[i]; |
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266 | txdmaBase = sc->txdmaBase; |
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267 | status = BFIN_REG16(txdmaBase, DMA_IRQ_STATUS_OFFSET); |
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268 | if (status & DMA_IRQ_STATUS_DMA_DONE) |
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269 | rtems_bsdnet_event_send (sc->txDaemonTid, INTERRUPT_EVENT); |
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270 | BFIN_REG16(txdmaBase, DMA_IRQ_STATUS_OFFSET) = status; |
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271 | } |
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272 | } |
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273 | |
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274 | void bfin_ethernet_mac_isr(int vector) { |
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275 | struct bfin_ethernetSoftc *sc; |
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276 | void *ethBase; |
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277 | int i; |
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278 | |
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279 | for (i = 0; i < N_BFIN_ETHERNET; i++) { |
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280 | sc = ðernetSoftc[i]; |
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281 | ethBase = sc->ethBase; |
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282 | BFIN_REG32(ethBase, EMAC_SYSTAT_OFFSET) = ~(uint32_t) 0; |
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283 | } |
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284 | } |
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285 | |
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286 | static bool txFree(struct bfin_ethernetSoftc *sc, int index) { |
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287 | bool freed; |
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288 | txStatusT *status; |
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289 | |
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290 | freed = false; |
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291 | if (sc->tx[index].inUse) { |
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292 | status = (txStatusT *) sc->tx[index].status.addr; |
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293 | rtems_cache_invalidate_multiple_data_lines(status, sizeof(*status)); |
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294 | if (status->status != 0) { |
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295 | /* update statistics */ |
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296 | |
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297 | sc->tx[index].inUse = false; |
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298 | freed = true; |
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299 | } |
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300 | } |
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301 | |
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302 | return freed; |
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303 | } |
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304 | |
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305 | static void txDaemon(void *arg) { |
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306 | struct bfin_ethernetSoftc *sc; |
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307 | struct ifnet *ifp; |
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308 | struct mbuf *m, *first; |
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309 | rtems_event_set events; |
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310 | void *ethBase; |
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311 | void *txdmaBase; |
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312 | txStatusT *status; |
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313 | int head; |
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314 | int prevHead; |
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315 | int tail; |
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316 | int length; |
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317 | char *ptr; |
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318 | |
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319 | sc = (struct bfin_ethernetSoftc *) arg; |
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320 | ifp = &sc->arpcom.ac_if; |
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321 | |
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322 | ethBase = sc->ethBase; |
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323 | txdmaBase = sc->txdmaBase; |
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324 | head = 0; |
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325 | prevHead = sc->txDescCount - 1; |
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326 | tail = 0; |
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327 | |
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328 | while (1) { |
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329 | /* wait for packet or isr */ |
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330 | rtems_bsdnet_event_receive(START_TRANSMIT_EVENT | INTERRUPT_EVENT, |
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331 | RTEMS_EVENT_ANY | RTEMS_WAIT, |
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332 | RTEMS_NO_TIMEOUT, &events); |
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333 | |
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334 | /* if no descriptors are available, try to free one. To reduce |
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335 | transmit latency only do one here. */ |
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336 | if (sc->tx[head].inUse && txFree(sc, tail)) { |
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337 | if (++tail == sc->txDescCount) |
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338 | tail = 0; |
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339 | } |
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340 | /* send packets until the queue is empty or we run out of tx |
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341 | descriptors */ |
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342 | while (!sc->tx[head].inUse && (ifp->if_flags & IFF_OACTIVE)) { |
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343 | /* get the next mbuf chain to transmit */ |
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344 | IF_DEQUEUE(&ifp->if_snd, m); |
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345 | if (m != NULL) { |
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346 | /* copy packet into our buffer */ |
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347 | ptr = sc->tx[head].buffer.packet.data; |
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348 | length = 0; |
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349 | first = m; |
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350 | while (m && length <= BFIN_ETHERNET_MAX_FRAME_LENGTH) { |
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351 | length += m->m_len; |
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352 | if (length <= BFIN_ETHERNET_MAX_FRAME_LENGTH) |
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353 | memcpy(ptr, m->m_data, m->m_len); |
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354 | ptr += m->m_len; |
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355 | m = m->m_next; |
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356 | } |
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357 | m_freem(first); /* all done with mbuf */ |
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358 | if (length <= BFIN_ETHERNET_MAX_FRAME_LENGTH) { |
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359 | sc->tx[head].buffer.packet.length = length; |
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360 | |
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361 | /* setup tx dma */ |
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362 | status = (txStatusT *) sc->tx[head].status.addr; |
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363 | status->status = 0; |
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364 | sc->tx[head].inUse = true; |
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365 | rtems_cache_flush_multiple_data_lines(status, sizeof(*status)); |
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366 | |
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367 | /* configure dma to stop after sending this packet */ |
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368 | sc->tx[head].status.dmaConfig = DMA_MODE_STATUS_LAST; |
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369 | rtems_cache_flush_multiple_data_lines( |
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370 | &sc->tx[head].status.dmaConfig, |
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371 | sizeof(sc->tx[head].status.dmaConfig)); |
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372 | rtems_cache_flush_multiple_data_lines( |
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373 | &sc->tx[head].buffer.packet, |
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374 | length + sizeof(uint16_t)); |
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375 | |
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376 | /* modify previous descriptor to let it continue |
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377 | automatically */ |
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378 | sc->tx[prevHead].status.dmaConfig = DMA_MODE_STATUS; |
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379 | rtems_cache_flush_multiple_data_lines( |
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380 | &sc->tx[prevHead].status.dmaConfig, |
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381 | sizeof(sc->tx[prevHead].status.dmaConfig)); |
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382 | |
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383 | /* restart dma if it stopped before the packet we just |
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384 | added. this is purely to reduce transmit latency, |
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385 | as it would be restarted anyway after this loop (and |
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386 | needs to be, as there's a very small chance that the |
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387 | dma controller had started the last status transfer |
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388 | before the new dmaConfig word was written above and |
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389 | is still doing that status transfer when we check the |
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390 | status below. this will be caught by the check |
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391 | outside the loop as that is guaranteed to run at least |
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392 | once after the last dma complete interrupt. */ |
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393 | if ((BFIN_REG16(txdmaBase, DMA_IRQ_STATUS_OFFSET) & |
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394 | DMA_IRQ_STATUS_DMA_RUN) == 0 && |
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395 | BFIN_REG32(txdmaBase, DMA_NEXT_DESC_PTR_OFFSET) != |
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396 | (uint32_t) sc->tx[head].data.next) { |
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397 | BFIN_REG16(txdmaBase, DMA_CONFIG_OFFSET) = DMA_MODE_TX; |
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398 | BFIN_REG32(ethBase, EMAC_OPMODE_OFFSET) |= EMAC_OPMODE_TE; |
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399 | } |
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400 | |
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401 | if (++head == sc->txDescCount) |
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402 | head = 0; |
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403 | if (++prevHead == sc->txDescCount) |
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404 | prevHead = 0; |
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405 | |
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406 | /* if no descriptors are available, try to free one */ |
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407 | if (sc->tx[head].inUse && txFree(sc, tail)) { |
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408 | if (++tail == sc->txDescCount) |
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409 | tail = 0; |
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410 | } |
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411 | } else { |
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412 | /* dropping packet: too large */ |
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413 | |
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414 | } |
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415 | } else { |
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416 | /* no packets queued */ |
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417 | ifp->if_flags &= ~IFF_OACTIVE; |
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418 | } |
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419 | } |
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420 | |
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421 | /* if dma stopped and there's more to do, restart it */ |
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422 | if ((BFIN_REG16(txdmaBase, DMA_IRQ_STATUS_OFFSET) & |
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423 | DMA_IRQ_STATUS_DMA_RUN) == 0 && |
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424 | BFIN_REG32(txdmaBase, DMA_NEXT_DESC_PTR_OFFSET) != |
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425 | (uint32_t) &sc->tx[head].data) { |
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426 | BFIN_REG16(txdmaBase, DMA_CONFIG_OFFSET) = DMA_MODE_TX; |
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427 | BFIN_REG32(ethBase, EMAC_OPMODE_OFFSET) |= EMAC_OPMODE_TE; |
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428 | } |
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429 | |
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430 | /* free up any additional tx descriptors */ |
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431 | while (txFree(sc, tail)) { |
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432 | if (++tail == sc->txDescCount) |
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433 | tail = 0; |
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434 | } |
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435 | } |
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436 | } |
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437 | |
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438 | |
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439 | static void rxDaemon(void *arg) { |
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440 | struct bfin_ethernetSoftc *sc; |
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441 | struct ifnet *ifp; |
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442 | struct mbuf *m; |
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443 | struct mbuf *rxPacket; |
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444 | void *dataPtr; |
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445 | rtems_event_set events; |
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446 | struct ether_header *eh; |
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447 | rxStatusT *status; |
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448 | uint32_t rxStatus; |
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449 | int head; |
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450 | int prevHead; |
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451 | int length; |
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452 | void *ethBase; |
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453 | void *rxdmaBase; |
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454 | |
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455 | sc = (struct bfin_ethernetSoftc *) arg; |
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456 | rxdmaBase = sc->rxdmaBase; |
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457 | ethBase = sc->ethBase; |
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458 | ifp = &sc->arpcom.ac_if; |
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459 | prevHead = sc->rxDescCount - 1; |
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460 | head = 0; |
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461 | |
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462 | BFIN_REG16(rxdmaBase, DMA_CONFIG_OFFSET) = DMA_MODE_RX; |
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463 | BFIN_REG32(ethBase, EMAC_OPMODE_OFFSET) |= EMAC_OPMODE_RE; |
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464 | |
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465 | while (1) { |
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466 | status = sc->rx[head].status.addr; |
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467 | rtems_cache_invalidate_multiple_data_lines(status, sizeof(*status)); |
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468 | while (status->status != 0) { |
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469 | if (status->status & EMAC_RX_STAT_RX_OK) { |
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470 | /* get new cluster to replace this one */ |
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471 | MGETHDR(m, M_WAIT, MT_DATA); |
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472 | MCLGET(m, M_WAIT); |
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473 | m->m_pkthdr.rcvif = ifp; |
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474 | } else |
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475 | m = NULL; |
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476 | |
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477 | rxStatus = status->status; |
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478 | /* update statistics */ |
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479 | |
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480 | |
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481 | if (m) { |
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482 | /* save received packet to send up a little later */ |
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483 | rxPacket = sc->rx[head].m; |
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484 | dataPtr = sc->rx[head].data.addr; |
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485 | |
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486 | /* setup dma for new cluster */ |
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487 | sc->rx[head].m = m; |
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488 | sc->rx[head].data.addr = (void *) (((intptr_t) m->m_data + 3) & ~3); |
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489 | /* invalidate cache for new data buffer, in case any lines |
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490 | are dirty from previous owner */ |
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491 | rtems_cache_invalidate_multiple_data_lines( |
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492 | sc->rx[head].data.addr, |
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493 | BFIN_ETHERNET_MAX_FRAME_LENGTH + 2); |
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494 | } else |
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495 | rxPacket = NULL; |
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496 | |
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497 | sc->rx[head].status.dmaConfig = DMA_MODE_STATUS_LAST; |
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498 | rtems_cache_flush_multiple_data_lines(&sc->rx[head], |
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499 | sizeof(sc->rx[head])); |
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500 | |
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501 | /* mark descriptor as empty */ |
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502 | status->status = 0; |
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503 | rtems_cache_flush_multiple_data_lines(&status->status, |
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504 | sizeof(status->status)); |
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505 | |
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506 | /* allow dma to continue from previous descriptor into this |
---|
507 | one */ |
---|
508 | sc->rx[prevHead].status.dmaConfig = DMA_MODE_STATUS; |
---|
509 | rtems_cache_flush_multiple_data_lines( |
---|
510 | &sc->rx[prevHead].status.dmaConfig, |
---|
511 | sizeof(sc->rx[prevHead].status.dmaConfig)); |
---|
512 | |
---|
513 | if (rxPacket) { |
---|
514 | /* send it up */ |
---|
515 | eh = (struct ether_header *) ((intptr_t) dataPtr + 2); |
---|
516 | rxPacket->m_data = (caddr_t) ((intptr_t) dataPtr + 2 + 14); |
---|
517 | length = (rxStatus & EMAC_RX_STAT_RX_FRLEN_MASK) >> |
---|
518 | EMAC_RX_STAT_RX_FRLEN_SHIFT; |
---|
519 | rxPacket->m_len = length - 14; |
---|
520 | rxPacket->m_pkthdr.len = rxPacket->m_len; |
---|
521 | /* invalidate packet buffer cache again (even though it |
---|
522 | was invalidated prior to giving it to dma engine), |
---|
523 | because speculative reads might cause cache lines to |
---|
524 | be filled at any time */ |
---|
525 | rtems_cache_invalidate_multiple_data_lines(eh, length); |
---|
526 | ether_input(ifp, eh, rxPacket); |
---|
527 | } |
---|
528 | |
---|
529 | if (++prevHead == sc->rxDescCount) |
---|
530 | prevHead = 0; |
---|
531 | if (++head == sc->rxDescCount) |
---|
532 | head = 0; |
---|
533 | status = sc->rx[head].status.addr; |
---|
534 | rtems_cache_invalidate_multiple_data_lines(status, sizeof(*status)); |
---|
535 | } |
---|
536 | |
---|
537 | /* if dma stopped before the next descriptor, restart it */ |
---|
538 | if ((BFIN_REG16(rxdmaBase, DMA_IRQ_STATUS_OFFSET) & |
---|
539 | DMA_IRQ_STATUS_DMA_RUN) == 0 && |
---|
540 | BFIN_REG32(rxdmaBase, DMA_NEXT_DESC_PTR_OFFSET) != |
---|
541 | (uint32_t) &sc->rx[head].data) { |
---|
542 | BFIN_REG16(rxdmaBase, DMA_CONFIG_OFFSET) = DMA_MODE_RX; |
---|
543 | } |
---|
544 | |
---|
545 | rtems_bsdnet_event_receive(INTERRUPT_EVENT, RTEMS_WAIT | RTEMS_EVENT_ANY, |
---|
546 | RTEMS_NO_TIMEOUT, &events); |
---|
547 | } |
---|
548 | |
---|
549 | } |
---|
550 | |
---|
551 | /* |
---|
552 | ****************************************************************** |
---|
553 | * * |
---|
554 | * Initialization Routines * |
---|
555 | * * |
---|
556 | ****************************************************************** |
---|
557 | */ |
---|
558 | |
---|
559 | static void resetHardware(struct bfin_ethernetSoftc *sc) { |
---|
560 | void *ethBase; |
---|
561 | void *rxdmaBase; |
---|
562 | void *txdmaBase; |
---|
563 | |
---|
564 | ethBase = sc->ethBase; |
---|
565 | rxdmaBase = sc->rxdmaBase; |
---|
566 | txdmaBase = sc->txdmaBase; |
---|
567 | BFIN_REG32(ethBase, EMAC_OPMODE_OFFSET) = 0; |
---|
568 | BFIN_REG16(rxdmaBase, DMA_CONFIG_OFFSET) = 0; |
---|
569 | BFIN_REG16(txdmaBase, DMA_CONFIG_OFFSET) = 0; |
---|
570 | } |
---|
571 | |
---|
572 | static void initializeHardware(struct bfin_ethernetSoftc *sc) { |
---|
573 | struct ifnet *ifp; |
---|
574 | struct mbuf *m; |
---|
575 | unsigned char *hwaddr; |
---|
576 | int cacheAlignment; |
---|
577 | int rxStatusSize; |
---|
578 | int txStatusSize; |
---|
579 | char *ptr; |
---|
580 | int i; |
---|
581 | void *ethBase; |
---|
582 | void *rxdmaBase; |
---|
583 | void *txdmaBase; |
---|
584 | uint32_t divisor; |
---|
585 | |
---|
586 | ifp = &sc->arpcom.ac_if; |
---|
587 | ethBase = sc->ethBase; |
---|
588 | rxdmaBase = sc->rxdmaBase; |
---|
589 | txdmaBase = sc->txdmaBase; |
---|
590 | |
---|
591 | BFIN_REG32(ethBase, EMAC_OPMODE_OFFSET) = 0; |
---|
592 | BFIN_REG32(ethBase, EMAC_FLC_OFFSET) = 0; |
---|
593 | divisor = (sc->sclk / 25000000) / 2 - 1; |
---|
594 | BFIN_REG32(ethBase, EMAC_SYSCTL_OFFSET) = (divisor << |
---|
595 | EMAC_SYSCTL_MDCDIV_SHIFT) | |
---|
596 | EMAC_SYSCTL_RXDWA; |
---|
597 | #ifdef BFIN_IPCHECKSUMS |
---|
598 | BFIN_REG32(ethBase, EMAC_SYSCTL_OFFSET) |= EMAC_SYSCTL_RXCKS; |
---|
599 | #endif |
---|
600 | BFIN_REG32(ethBase, EMAC_SYSTAT_OFFSET) = ~(uint32_t) 0; |
---|
601 | BFIN_REG32(ethBase, EMAC_RX_IRQE_OFFSET) = 0; |
---|
602 | BFIN_REG32(ethBase, EMAC_RX_STKY_OFFSET) = ~(uint32_t) 0; |
---|
603 | BFIN_REG32(ethBase, EMAC_TX_IRQE_OFFSET) = 0; |
---|
604 | BFIN_REG32(ethBase, EMAC_TX_STKY_OFFSET) = ~(uint32_t) 0; |
---|
605 | BFIN_REG32(ethBase, EMAC_MMC_RIRQE_OFFSET) = 0; |
---|
606 | BFIN_REG32(ethBase, EMAC_MMC_RIRQS_OFFSET) = ~(uint32_t) 0; |
---|
607 | BFIN_REG32(ethBase, EMAC_MMC_TIRQE_OFFSET) = 0; |
---|
608 | BFIN_REG32(ethBase, EMAC_MMC_TIRQS_OFFSET) = ~(uint32_t) 0; |
---|
609 | BFIN_REG32(ethBase, EMAC_MMC_CTL_OFFSET) = EMAC_MMC_CTL_MMCE | |
---|
610 | EMAC_MMC_CTL_CCOR | |
---|
611 | EMAC_MMC_CTL_RSTC; |
---|
612 | BFIN_REG32(ethBase, EMAC_MMC_CTL_OFFSET) = EMAC_MMC_CTL_MMCE | |
---|
613 | EMAC_MMC_CTL_CCOR; |
---|
614 | |
---|
615 | BFIN_REG16(rxdmaBase, DMA_CONFIG_OFFSET) = 0; |
---|
616 | BFIN_REG16(txdmaBase, DMA_CONFIG_OFFSET) = 0; |
---|
617 | BFIN_REG16(rxdmaBase, DMA_X_COUNT_OFFSET) = 0; |
---|
618 | BFIN_REG16(txdmaBase, DMA_X_COUNT_OFFSET) = 0; |
---|
619 | BFIN_REG16(rxdmaBase, DMA_X_MODIFY_OFFSET) = 4; |
---|
620 | BFIN_REG16(txdmaBase, DMA_X_MODIFY_OFFSET) = 4; |
---|
621 | BFIN_REG16(rxdmaBase, DMA_Y_COUNT_OFFSET) = 0; |
---|
622 | BFIN_REG16(txdmaBase, DMA_Y_COUNT_OFFSET) = 0; |
---|
623 | BFIN_REG16(rxdmaBase, DMA_Y_MODIFY_OFFSET) = 0; |
---|
624 | BFIN_REG16(txdmaBase, DMA_Y_MODIFY_OFFSET) = 0; |
---|
625 | BFIN_REG16(rxdmaBase, DMA_IRQ_STATUS_OFFSET) = DMA_IRQ_STATUS_DMA_ERR | |
---|
626 | DMA_IRQ_STATUS_DMA_DONE; |
---|
627 | |
---|
628 | /* The status structures cannot share cache lines with anything else, |
---|
629 | including other status structures, so we can safely manage both the |
---|
630 | processor and DMA writing to them. So this rounds up the structure |
---|
631 | sizes to a multiple of the cache line size. */ |
---|
632 | cacheAlignment = (int) rtems_cache_get_data_line_size(); |
---|
633 | if (cacheAlignment == 0) |
---|
634 | cacheAlignment = 1; |
---|
635 | rxStatusSize = cacheAlignment * ((sizeof(rxStatusT) + cacheAlignment - 1) / |
---|
636 | cacheAlignment); |
---|
637 | txStatusSize = cacheAlignment * ((sizeof(txStatusT) + cacheAlignment - 1) / |
---|
638 | cacheAlignment); |
---|
639 | /* Allocate enough extra to allow structures to start at cache aligned |
---|
640 | boundary. */ |
---|
641 | sc->status = malloc(sc->rxDescCount * rxStatusSize + |
---|
642 | sc->txDescCount * txStatusSize + |
---|
643 | cacheAlignment - 1, M_DEVBUF, M_NOWAIT); |
---|
644 | sc->rx = malloc(sc->rxDescCount * sizeof(*sc->rx), M_DEVBUF, M_NOWAIT); |
---|
645 | sc->tx = malloc(sc->txDescCount * sizeof(*sc->tx), M_DEVBUF, M_NOWAIT); |
---|
646 | if (sc->status == NULL || sc->rx == NULL || sc->tx == NULL) |
---|
647 | rtems_panic("No memory!\n"); |
---|
648 | |
---|
649 | /* Start status structures at cache aligned boundary. */ |
---|
650 | ptr = (char *) (((intptr_t) sc->status + cacheAlignment - 1) & |
---|
651 | ~(cacheAlignment - 1)); |
---|
652 | memset(ptr, 0, sc->rxDescCount * rxStatusSize + |
---|
653 | sc->txDescCount * txStatusSize); |
---|
654 | memset(sc->rx, 0, sc->rxDescCount * sizeof(*sc->rx)); |
---|
655 | memset(sc->tx, 0, sc->txDescCount * sizeof(*sc->tx)); |
---|
656 | rtems_cache_flush_multiple_data_lines(ptr, sc->rxDescCount * rxStatusSize + |
---|
657 | sc->txDescCount * txStatusSize); |
---|
658 | for (i = 0; i < sc->rxDescCount; i++) { |
---|
659 | MGETHDR(m, M_WAIT, MT_DATA); |
---|
660 | MCLGET(m, M_WAIT); |
---|
661 | m->m_pkthdr.rcvif = ifp; |
---|
662 | sc->rx[i].m = m; |
---|
663 | /* start dma at 32 bit boundary */ |
---|
664 | sc->rx[i].data.addr = (void *) (((intptr_t) m->m_data + 3) & ~3); |
---|
665 | rtems_cache_invalidate_multiple_data_lines( |
---|
666 | sc->rx[i].data.addr, |
---|
667 | BFIN_ETHERNET_MAX_FRAME_LENGTH + 2); |
---|
668 | sc->rx[i].data.dmaConfig = DMA_MODE_RX; |
---|
669 | sc->rx[i].data.next = &(sc->rx[i].status); |
---|
670 | sc->rx[i].status.addr = ptr; |
---|
671 | if (i < sc->rxDescCount - 1) { |
---|
672 | sc->rx[i].status.dmaConfig = DMA_MODE_STATUS; |
---|
673 | sc->rx[i].status.next = &(sc->rx[i + 1].data); |
---|
674 | } else { |
---|
675 | sc->rx[i].status.dmaConfig = DMA_MODE_STATUS_LAST; |
---|
676 | sc->rx[i].status.next = &(sc->rx[0].data); |
---|
677 | } |
---|
678 | ptr += rxStatusSize; |
---|
679 | } |
---|
680 | rtems_cache_flush_multiple_data_lines(sc->rx, sc->rxDescCount * |
---|
681 | sizeof(*sc->rx)); |
---|
682 | for (i = 0; i < sc->txDescCount; i++) { |
---|
683 | sc->tx[i].data.addr = &sc->tx[i].buffer.packet; |
---|
684 | sc->tx[i].data.dmaConfig = DMA_MODE_TX; |
---|
685 | sc->tx[i].data.next = &(sc->tx[i].status); |
---|
686 | sc->tx[i].status.addr = ptr; |
---|
687 | sc->tx[i].status.dmaConfig = DMA_MODE_STATUS_LAST; |
---|
688 | if (i < sc->txDescCount - 1) |
---|
689 | sc->tx[i].status.next = &(sc->tx[i + 1].data); |
---|
690 | else |
---|
691 | sc->tx[i].status.next = &(sc->tx[0].data); |
---|
692 | sc->tx[i].inUse = false; |
---|
693 | ptr += txStatusSize; |
---|
694 | } |
---|
695 | rtems_cache_flush_multiple_data_lines(sc->tx, sc->txDescCount * |
---|
696 | sizeof(*sc->tx)); |
---|
697 | |
---|
698 | BFIN_REG32(rxdmaBase, DMA_NEXT_DESC_PTR_OFFSET) = (uint32_t) &sc->rx[0].data; |
---|
699 | BFIN_REG32(txdmaBase, DMA_NEXT_DESC_PTR_OFFSET) = (uint32_t) &sc->tx[0].data; |
---|
700 | |
---|
701 | hwaddr = sc->arpcom.ac_enaddr; |
---|
702 | BFIN_REG16(ethBase, EMAC_ADDRHI_OFFSET) = ((uint16_t) hwaddr[5] << 8) | |
---|
703 | hwaddr[4]; |
---|
704 | BFIN_REG32(ethBase, EMAC_ADDRLO_OFFSET) = ((uint32_t) hwaddr[3] << 24) | |
---|
705 | ((uint32_t) hwaddr[2] << 16) | |
---|
706 | ((uint32_t) hwaddr[1] << 8) | |
---|
707 | hwaddr[0]; |
---|
708 | |
---|
709 | if (sc->acceptBroadcast) |
---|
710 | BFIN_REG32(ethBase, EMAC_OPMODE_OFFSET) &= ~EMAC_OPMODE_DBF; |
---|
711 | else |
---|
712 | BFIN_REG32(ethBase, EMAC_OPMODE_OFFSET) |= EMAC_OPMODE_DBF; |
---|
713 | |
---|
714 | } |
---|
715 | |
---|
716 | /* send packet (caller provides header) */ |
---|
717 | static void ethernetStart(struct ifnet *ifp) { |
---|
718 | struct bfin_ethernetSoftc *sc; |
---|
719 | |
---|
720 | sc = ifp->if_softc; |
---|
721 | |
---|
722 | ifp->if_flags |= IFF_OACTIVE; |
---|
723 | rtems_bsdnet_event_send(sc->txDaemonTid, START_TRANSMIT_EVENT); |
---|
724 | } |
---|
725 | |
---|
726 | /* initialize and start the device */ |
---|
727 | static void ethernetInit(void *arg) { |
---|
728 | struct bfin_ethernetSoftc *sc; |
---|
729 | struct ifnet *ifp; |
---|
730 | void *ethBase; |
---|
731 | |
---|
732 | sc = arg; |
---|
733 | ifp = &sc->arpcom.ac_if; |
---|
734 | ethBase = sc->ethBase; |
---|
735 | |
---|
736 | if (sc->txDaemonTid == 0) { |
---|
737 | initializeHardware(sc); |
---|
738 | |
---|
739 | /* start driver tasks */ |
---|
740 | sc->rxDaemonTid = rtems_bsdnet_newproc("BFrx", 4096, rxDaemon, sc); |
---|
741 | sc->txDaemonTid = rtems_bsdnet_newproc("BFtx", 4096, txDaemon, sc); |
---|
742 | |
---|
743 | } |
---|
744 | |
---|
745 | if (ifp->if_flags & IFF_PROMISC) |
---|
746 | BFIN_REG32(ethBase, EMAC_OPMODE_OFFSET) |= EMAC_OPMODE_PR; |
---|
747 | else |
---|
748 | BFIN_REG32(ethBase, EMAC_OPMODE_OFFSET) &= ~EMAC_OPMODE_PR; |
---|
749 | |
---|
750 | /* |
---|
751 | * Tell the world that we're running. |
---|
752 | */ |
---|
753 | ifp->if_flags |= IFF_RUNNING; |
---|
754 | |
---|
755 | } |
---|
756 | |
---|
757 | /* driver ioctl handler */ |
---|
758 | static int ethernetIoctl(struct ifnet *ifp, ioctl_command_t command, |
---|
759 | caddr_t data) { |
---|
760 | int result; |
---|
761 | struct bfin_ethernetSoftc *sc = ifp->if_softc; |
---|
762 | |
---|
763 | result = 0; |
---|
764 | switch (command) { |
---|
765 | case SIOCGIFADDR: |
---|
766 | case SIOCSIFADDR: |
---|
767 | ether_ioctl(ifp, command, data); |
---|
768 | break; |
---|
769 | case SIOCSIFFLAGS: |
---|
770 | switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { |
---|
771 | case IFF_RUNNING: |
---|
772 | ethernetStop(sc); |
---|
773 | break; |
---|
774 | case IFF_UP: |
---|
775 | ethernetInit(sc); |
---|
776 | break; |
---|
777 | case IFF_UP | IFF_RUNNING: |
---|
778 | ethernetStop(sc); |
---|
779 | ethernetInit(sc); |
---|
780 | break; |
---|
781 | default: |
---|
782 | break; |
---|
783 | } |
---|
784 | break; |
---|
785 | case SIO_RTEMS_SHOW_STATS: |
---|
786 | bfin_ethernetStats(sc); |
---|
787 | break; |
---|
788 | case SIOCADDMULTI: |
---|
789 | case SIOCDELMULTI: |
---|
790 | default: |
---|
791 | result = EINVAL; |
---|
792 | break; |
---|
793 | } |
---|
794 | |
---|
795 | return result; |
---|
796 | } |
---|
797 | |
---|
798 | /* attach a BFIN ETHERNET driver to the system */ |
---|
799 | int bfin_ethernet_driver_attach(struct rtems_bsdnet_ifconfig *config, |
---|
800 | int attaching, |
---|
801 | bfin_ethernet_configuration_t *chip) { |
---|
802 | struct bfin_ethernetSoftc *sc; |
---|
803 | struct ifnet *ifp; |
---|
804 | int mtu; |
---|
805 | int unitNumber; |
---|
806 | char *unitName; |
---|
807 | |
---|
808 | if ((unitNumber = rtems_bsdnet_parse_driver_name(config, &unitName)) < 0) |
---|
809 | return 0; |
---|
810 | |
---|
811 | if ((unitNumber <= 0) || (unitNumber > N_BFIN_ETHERNET)) { |
---|
812 | printf("Bad bfin ethernet unit number %d.\n", unitNumber); |
---|
813 | return 0; |
---|
814 | } |
---|
815 | sc = ðernetSoftc[unitNumber - 1]; |
---|
816 | ifp = &sc->arpcom.ac_if; |
---|
817 | if (ifp->if_softc != NULL) { |
---|
818 | printf("Driver already in use.\n"); |
---|
819 | return 0; |
---|
820 | } |
---|
821 | |
---|
822 | memset(sc, 0, sizeof(*sc)); |
---|
823 | |
---|
824 | /* process options */ |
---|
825 | if (config->hardware_address) |
---|
826 | memcpy(sc->arpcom.ac_enaddr, config->hardware_address, ETHER_ADDR_LEN); |
---|
827 | else |
---|
828 | memset(sc->arpcom.ac_enaddr, 0x08, ETHER_ADDR_LEN); |
---|
829 | if (config->mtu) |
---|
830 | mtu = config->mtu; |
---|
831 | else |
---|
832 | mtu = ETHERMTU; |
---|
833 | if (config->rbuf_count) |
---|
834 | sc->rxDescCount = config->rbuf_count; |
---|
835 | else |
---|
836 | sc->rxDescCount = chip->rxDescCount; |
---|
837 | if (config->xbuf_count) |
---|
838 | sc->txDescCount = config->xbuf_count; |
---|
839 | else |
---|
840 | sc->txDescCount = chip->txDescCount; |
---|
841 | /* minimum two of each type descriptor */ |
---|
842 | if (sc->rxDescCount <= 1) |
---|
843 | sc->rxDescCount = 2; |
---|
844 | if (sc->txDescCount <= 1) |
---|
845 | sc->txDescCount = 2; |
---|
846 | |
---|
847 | sc->acceptBroadcast = !config->ignore_broadcast; |
---|
848 | |
---|
849 | sc->sclk = chip->sclk; |
---|
850 | sc->ethBase = chip->ethBaseAddress; |
---|
851 | sc->rxdmaBase = chip->rxdmaBaseAddress; |
---|
852 | sc->txdmaBase = chip->txdmaBaseAddress; |
---|
853 | |
---|
854 | /* make sure we should not have any interrupts asserted */ |
---|
855 | resetHardware(sc); |
---|
856 | |
---|
857 | sc->rmii = (chip->phyType == rmii); |
---|
858 | sc->phyAddr = chip->phyAddr; |
---|
859 | |
---|
860 | /* set up network interface values */ |
---|
861 | ifp->if_softc = sc; |
---|
862 | ifp->if_unit = unitNumber; |
---|
863 | ifp->if_name = unitName; |
---|
864 | ifp->if_mtu = mtu; |
---|
865 | ifp->if_init = ethernetInit; |
---|
866 | ifp->if_ioctl = ethernetIoctl; |
---|
867 | ifp->if_start = ethernetStart; |
---|
868 | ifp->if_output = ether_output; |
---|
869 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; |
---|
870 | if (ifp->if_snd.ifq_maxlen == 0) |
---|
871 | ifp->if_snd.ifq_maxlen = ifqmaxlen; |
---|
872 | |
---|
873 | if_attach(ifp); |
---|
874 | ether_ifattach(ifp); |
---|
875 | |
---|
876 | return 1; |
---|
877 | } |
---|
878 | |
---|