source: rtems/c/src/lib/libcpu/bfin/include/mmuRegs.h @ f3b29236

5
Last change on this file since f3b29236 was c499856, checked in by Chris Johns <chrisj@…>, on 03/20/14 at 21:10:47

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1/*  Blackfin MMU Registers
2 *
3 *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
4 *             written by Allan Hessenflow <allanh@kallisti.com>
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.org/license/LICENSE.
9 */
10
11#ifndef _mmuRegs_h_
12#define _mmuRegs_h_
13
14/* register addresses */
15#define DCPLB_ADDR0                               0xffe00100
16#define DCPLB_DATA0                               0xffe00200
17#define DCPLB_COUNT                                       16
18#define DCPLB_ADDR_PITCH                                   4
19#define DCPLB_DATA_PITCH                                   4
20#define ICPLB_ADDR0                               0xffe01100
21#define ICPLB_DATA0                               0xffe01200
22#define ICPLB_COUNT                                       16
23#define ICPLB_ADDR_PITCH                                   4
24#define ICPLB_DATA_PITCH                                   4
25
26
27/* register fields */
28#define DCPLB_DATA_PAGE_SIZE_MASK                 0x00030000
29#define DCPLB_DATA_PAGE_SIZE_1KB                  0x00000000
30#define DCPLB_DATA_PAGE_SIZE_4KB                  0x00010000
31#define DCPLB_DATA_PAGE_SIZE_1MB                  0x00020000
32#define DCPLB_DATA_PAGE_SIZE_4MB                  0x00030000
33#define DCPLB_DATA_CPLB_L1_AOW                    0x00008000
34#define DCPLB_DATA_CPLB_WT                        0x00004000
35#define DCPLB_DATA_CPLB_L1_CHBL                   0x00001000
36#define DCPLB_DATA_CPLB_DIRTY                     0x00000080
37#define DCPLB_DATA_CPLB_SUPV_WR                   0x00000010
38#define DCPLB_DATA_CPLB_USER_WR                   0x00000008
39#define DCPLB_DATA_CPLB_USER_RD                   0x00000004
40#define DCPLB_DATA_CPLB_LOCK                      0x00000002
41#define DCPLB_DATA_CPLB_VALID                     0x00000001
42
43#define ICPLB_DATA_PAGE_SIZE_MASK                 0x00030000
44#define ICPLB_DATA_PAGE_SIZE_1KB                  0x00000000
45#define ICPLB_DATA_PAGE_SIZE_4KB                  0x00010000
46#define ICPLB_DATA_PAGE_SIZE_1MB                  0x00020000
47#define ICPLB_DATA_PAGE_SIZE_4MB                  0x00030000
48#define ICPLB_DATA_CPLB_L1_CHBL                   0x00001000
49#define ICPLB_DATA_CPLB_LRUPRIO                   0x00000100
50#define ICPLB_DATA_CPLB_USER_RD                   0x00000004
51#define ICPLB_DATA_CPLB_LOCK                      0x00000002
52#define ICPLB_DATA_CPLB_VALID                     0x00000001
53
54#endif /* _mmuRegs_h_ */
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