source: rtems/c/src/lib/libcpu/bfin/include/memoryRegs.h @ c193baad

4.104.115
Last change on this file since c193baad was 30abd24, checked in by Joel Sherrill <joel.sherrill@…>, on 08/15/08 at 20:18:41

2008-08-15 Allan Hessenflow <allanh@…>

  • ChangeLog?, Makefile.am, README, configure.ac, preinstall.am, cache/cache.c, cache/cache_.h, clock/clock.c, clock/rtc.c, clock/tod.h, include/bf533.h, include/bf537.h, include/cecRegs.h, include/coreTimerRegs.h, include/dmaRegs.h, include/ebiuRegs.h, include/ethernetRegs.h, include/gpioRegs.h, include/memoryRegs.h, include/mmuRegs.h, include/ppiRegs.h, include/rtcRegs.h, include/sicRegs.h, include/spiRegs.h, include/sportRegs.h, include/timerRegs.h, include/twiRegs.h, include/uartRegs.h, include/wdogRegs.h, interrupt/interrupt.c, interrupt/interrupt.h, mmu/mmu.c, mmu/mmu.h, network/ethernet.c, network/ethernet.h, serial/spi.c, serial/spi.h, serial/sport.c, serial/sport.h, serial/twi.c, serial/twi.h, serial/uart.c, serial/uart.h, timer/timer.c: New files.
  • Property mode set to 100644
File size: 2.5 KB
Line 
1/*  Blackfin Memory Registers
2 *
3 *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
4 *             written by Allan Hessenflow <allanh@kallisti.com>
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.com/license/LICENSE.
9 *
10 *  $Id$
11 */
12
13#ifndef _memoryRegs_h_
14#define _memoryRegs_h_
15
16/* register addresses */
17#define DMEM_CONTROL                              0xffe00004
18#define DTEST_COMMAND                             0xffe00300
19#define DTEST_DATA0                               0xffe00400
20#define DTEST_DATA1                               0xffe00404
21
22#define IMEM_CONTROL                              0xffe01004
23
24
25/* register fields */
26#define DMEM_CONTROL_PORT_PREF1                   0x00002000
27#define DMEM_CONTROL_PORT_PREF0                   0x00001000
28#define DMEM_CONTROL_DCBS                         0x00000010
29#define DMEM_CONTROL_DMC_MASK                     0x0000000c
30#define DMEM_CONTROL_DMC_SHIFT                             2
31#define DMEM_CONTROL_ENDCPLB                      0x00000002
32
33#define DTEST_COMMAND_ACCESS_WAY1                 0x02000000
34#define DTEST_COMMAND_ACCESS_INSTRUCTION          0x01000000
35#define DTEST_COMMAND_ACCESS_BANKB                0x00800000
36#define DTEST_COMMAND_SRAM_ADDR_13_12_MASK        0x00030000
37#define DTEST_COMMAND_SRAM_ADDR_13_12_SHIFT               16
38#define DTEST_COMMAND_DATA_CACHE_SELECT           0x00004000
39#define DTEST_COMMAND_SET_INDEX_MASK              0x000007e0
40#define DTEST_COMMAND_SET_INDEX_SHIFT                      5
41#define DTEST_COMMAND_DOUBLE_WORD_INDEX_MASK      0x00000018
42#define DTEST_COMMAND_DOUBLE_WORD_INDEX_SHIFT              3
43#define DTEST_COMMAND_ACCESS_DATA_ARRAY           0x00000004
44#define DTEST_COMMAND_WRITE_ACCESS                0x00000002
45
46#define DTEST_DATA0_TAG_19_2_MASK                 0xffffc000
47#define DTEST_DATA0_TAG_19_2_SHIFT                        14
48#define DTEST_DATA0_TAG                           0x00000800
49#define DTEST_DATA0_LRU                           0x00000004
50#define DTEST_DATA0_DIRTY                         0x00000002
51#define DTEST_DATA0_VALID                         0x00000001
52
53#define IMEM_CONTROL_LRUPRIORST                   0x00002000
54#define IMEM_CONTROL_ILOC_MASK                    0x00000078
55#define IMEM_CONTROL_ILOC_SHIFT                            3
56#define IMEM_CONTROL_IMC                          0x00000004
57#define IMEM_CONTROL_ENICPLB                      0x00000002
58
59
60#endif /* _memoryRegs_h_ */
61
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