| 1 | /* Blackfin Ethernet Registers |
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| 2 | * |
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| 3 | * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA |
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| 4 | * written by Allan Hessenflow <allanh@kallisti.com> |
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| 5 | * |
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| 6 | * The license and distribution terms for this file may be |
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| 7 | * found in the file LICENSE in this distribution or at |
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| 8 | * http://www.rtems.com/license/LICENSE. |
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| 9 | * |
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| 10 | * $Id$ |
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| 11 | */ |
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| 12 | |
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| 13 | #ifndef _ethernetRegs_h_ |
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| 14 | #define _ethernetRegs_h_ |
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| 15 | |
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| 16 | /* register addresses */ |
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| 17 | |
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| 18 | #define EMAC_OPMODE_OFFSET 0x0000 |
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| 19 | #define EMAC_ADDRLO_OFFSET 0x0004 |
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| 20 | #define EMAC_ADDRHI_OFFSET 0x0008 |
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| 21 | #define EMAC_HASHLO_OFFSET 0x000c |
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| 22 | #define EMAC_HASHHI_OFFSET 0x0010 |
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| 23 | #define EMAC_STAADD_OFFSET 0x0014 |
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| 24 | #define EMAC_STADAT_OFFSET 0x0018 |
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| 25 | #define EMAC_FLC_OFFSET 0x001c |
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| 26 | #define EMAC_VLAN1_OFFSET 0x0020 |
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| 27 | #define EMAC_VLAN2_OFFSET 0x0024 |
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| 28 | #define EMAC_WKUP_CTL_OFFSET 0x002c |
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| 29 | #define EMAC_WKUP_FFMSK0_OFFSET 0x0030 |
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| 30 | #define EMAC_WKUP_FFMSK1_OFFSET 0x0034 |
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| 31 | #define EMAC_WKUP_FFMSK2_OFFSET 0x0038 |
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| 32 | #define EMAC_WKUP_FFMSK3_OFFSET 0x003c |
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| 33 | #define EMAC_WKUP_FFCMD_OFFSET 0x0040 |
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| 34 | #define EMAC_WKUP_FFOFF_OFFSET 0x0044 |
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| 35 | #define EMAC_WKUP_FFCRC01_OFFSET 0x0048 |
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| 36 | #define EMAC_WKUP_FFCRC23_OFFSET 0x004c |
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| 37 | #define EMAC_SYSCTL_OFFSET 0x0060 |
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| 38 | #define EMAC_SYSTAT_OFFSET 0x0064 |
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| 39 | #define EMAC_RX_STAT_OFFSET 0x0068 |
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| 40 | #define EMAC_RX_STKY_OFFSET 0x006c |
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| 41 | #define EMAC_RX_IRQE_OFFSET 0x0070 |
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| 42 | #define EMAC_TX_STAT_OFFSET 0x0074 |
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| 43 | #define EMAC_TX_STKY_OFFSET 0x0078 |
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| 44 | #define EMAC_TX_IRQE_OFFSET 0x007c |
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| 45 | #define EMAC_MMC_CTL_OFFSET 0x0080 |
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| 46 | #define EMAC_MMC_RIRQS_OFFSET 0x0084 |
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| 47 | #define EMAC_MMC_RIRQE_OFFSET 0x0088 |
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| 48 | #define EMAC_MMC_TIRQS_OFFSET 0x008c |
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| 49 | #define EMAC_MMC_TIRQE_OFFSET 0x0090 |
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| 50 | |
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| 51 | #define EMAC_RXC_OK_OFFSET 0x0100 |
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| 52 | #define EMAC_RXC_FCS_OFFSET 0x0104 |
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| 53 | #define EMAC_RXC_ALIGN_OFFSET 0x0108 |
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| 54 | #define EMAC_RXC_OCTET_OFFSET 0x010c |
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| 55 | #define EMAC_RXC_DMAOVF_OFFSET 0x0110 |
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| 56 | #define EMAC_RXC_UNICST_OFFSET 0x0114 |
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| 57 | #define EMAC_RXC_MULTI_OFFSET 0x0118 |
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| 58 | #define EMAC_RXC_BROAD_OFFSET 0x011c |
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| 59 | #define EMAC_RXC_LNERRI_OFFSET 0x0120 |
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| 60 | #define EMAC_RXC_LNERRO_OFFSET 0x0124 |
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| 61 | #define EMAC_RXC_LONG_OFFSET 0x0128 |
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| 62 | #define EMAC_RXC_MACCTL_OFFSET 0x012c |
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| 63 | #define EMAC_RXC_OPCODE_OFFSET 0x0130 |
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| 64 | #define EMAC_RXC_PAUSE_OFFSET 0x0134 |
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| 65 | #define EMAC_RXC_ALLFRM_OFFSET 0x0138 |
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| 66 | #define EMAC_RXC_ALLOCT_OFFSET 0x013c |
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| 67 | #define EMAC_RXC_TYPED_OFFSET 0x0140 |
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| 68 | #define EMAC_RXC_SHORT_OFFSET 0x0144 |
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| 69 | #define EMAC_RXC_EQ64_OFFSET 0x0148 |
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| 70 | #define EMAC_RXC_LT128_OFFSET 0x014c |
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| 71 | #define EMAC_RXC_LT256_OFFSET 0x0150 |
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| 72 | #define EMAC_RXC_LT512_OFFSET 0x0154 |
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| 73 | #define EMAC_RXC_LT1024_OFFSET 0x0158 |
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| 74 | #define EMAC_RXC_GE1024_OFFSET 0x015c |
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| 75 | |
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| 76 | #define EMAC_TXC_OK_OFFSET 0x0180 |
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| 77 | #define EMAC_TXC_1COL_OFFSET 0x0184 |
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| 78 | #define EMAC_TXC_GT1COL_OFFSET 0x0188 |
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| 79 | #define EMAC_TXC_OCTET_OFFSET 0x018c |
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| 80 | #define EMAC_TXC_DEFER_OFFSET 0x0190 |
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| 81 | #define EMAC_TXC_LATECL_OFFSET 0x0194 |
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| 82 | #define EMAC_TXC_XS_COL_OFFSET 0x0198 |
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| 83 | #define EMAC_TXC_DMAUND_OFFSET 0x019c |
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| 84 | #define EMAC_TXC_CRSERR_OFFSET 0x01a0 |
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| 85 | #define EMAC_TXC_UNICST_OFFSET 0x01a4 |
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| 86 | #define EMAC_TXC_MULTI_OFFSET 0x01a8 |
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| 87 | #define EMAC_TXC_BROAD_OFFSET 0x01ac |
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| 88 | #define EMAC_TXC_ES_DFR_OFFSET 0x01b0 |
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| 89 | #define EMAC_TXC_MACCTL_OFFSET 0x01b4 |
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| 90 | #define EMAC_TXC_ALLFRM_OFFSET 0x01b8 |
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| 91 | #define EMAC_TXC_ALLOCT_OFFSET 0x01bc |
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| 92 | #define EMAC_TXC_EQ64_OFFSET 0x01c0 |
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| 93 | #define EMAC_TXC_LT128_OFFSET 0x01c4 |
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| 94 | #define EMAC_TXC_LT256_OFFSET 0x01c8 |
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| 95 | #define EMAC_TXC_LT512_OFFSET 0x01cc |
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| 96 | #define EMAC_TXC_LT1024_OFFSET 0x01d0 |
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| 97 | #define EMAC_TXC_GE1024_OFFSET 0x01d4 |
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| 98 | #define EMAC_TXC_ABORT_OFFSET 0x01d8 |
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| 99 | |
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| 100 | |
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| 101 | /* register fields */ |
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| 102 | |
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| 103 | #define EMAC_OPMODE_DRO 0x10000000 |
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| 104 | #define EMAC_OPMODE_LB 0x08000000 |
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| 105 | #define EMAC_OPMODE_FDMODE 0x04000000 |
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| 106 | #define EMAC_OPMODE_RMII_10 0x02000000 |
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| 107 | #define EMAC_OPMODE_RMII 0x01000000 |
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| 108 | #define EMAC_OPMODE_LCTRE 0x00800000 |
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| 109 | #define EMAC_OPMODE_DRTY 0x00400000 |
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| 110 | #define EMAC_OPMODE_BOLMT_MASK 0x00300000 |
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| 111 | #define EMAC_OPMODE_BOLMT_1023 0x00000000 |
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| 112 | #define EMAC_OPMODE_BOLMT_255 0x00100000 |
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| 113 | #define EMAC_OPMODE_BOLMT_15 0x00200000 |
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| 114 | #define EMAC_OPMODE_BOLMT_1 0x00300000 |
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| 115 | #define EMAC_OPMODE_DC 0x00080000 |
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| 116 | #define EMAC_OPMODE_DTXCRC 0x00040000 |
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| 117 | #define EMAC_OPMODE_DTXPAD 0x00020000 |
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| 118 | #define EMAC_OPMODE_TE 0x00010000 |
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| 119 | #define EMAC_OPMODE_RAF 0x00001000 |
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| 120 | #define EMAC_OPMODE_PSF 0x00000800 |
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| 121 | #define EMAC_OPMODE_PBF 0x00000400 |
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| 122 | #define EMAC_OPMODE_DBF 0x00000200 |
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| 123 | #define EMAC_OPMODE_IFE 0x00000100 |
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| 124 | #define EMAC_OPMODE_PR 0x00000080 |
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| 125 | #define EMAC_OPMODE_PAM 0x00000040 |
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| 126 | #define EMAC_OPMODE_HM 0x00000020 |
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| 127 | #define EMAC_OPMODE_HU 0x00000010 |
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| 128 | #define EMAC_OPMODE_ASTP 0x00000002 |
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| 129 | #define EMAC_OPMODE_RE 0x00000001 |
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| 130 | |
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| 131 | #define EMAC_STAADD_PHYAD_MASK 0x0000f800 |
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| 132 | #define EMAC_STAADD_PHYAD_SHIFT 11 |
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| 133 | #define EMAC_STAADD_REGAD_MASK 0x000007c0 |
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| 134 | #define EMAC_STAADD_REGAD_SHIFT 6 |
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| 135 | #define EMAC_STAADD_STAIE 0x00000008 |
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| 136 | #define EMAC_STAADD_STADISPRE 0x00000004 |
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| 137 | #define EMAC_STAADD_STAOP 0x00000002 |
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| 138 | #define EMAC_STAADD_STABUSY 0x00000001 |
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| 139 | |
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| 140 | #define EMAC_FLC_FLCPAUSE_MASK 0xffff0000 |
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| 141 | #define EMAC_FLC_FLCPAUSE_SHIFT 16 |
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| 142 | #define EMAC_FLC_BKPRSEN 0x00000008 |
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| 143 | #define EMAC_FLC_PCF 0x00000004 |
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| 144 | #define EMAC_FLC_FLCE 0x00000002 |
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| 145 | #define EMAC_FLC_FLCBUSY 0x00000001 |
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| 146 | |
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| 147 | #define EMAC_WKUP_CTL_RWKS_MASK 0x00000f00 |
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| 148 | #define EMAC_WKUP_CTL_RWKS_SHIFT 8 |
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| 149 | #define EMAC_WKUP_CTL_MPKS 0x00000020 |
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| 150 | #define EMAC_WKUP_CTL_GUWKE 0x00000008 |
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| 151 | #define EMAC_WKUP_CTL_RWKE 0x00000004 |
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| 152 | #define EMAC_WKUP_CTL_MPKE 0x00000002 |
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| 153 | #define EMAC_WKUP_CTL_CAPWKFRM 0x00000001 |
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| 154 | |
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| 155 | #define EMAC_WKUP_FFCMD_3_TYPE 0x08000000 |
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| 156 | #define EMAC_WKUP_FFCMD_3_EN 0x01000000 |
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| 157 | #define EMAC_WKUP_FFCMD_2_TYPE 0x00080000 |
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| 158 | #define EMAC_WKUP_FFCMD_2_EN 0x00010000 |
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| 159 | #define EMAC_WKUP_FFCMD_1_TYPE 0x00000800 |
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| 160 | #define EMAC_WKUP_FFCMD_1_EN 0x00000100 |
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| 161 | #define EMAC_WKUP_FFCMD_0_TYPE 0x00000008 |
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| 162 | #define EMAC_WKUP_FFCMD_0_EN 0x00000001 |
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| 163 | |
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| 164 | #define EMAC_WKUP_FFOFF_3_MASK 0xff000000 |
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| 165 | #define EMAC_WKUP_FFOFF_3_SHIFT 24 |
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| 166 | #define EMAC_WKUP_FFOFF_2_MASK 0x00ff0000 |
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| 167 | #define EMAC_WKUP_FFOFF_2_SHIFT 16 |
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| 168 | #define EMAC_WKUP_FFOFF_1_MASK 0x0000ff00 |
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| 169 | #define EMAC_WKUP_FFOFF_1_SHIFT 8 |
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| 170 | #define EMAC_WKUP_FFOFF_0_MASK 0x000000ff |
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| 171 | #define EMAC_WKUP_FFOFF_0_SHIFT 0 |
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| 172 | |
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| 173 | #define EMAC_WKUP_FFCRC01_1_MASK 0xffff0000 |
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| 174 | #define EMAC_WKUP_FFCRC01_1_SHIFT 16 |
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| 175 | #define EMAC_WKUP_FFCRC01_0_MASK 0x0000ffff |
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| 176 | #define EMAC_WKUP_FFCRC01_0_SHIFT 0 |
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| 177 | |
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| 178 | #define EMAC_WKUP_FFCRC23_3_MASK 0xffff0000 |
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| 179 | #define EMAC_WKUP_FFCRC23_3_SHIFT 16 |
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| 180 | #define EMAC_WKUP_FFCRC23_2_MASK 0x0000ffff |
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| 181 | #define EMAC_WKUP_FFCRC23_2_SHIFT 0 |
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| 182 | |
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| 183 | #define EMAC_SYSCTL_MDCDIV_MASK 0x00003f00 |
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| 184 | #define EMAC_SYSCTL_MDCDIV_SHIFT 8 |
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| 185 | #define EMAC_SYSCTL_TXDWA 0x00000010 |
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| 186 | #define EMAC_SYSCTL_RXCKS 0x00000004 |
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| 187 | #define EMAC_SYSCTL_RXDWA 0x00000002 |
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| 188 | #define EMAC_SYSCTL_PHYIE 0x00000001 |
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| 189 | |
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| 190 | #define EMAC_SYSTAT_STMDONE 0x00000080 |
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| 191 | #define EMAC_SYSTAT_TXDMAERR 0x00000040 |
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| 192 | #define EMAC_SYSTAT_RXDMAERR 0x00000020 |
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| 193 | #define EMAC_SYSTAT_WAKEDET 0x00000010 |
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| 194 | #define EMAC_SYSTAT_TXFSINT 0x00000008 |
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| 195 | #define EMAC_SYSTAT_RXFSINT 0x00000004 |
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| 196 | #define EMAC_SYSTAT_MMCINT 0x00000002 |
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| 197 | #define EMAC_SYSTAT_PHYINT 0x00000001 |
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| 198 | |
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| 199 | #define EMAC_RX_STAT_RX_ACCEPT 0x80000000 |
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| 200 | #define EMAC_RX_STAT_RX_VLAN2 0x40000000 |
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| 201 | #define EMAC_RX_STAT_RX_VLAN1 0x20000000 |
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| 202 | #define EMAC_RX_STAT_RX_TYPE 0x10000000 |
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| 203 | #define EMAC_RX_STAT_RX_UCTL 0x08000000 |
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| 204 | #define EMAC_RX_STAT_RX_CTL 0x04000000 |
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| 205 | #define EMAC_RX_STAT_RX_BROAD_MULTI_MASK 0x03000000 |
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| 206 | #define EMAC_RX_STAT_RX_BROAD_MULTI_ILLEGAL 0x03000000 |
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| 207 | #define EMAC_RX_STAT_RX_BROAD_MULTI_BROADCAST 0x02000000 |
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| 208 | #define EMAC_RX_STAT_RX_BROAD_MULTI_GROUP 0x01000000 |
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| 209 | #define EMAC_RX_STAT_RX_BROAD_MULTI_UNICAST 0x00000000 |
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| 210 | #define EMAC_RX_STAT_RX_RANGE 0x00800000 |
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| 211 | #define EMAC_RX_STAT_RX_LATE 0x00400000 |
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| 212 | #define EMAC_RX_STAT_RX_PHY 0x00200000 |
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| 213 | #define EMAC_RX_STAT_RX_DMAO 0x00100000 |
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| 214 | #define EMAC_RX_STAT_RX_ADDR 0x00080000 |
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| 215 | #define EMAC_RX_STAT_RX_FRAG 0x00040000 |
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| 216 | #define EMAC_RX_STAT_RX_LEN 0x00020000 |
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| 217 | #define EMAC_RX_STAT_RX_CRC 0x00010000 |
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| 218 | #define EMAC_RX_STAT_RX_ALIGN 0x00008000 |
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| 219 | #define EMAC_RX_STAT_RX_LONG 0x00004000 |
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| 220 | #define EMAC_RX_STAT_RX_OK 0x00002000 |
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| 221 | #define EMAC_RX_STAT_RX_COMP 0x00001000 |
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| 222 | #define EMAC_RX_STAT_RX_FRLEN_MASK 0x000007ff |
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| 223 | #define EMAC_RX_STAT_RX_FRLEN_SHIFT 0 |
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| 224 | |
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| 225 | #define EMAC_RX_STKY_RX_ACCEPT 0x80000000 |
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| 226 | #define EMAC_RX_STKY_RX_VLAN2 0x40000000 |
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| 227 | #define EMAC_RX_STKY_RX_VLAN1 0x20000000 |
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| 228 | #define EMAC_RX_STKY_RX_TYPE 0x10000000 |
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| 229 | #define EMAC_RX_STKY_RX_UCTL 0x08000000 |
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| 230 | #define EMAC_RX_STKY_RX_CTL 0x04000000 |
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| 231 | #define EMAC_RX_STKY_RX_BROAD 0x02000000 |
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| 232 | #define EMAC_RX_STKY_RX_MULTI 0x01000000 |
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| 233 | #define EMAC_RX_STKY_RX_RANGE 0x00800000 |
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| 234 | #define EMAC_RX_STKY_RX_LATE 0x00400000 |
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| 235 | #define EMAC_RX_STKY_RX_PHY 0x00200000 |
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| 236 | #define EMAC_RX_STKY_RX_DMAO 0x00100000 |
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| 237 | #define EMAC_RX_STKY_RX_ADDR 0x00080000 |
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| 238 | #define EMAC_RX_STKY_RX_FRAG 0x00040000 |
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| 239 | #define EMAC_RX_STKY_RX_LEN 0x00020000 |
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| 240 | #define EMAC_RX_STKY_RX_CRC 0x00010000 |
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| 241 | #define EMAC_RX_STKY_RX_ALIGN 0x00008000 |
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| 242 | #define EMAC_RX_STKY_RX_LONG 0x00004000 |
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| 243 | #define EMAC_RX_STKY_RX_OK 0x00002000 |
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| 244 | #define EMAC_RX_STKY_RX_COMP 0x00001000 |
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| 245 | |
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| 246 | #define EMAC_RX_IRQE_RX_ACCEPT 0x80000000 |
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| 247 | #define EMAC_RX_IRQE_RX_VLAN2 0x40000000 |
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| 248 | #define EMAC_RX_IRQE_RX_VLAN1 0x20000000 |
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| 249 | #define EMAC_RX_IRQE_RX_TYPE 0x10000000 |
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| 250 | #define EMAC_RX_IRQE_RX_UCTL 0x08000000 |
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| 251 | #define EMAC_RX_IRQE_RX_CTL 0x04000000 |
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| 252 | #define EMAC_RX_IRQE_RX_BROAD 0x02000000 |
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| 253 | #define EMAC_RX_IRQE_RX_MULTI 0x01000000 |
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| 254 | #define EMAC_RX_IRQE_RX_RANGE 0x00800000 |
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| 255 | #define EMAC_RX_IRQE_RX_LATE 0x00400000 |
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| 256 | #define EMAC_RX_IRQE_RX_PHY 0x00200000 |
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| 257 | #define EMAC_RX_IRQE_RX_DMAO 0x00100000 |
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| 258 | #define EMAC_RX_IRQE_RX_ADDR 0x00080000 |
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| 259 | #define EMAC_RX_IRQE_RX_FRAG 0x00040000 |
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| 260 | #define EMAC_RX_IRQE_RX_LEN 0x00020000 |
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| 261 | #define EMAC_RX_IRQE_RX_CRC 0x00010000 |
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| 262 | #define EMAC_RX_IRQE_RX_ALIGN 0x00008000 |
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| 263 | #define EMAC_RX_IRQE_RX_LONG 0x00004000 |
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| 264 | #define EMAC_RX_IRQE_RX_OK 0x00002000 |
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| 265 | #define EMAC_RX_IRQE_RX_COMP 0x00001000 |
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| 266 | |
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| 267 | #define EMAC_TX_STAT_TX_FRLEN_MASK 0x07ff0000 |
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| 268 | #define EMAC_TX_STAT_TX_FRLEN_SHIFT 16 |
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| 269 | #define EMAC_TX_STAT_TX_RETRY 0x00008000 |
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| 270 | #define EMAC_TX_STAT_TX_LOSS 0x00004000 |
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| 271 | #define EMAC_TX_STAT_TX_CRS 0x00002000 |
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| 272 | #define EMAC_TX_STAT_TX_DEFER 0x00001000 |
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| 273 | #define EMAC_TX_STAT_TX_CCNT_MASK 0x00000f00 |
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| 274 | #define EMAC_TX_STAT_TX_CCNT_SHIFT 8 |
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| 275 | #define EMAC_TX_STAT_TX_MULTI_BROAD_MASK 0x000000c0 |
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| 276 | #define EMAC_TX_STAT_TX_MULTI_BROAD_ILLEGAL 0x000000c0 |
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| 277 | #define EMAC_TX_STAT_TX_MULTI_BROAD_GROUP 0x00000080 |
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| 278 | #define EMAC_TX_STAT_TX_MULTI_BROAD_BROADCAST 0x00000040 |
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| 279 | #define EMAC_TX_STAT_TX_MULTI_BROAD_UNICAST 0x00000000 |
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| 280 | #define EMAC_TX_STAT_TX_EDEFER 0x00000020 |
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| 281 | #define EMAC_TX_STAT_TX_DMAU 0x00000010 |
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| 282 | #define EMAC_TX_STAT_TX_LATE 0x00000008 |
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| 283 | #define EMAC_TX_STAT_TX_ECOLL 0x00000004 |
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| 284 | #define EMAC_TX_STAT_TX_OK 0x00000002 |
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| 285 | #define EMAC_TX_STAT_TX_COMP 0x00000001 |
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| 286 | |
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| 287 | #define EMAC_TX_STKY_TX_RETRY 0x00008000 |
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| 288 | #define EMAC_TX_STKY_TX_LOSS 0x00004000 |
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| 289 | #define EMAC_TX_STKY_TX_CRS 0x00002000 |
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| 290 | #define EMAC_TX_STKY_TX_DEFER 0x00001000 |
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| 291 | #define EMAC_TX_STKY_TX_CCNT_MASK 0x00000f00 |
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| 292 | #define EMAC_TX_STKY_TX_CCNT_SHIFT 8 |
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| 293 | #define EMAC_TX_STKY_TX_MULTI 0x00000080 |
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| 294 | #define EMAC_TX_STKY_TX_BROAD 0x00000040 |
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| 295 | #define EMAC_TX_STKY_TX_EDEFER 0x00000020 |
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| 296 | #define EMAC_TX_STKY_TX_DMAU 0x00000010 |
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| 297 | #define EMAC_TX_STKY_TX_LATE 0x00000008 |
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| 298 | #define EMAC_TX_STAT_TX_ECOLL 0x00000004 |
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| 299 | #define EMAC_TX_STAT_TX_OK 0x00000002 |
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| 300 | #define EMAC_TX_STAT_TX_COMP 0x00000001 |
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| 301 | |
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| 302 | #define EMAC_TX_IRQE_TX_RETRY 0x00008000 |
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| 303 | #define EMAC_TX_IRQE_TX_LOSS 0x00004000 |
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| 304 | #define EMAC_TX_IRQE_TX_CRS 0x00002000 |
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| 305 | #define EMAC_TX_IRQE_TX_DEFER 0x00001000 |
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| 306 | #define EMAC_TX_IRQE_TX_CCNT_MASK 0x00000f00 |
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| 307 | #define EMAC_TX_IRQE_TX_CCNT_SHIFT 8 |
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| 308 | #define EMAC_TX_IRQE_TX_MULTI 0x00000080 |
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| 309 | #define EMAC_TX_IRQE_TX_BROAD 0x00000040 |
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| 310 | #define EMAC_TX_IRQE_TX_EDEFER 0x00000020 |
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| 311 | #define EMAC_TX_IRQE_TX_DMAU 0x00000010 |
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| 312 | #define EMAC_TX_IRQE_TX_LATE 0x00000008 |
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| 313 | #define EMAC_TX_IRQE_TX_ECOLL 0x00000004 |
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| 314 | #define EMAC_TX_IRQE_TX_OK 0x00000002 |
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| 315 | #define EMAC_TX_IRQE_TX_COMP 0x00000001 |
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| 316 | |
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| 317 | #define EMAC_MMC_RIRQS_RX_GE1024_CNT 0x00800000 |
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| 318 | #define EMAC_MMC_RIRQS_RX_LT1024_CNT 0x00400000 |
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| 319 | #define EMAC_MMC_RIRQS_RX_LT512_CNT 0x00200000 |
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| 320 | #define EMAC_MMC_RIRQS_RX_LT256_CNT 0x00100000 |
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| 321 | #define EMAC_MMC_RIRQS_RX_LT128_CNT 0x00080000 |
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| 322 | #define EMAC_MMC_RIRQS_RX_EQ64_CNT 0x00040000 |
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| 323 | #define EMAC_MMC_RIRQS_RX_SHORT_CNT 0x00020000 |
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| 324 | #define EMAC_MMC_RIRQS_RX_TYPED_CNT 0x00010000 |
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| 325 | #define EMAC_MMC_RIRQS_RX_ALLO_CNT 0x00008000 |
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| 326 | #define EMAC_MMC_RIRQS_RX_ALLF_CNT 0x00004000 |
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| 327 | #define EMAC_MMC_RIRQS_RX_PAUSE_CNT 0x00002000 |
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| 328 | #define EMAC_MMC_RIRQS_RX_OPCODE_CNT 0x00001000 |
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| 329 | #define EMAC_MMC_RIRQS_RX_MACCTL_CNT 0x00000800 |
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| 330 | #define EMAC_MMC_RIRQS_RX_LONG_CNT 0x00000400 |
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| 331 | #define EMAC_MMC_RIRQS_RX_ORL_CNT 0x00000200 |
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| 332 | #define EMAC_MMC_RIRQS_RX_IRL_CNT 0x00000100 |
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| 333 | #define EMAC_MMC_RIRQS_RX_BROAD_CNT 0x00000080 |
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| 334 | #define EMAC_MMC_RIRQS_RX_MULTI_CNT 0x00000040 |
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| 335 | #define EMAC_MMC_RIRQS_RX_UNI_CNT 0x00000020 |
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| 336 | #define EMAC_MMC_RIRQS_RX_LOST_CNT 0x00000010 |
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| 337 | #define EMAC_MMC_RIRQS_RX_OCTET_CNT 0x00000008 |
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| 338 | #define EMAC_MMC_RIRQS_RX_ALIGN_CNT 0x00000004 |
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| 339 | #define EMAC_MMC_RIRQS_RX_FCS_CNT 0x00000002 |
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| 340 | #define EMAC_MMC_RIRQS_RX_OK_CNT 0x00000001 |
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| 341 | |
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| 342 | #define EMAC_MMC_RIRQE_RX_GE1024_CNT 0x00800000 |
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| 343 | #define EMAC_MMC_RIRQE_RX_LT1024_CNT 0x00400000 |
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| 344 | #define EMAC_MMC_RIRQE_RX_LT512_CNT 0x00200000 |
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| 345 | #define EMAC_MMC_RIRQE_RX_LT256_CNT 0x00100000 |
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| 346 | #define EMAC_MMC_RIRQE_RX_LT128_CNT 0x00080000 |
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| 347 | #define EMAC_MMC_RIRQE_RX_EQ64_CNT 0x00040000 |
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| 348 | #define EMAC_MMC_RIRQE_RX_SHORT_CNT 0x00020000 |
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| 349 | #define EMAC_MMC_RIRQE_RX_TYPED_CNT 0x00010000 |
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| 350 | #define EMAC_MMC_RIRQE_RX_ALLO_CNT 0x00008000 |
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| 351 | #define EMAC_MMC_RIRQE_RX_ALLF_CNT 0x00004000 |
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| 352 | #define EMAC_MMC_RIRQE_RX_PAUSE_CNT 0x00002000 |
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| 353 | #define EMAC_MMC_RIRQE_RX_OPCODE_CNT 0x00001000 |
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| 354 | #define EMAC_MMC_RIRQE_RX_MACCTL_CNT 0x00000800 |
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| 355 | #define EMAC_MMC_RIRQE_RX_LONG_CNT 0x00000400 |
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| 356 | #define EMAC_MMC_RIRQE_RX_ORL_CNT 0x00000200 |
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| 357 | #define EMAC_MMC_RIRQE_RX_IRL_CNT 0x00000100 |
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| 358 | #define EMAC_MMC_RIRQE_RX_BROAD_CNT 0x00000080 |
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| 359 | #define EMAC_MMC_RIRQE_RX_MULTI_CNT 0x00000040 |
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| 360 | #define EMAC_MMC_RIRQE_RX_UNI_CNT 0x00000020 |
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| 361 | #define EMAC_MMC_RIRQE_RX_LOST_CNT 0x00000010 |
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| 362 | #define EMAC_MMC_RIRQE_RX_OCTET_CNT 0x00000008 |
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| 363 | #define EMAC_MMC_RIRQE_RX_ALIGN_CNT 0x00000004 |
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| 364 | #define EMAC_MMC_RIRQE_RX_FCS_CNT 0x00000002 |
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| 365 | #define EMAC_MMC_RIRQE_RX_OK_CNT 0x00000001 |
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| 366 | |
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| 367 | #define EMAC_MMC_TIRQS_TX_ABORT_CNT 0x00400000 |
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| 368 | #define EMAC_MMC_TIRQS_TX_GE1024_CNT 0x00200000 |
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| 369 | #define EMAC_MMC_TIRQS_TX_LT1024_CNT 0x00100000 |
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| 370 | #define EMAC_MMC_TIRQS_TX_LT512_CNT 0x00080000 |
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| 371 | #define EMAC_MMC_TIRQS_TX_LT256_CNT 0x00040000 |
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| 372 | #define EMAC_MMC_TIRQS_TX_LT128_CNT 0x00020000 |
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| 373 | #define EMAC_MMC_TIRQS_TX_EQ64_CNT 0x00010000 |
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| 374 | #define EMAC_MMC_TIRQS_TX_ALLO_CNT 0x00008000 |
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| 375 | #define EMAC_MMC_TIRQS_TX_ALLF_CNT 0x00004000 |
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| 376 | #define EMAC_MMC_TIRQS_TX_MACCTL_CNT 0x00002000 |
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| 377 | #define EMAC_MMC_TIRQS_TX_EXDEF_CNT 0x00001000 |
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| 378 | #define EMAC_MMC_TIRQS_TX_BROAD_CNT 0x00000800 |
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| 379 | #define EMAC_MMC_TIRQS_TX_MULTI_CNT 0x00000400 |
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| 380 | #define EMAC_MMC_TIRQS_TX_UNI_CNT 0x00000200 |
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| 381 | #define EMAC_MMC_TIRQS_TX_CRS_CNT 0x00000100 |
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| 382 | #define EMAC_MMC_TIRQS_TX_LOST_CNT 0x00000080 |
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| 383 | #define EMAC_MMC_TIRQS_TX_ABORTC_CNT 0x00000040 |
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| 384 | #define EMAC_MMC_TIRQS_TX_LATE_CNT 0x00000020 |
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| 385 | #define EMAC_MMC_TIRQS_TX_DEFER_CNT 0x00000010 |
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| 386 | #define EMAC_MMC_TIRQS_TX_OCTET_CNT 0x00000008 |
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| 387 | #define EMAC_MMC_TIRQS_TX_MCOLL_CNT 0x00000004 |
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| 388 | #define EMAC_MMC_TIRQS_TX_SCOLL_CNT 0x00000002 |
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| 389 | #define EMAC_MMC_TIRQS_TX_OK_CNT 0x00000001 |
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| 390 | |
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| 391 | #define EMAC_MMC_TIRQE_TX_ABORT_CNT 0x00400000 |
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| 392 | #define EMAC_MMC_TIRQE_TX_GE1024_CNT 0x00200000 |
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| 393 | #define EMAC_MMC_TIRQE_TX_LT1024_CNT 0x00100000 |
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| 394 | #define EMAC_MMC_TIRQE_TX_LT512_CNT 0x00080000 |
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| 395 | #define EMAC_MMC_TIRQE_TX_LT256_CNT 0x00040000 |
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| 396 | #define EMAC_MMC_TIRQE_TX_LT128_CNT 0x00020000 |
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| 397 | #define EMAC_MMC_TIRQE_TX_EQ64_CNT 0x00010000 |
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| 398 | #define EMAC_MMC_TIRQE_TX_ALLO_CNT 0x00008000 |
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| 399 | #define EMAC_MMC_TIRQE_TX_ALLF_CNT 0x00004000 |
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| 400 | #define EMAC_MMC_TIRQE_TX_MACCTL_CNT 0x00002000 |
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| 401 | #define EMAC_MMC_TIRQE_TX_EXDEF_CNT 0x00001000 |
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| 402 | #define EMAC_MMC_TIRQE_TX_BROAD_CNT 0x00000800 |
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| 403 | #define EMAC_MMC_TIRQE_TX_MULTI_CNT 0x00000400 |
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| 404 | #define EMAC_MMC_TIRQE_TX_UNI_CNT 0x00000200 |
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| 405 | #define EMAC_MMC_TIRQE_TX_CRS_CNT 0x00000100 |
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| 406 | #define EMAC_MMC_TIRQE_TX_LOST_CNT 0x00000080 |
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| 407 | #define EMAC_MMC_TIRQE_TX_ABORTC_CNT 0x00000040 |
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| 408 | #define EMAC_MMC_TIRQE_TX_LATE_CNT 0x00000020 |
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| 409 | #define EMAC_MMC_TIRQE_TX_DEFER_CNT 0x00000010 |
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| 410 | #define EMAC_MMC_TIRQE_TX_OCTET_CNT 0x00000008 |
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| 411 | #define EMAC_MMC_TIRQE_TX_MCOLL_CNT 0x00000004 |
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| 412 | #define EMAC_MMC_TIRQE_TX_SCOLL_CNT 0x00000002 |
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| 413 | #define EMAC_MMC_TIRQE_TX_OK_CNT 0x00000001 |
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| 414 | |
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| 415 | #define EMAC_MMC_CTL_MMCE 0x00000008 |
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| 416 | #define EMAC_MMC_CTL_CCOR 0x00000004 |
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| 417 | #define EMAC_MMC_CTL_CROLL 0x00000002 |
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| 418 | #define EMAC_MMC_CTL_RSTC 0x00000001 |
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| 419 | |
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| 420 | |
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| 421 | #endif /* _ethernetRegs_h_ */ |
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| 422 | |
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