1 | /* Blackfin External Peripheral Interface Registers |
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2 | * |
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3 | * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA |
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4 | * written by Allan Hessenflow <allanh@kallisti.com> |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.com/license/LICENSE. |
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9 | */ |
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10 | |
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11 | #ifndef _ebiuRegs_h_ |
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12 | #define _ebiuRegs_h_ |
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13 | |
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14 | /* register addresses */ |
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15 | |
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16 | #define EBIU_AMGCTL (EBIU_BASE_ADDRESS + 0x0000) |
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17 | #define EBIU_AMBCTL0 (EBIU_BASE_ADDRESS + 0x0004) |
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18 | #define EBIU_AMBCTL1 (EBIU_BASE_ADDRESS + 0x0008) |
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19 | #define EBIU_SDGCTL (EBIU_BASE_ADDRESS + 0x0010) |
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20 | #define EBIU_SDBCTL (EBIU_BASE_ADDRESS + 0x0014) |
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21 | #define EBIU_SDRRC (EBIU_BASE_ADDRESS + 0x0018) |
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22 | #define EBIU_SDSTAT (EBIU_BASE_ADDRESS + 0x001c) |
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23 | |
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24 | /* register fields */ |
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25 | |
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26 | #define EBIU_AMGCTL_CDPRIO 0x0100 |
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27 | #define EBIU_AMGCTL_AMBEN_MASK 0x000e |
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28 | #define EBIU_AMGCTL_AMBEN_SHIFT 1 |
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29 | #define EBIU_AMGCTL_AMCKEN 0x0001 |
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30 | |
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31 | #define EBIU_AMBCTL0_B1WAT_MASK 0xf0000000 |
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32 | #define EBIU_AMBCTL0_B1WAT_SHIFT 28 |
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33 | #define EBIU_AMBCTL0_B1RAT_MASK 0x0f000000 |
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34 | #define EBIU_AMBCTL0_B1RAT_SHIFT 24 |
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35 | #define EBIU_AMBCTL0_B1HT_MASK 0x00c00000 |
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36 | #define EBIU_AMBCTL0_B1HT_SHIFT 22 |
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37 | #define EBIU_AMBCTL0_B1ST_MASK 0x00300000 |
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38 | #define EBIU_AMBCTL0_B1ST_SHIFT 20 |
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39 | #define EBIU_AMBCTL0_B1TT_MASK 0x000c0000 |
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40 | #define EBIU_AMBCTL0_B1TT_SHIFT 18 |
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41 | #define EBIU_AMBCTL0_B1RDYPOL 0x00020000 |
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42 | #define EBIU_AMBCTL0_B1RDYEN 0x00010000 |
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43 | #define EBIU_AMBCTL0_B0WAT_MASK 0x0000f000 |
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44 | #define EBIU_AMBCTL0_B0WAT_SHIFT 12 |
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45 | #define EBIU_AMBCTL0_B0RAT_MASK 0x00000f00 |
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46 | #define EBIU_AMBCTL0_B0RAT_SHIFT 8 |
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47 | #define EBIU_AMBCTL0_B0HT_MASK 0x000000c0 |
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48 | #define EBIU_AMBCTL0_B0HT_SHIFT 6 |
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49 | #define EBIU_AMBCTL0_B0ST_MASK 0x00000030 |
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50 | #define EBIU_AMBCTL0_B0ST_SHIFT 4 |
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51 | #define EBIU_AMBCTL0_B0TT_MASK 0x0000000c |
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52 | #define EBIU_AMBCTL0_B0TT_SHIFT 2 |
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53 | #define EBIU_AMBCTL0_B0RDYPOL 0x00000002 |
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54 | #define EBIU_AMBCTL0_B0RDYEN 0x00000001 |
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55 | |
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56 | #define EBIU_AMBCTL1_B3WAT_MASK 0xf0000000 |
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57 | #define EBIU_AMBCTL1_B3WAT_SHIFT 28 |
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58 | #define EBIU_AMBCTL1_B3RAT_MASK 0x0f000000 |
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59 | #define EBIU_AMBCTL1_B3RAT_SHIFT 24 |
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60 | #define EBIU_AMBCTL1_B3HT_MASK 0x00c00000 |
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61 | #define EBIU_AMBCTL1_B3HT_SHIFT 22 |
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62 | #define EBIU_AMBCTL1_B3ST_MASK 0x00300000 |
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63 | #define EBIU_AMBCTL1_B3ST_SHIFT 20 |
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64 | #define EBIU_AMBCTL1_B3TT_MASK 0x000c0000 |
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65 | #define EBIU_AMBCTL1_B3TT_SHIFT 18 |
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66 | #define EBIU_AMBCTL1_B3RDYPOL 0x00020000 |
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67 | #define EBIU_AMBCTL1_B3RDYEN 0x00010000 |
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68 | #define EBIU_AMBCTL1_B2WAT_MASK 0x0000f000 |
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69 | #define EBIU_AMBCTL1_B2WAT_SHIFT 12 |
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70 | #define EBIU_AMBCTL1_B2RAT_MASK 0x00000f00 |
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71 | #define EBIU_AMBCTL1_B2RAT_SHIFT 8 |
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72 | #define EBIU_AMBCTL1_B2HT_MASK 0x000000c0 |
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73 | #define EBIU_AMBCTL1_B2HT_SHIFT 6 |
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74 | #define EBIU_AMBCTL1_B2ST_MASK 0x00000030 |
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75 | #define EBIU_AMBCTL1_B2ST_SHIFT 4 |
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76 | #define EBIU_AMBCTL1_B2TT_MASK 0x0000000c |
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77 | #define EBIU_AMBCTL1_B2TT_SHIFT 2 |
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78 | #define EBIU_AMBCTL1_B2RDYPOL 0x00000002 |
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79 | #define EBIU_AMBCTL1_B2RDYEN 0x00000001 |
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80 | |
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81 | #define EBIU_SDGCTL_CDDBG 0x40000000 |
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82 | #define EBIU_SDGCTL_TCSR 0x20000000 |
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83 | #define EBIU_SDGCTL_EMREN 0x10000000 |
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84 | #define EBIU_SDGCTL_FBBRW 0x04000000 |
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85 | #define EBIU_SDGCTL_EBUFE 0x02000000 |
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86 | #define EBIU_SDGCTL_SRFS 0x01000000 |
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87 | #define EBIU_SDGCTL_PSSE 0x00800000 |
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88 | #define EBIU_SDGCTL_PSM 0x00400000 |
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89 | #define EBIU_SDGCTL_PUPSD 0x00200000 |
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90 | #define EBIU_SDGCTL_TWR_MASK 0x00180000 |
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91 | #define EBIU_SDGCTL_TWR_SHIFT 19 |
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92 | #define EBIU_SDGCTL_TRCD_MASK 0x00038000 |
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93 | #define EBIU_SDGCTL_TRCD_SHIFT 15 |
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94 | #define EBIU_SDGCTL_TRP_MASK 0x00003800 |
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95 | #define EBIU_SDGCTL_TRP_SHIFT 11 |
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96 | #define EBIU_SDGCTL_TRAS_MASK 0x000003c0 |
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97 | #define EBIU_SDGCTL_TRAS_SHIFT 6 |
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98 | #define EBIU_SDGCTL_PASR_MASK 0x00000030 |
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99 | #define EBIU_SDGCTL_PASR_ALL 0x00000000 |
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100 | #define EBIU_SDGCTL_PASR_0_1 0x00000010 |
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101 | #define EBIU_SDGCTL_PASR_0 0x00000020 |
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102 | #define EBIU_SDGCTL_CL_MASK 0x0000000c |
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103 | #define EBIU_SDGCTL_CL_SHIFT 2 |
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104 | #define EBIU_SDGCTL_SCTLE 0x00000001 |
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105 | |
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106 | #define EBIU_SDBCTL_EBCAW_MASK 0x0030 |
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107 | #define EBIU_SDBCTL_SHIFT 4 |
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108 | #define EBIU_SDBCTL_EBCAW_8 0x0000 |
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109 | #define EBIU_SDBCTL_EBCAW_9 0x0010 |
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110 | #define EBIU_SDBCTL_EBCAW_10 0x0020 |
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111 | #define EBIU_SDBCTL_EBCAW_11 0x0030 |
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112 | #define EBIU_SDBCTL_EBSZ_MASK 0x000e |
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113 | #define EBIU_SDBCTL_EBSZ_SHIFT 1 |
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114 | #define EBIU_SDBCTL_EBSZ_16M 0x0000 |
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115 | #define EBIU_SDBCTL_EBSZ_32M 0x0002 |
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116 | #define EBIU_SDBCTL_EBSZ_64M 0x0004 |
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117 | #define EBIU_SDBCTL_EBSZ_128M 0x0006 |
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118 | #define EBIU_SDBCTL_EBSZ_256M 0x0008 |
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119 | #define EBIU_SDBCTL_EBSZ_512M 0x000a |
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120 | #define EBIU_SDBCTL_EBE 0x0001 |
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121 | |
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122 | #define EBIU_SDRRC_RDIV_MASK 0x0fff |
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123 | #define EBIU_SDRRC_RDIV_SHIFT 0 |
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124 | |
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125 | #define EBIU_SDSTAT_BGSTAT 0x0020 |
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126 | #define EBIU_SDSTAT_SDEASE 0x0010 |
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127 | #define EBIU_SDSTAT_SDRS 0x0008 |
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128 | #define EBIU_SDSTAT_SDPUA 0x0004 |
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129 | #define EBIU_SDSTAT_SDSRA 0x0002 |
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130 | #define EBIU_SDSTAT_SDCI 0x0001 |
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131 | |
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132 | |
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133 | #endif /* _ebiuRegs_h_ */ |
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134 | |
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