1 | /* Blackfin DMA Registers |
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2 | * |
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3 | * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA |
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4 | * written by Allan Hessenflow <allanh@kallisti.com> |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.com/license/LICENSE. |
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9 | * |
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10 | * $Id$ |
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11 | */ |
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12 | |
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13 | #ifndef _dmaRegs_h_ |
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14 | #define _dmaRegs_h_ |
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15 | |
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16 | |
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17 | /* register addresses */ |
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18 | |
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19 | #define DMA_NEXT_DESC_PTR_OFFSET 0x0000 |
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20 | #define DMA_START_ADDR_OFFSET 0x0004 |
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21 | #define DMA_CONFIG_OFFSET 0x0008 |
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22 | #define DMA_X_COUNT_OFFSET 0x0010 |
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23 | #define DMA_X_MODIFY_OFFSET 0x0014 |
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24 | #define DMA_Y_COUNT_OFFSET 0x0018 |
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25 | #define DMA_Y_MODIFY_OFFSET 0x001c |
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26 | #define DMA_CURR_DESC_PTR_OFFSET 0x0020 |
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27 | #define DMA_CURR_ADDR_OFFSET 0x0024 |
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28 | #define DMA_IRQ_STATUS_OFFSET 0x0028 |
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29 | #define DMA_PERIPHERAL_MAP_OFFSET 0x002c |
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30 | #define DMA_CURR_X_COUNT_OFFSET 0x0030 |
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31 | #define DMA_CURR_Y_COUNT_OFFSET 0x0038 |
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32 | |
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33 | #define HMDMA_CONTROL_OFFSET 0x0000 |
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34 | #define HMDMA_ECINIT_OFFSET 0x0004 |
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35 | #define HMDMA_BCINIT_OFFSET 0x0008 |
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36 | #define HMDMA_ECURGENT_OFFSET 0x000c |
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37 | #define HMDMA_ECOVERFLOW_OFFSET 0x0010 |
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38 | #define HMDMA_ECOUNT_OFFSET 0x0014 |
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39 | #define HMDMA_BCOUNT_OFFSET 0x0018 |
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40 | |
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41 | |
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42 | /* register fields */ |
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43 | |
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44 | #define DMA_CONFIG_FLOW_MASK 0x7000 |
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45 | #define DMA_CONFIG_FLOW_STOP 0x0000 |
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46 | #define DMA_CONFIG_FLOW_AUTOBUFFER 0x1000 |
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47 | #define DMA_CONFIG_FLOW_DESC_ARRAY 0x4000 |
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48 | #define DMA_CONFIG_FLOW_DESC_SMALL 0x6000 |
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49 | #define DMA_CONFIG_FLOW_DESC_LARGE 0x7000 |
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50 | #define DMA_CONFIG_NDSIZE_MASK 0x0f00 |
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51 | #define DMA_CONFIG_NDSIZE_SHIFT 8 |
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52 | #define DMA_CONFIG_DI_EN 0x0080 |
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53 | #define DMA_CONFIG_DI_SEL 0x0040 |
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54 | #define DMA_CONFIG_SYNC 0x0020 |
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55 | #define DMA_CONFIG_DMA2D 0x0010 |
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56 | #define DMA_CONFIG_WDSIZE_MASK 0x000c |
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57 | #define DMA_CONFIG_WDSIZE_8 0x0000 |
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58 | #define DMA_CONFIG_WDSIZE_16 0x0004 |
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59 | #define DMA_CONFIG_WDSIZE_32 0x0008 |
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60 | #define DMA_CONFIG_WNR 0x0002 |
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61 | #define DMA_CONFIG_DMAEN 0x0001 |
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62 | |
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63 | #define DMA_IRQ_STATUS_DMA_RUN 0x0008 |
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64 | #define DMA_IRQ_STATUS_DFETCH 0x0004 |
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65 | #define DMA_IRQ_STATUS_DMA_ERR 0x0002 |
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66 | #define DMA_IRQ_STATUS_DMA_DONE 0x0001 |
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67 | |
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68 | #define DMA_PERIPHERAL_MAP_PMAP_MASK 0xf000 |
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69 | #define DMA_PERIPHERAL_MAP_PMAP_PPI 0x0000 |
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70 | #define DMA_PERIPHERAL_MAP_PMAP_ETHRX 0x1000 |
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71 | #define DMA_PERIPHERAL_MAP_PMAP_ETHTX 0x2000 |
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72 | #define DMA_PERIPHERAL_MAP_PMAP_SPORT0RX 0x3000 |
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73 | #define DMA_PERIPHERAL_MAP_PMAP_SPORT0TX 0x4000 |
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74 | #define DMA_PERIPHERAL_MAP_PMAP_SPORT1RX 0x5000 |
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75 | #define DMA_PERIPHERAL_MAP_PMAP_SPORT1TX 0x6000 |
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76 | #define DMA_PERIPHERAL_MAP_PMAP_SPI 0x7000 |
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77 | #define DMA_PERIPHERAL_MAP_PMAP_UART0RX 0x8000 |
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78 | #define DMA_PERIPHERAL_MAP_PMAP_UART0TX 0x9000 |
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79 | #define DMA_PERIPHERAL_MAP_PMAP_UART1RX 0xa000 |
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80 | #define DMA_PERIPHERAL_MAP_PMAP_UART1TX 0xb000 |
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81 | #define DMA_PERIPHERAL_MAP_CTYPE 0x0040 |
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82 | |
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83 | #define HMDMA_CONTROL_BDI 0x8000 |
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84 | #define HMDMA_CONTROL_OI 0x4000 |
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85 | #define HMDMA_CONTROL_PS 0x2000 |
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86 | #define HMDMA_CONTROL_RBC 0x1000 |
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87 | #define HMDMA_CONTROL_DRQ_MASK 0x0300 |
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88 | #define HMDMA_CONTROL_DRQ_NONE 0x0000 |
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89 | #define HMDMA_CONTROL_DRQ_SINGLE 0x0100 |
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90 | #define HMDMA_CONTROL_DRQ_MULTIPLE 0x0200 |
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91 | #define HMDMA_CONTROL_DRQ_URGENT_MULTIPLE 0x0300 |
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92 | #define HMDMA_CONTROL_MBDI 0x0040 |
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93 | #define HMDMA_CONTROL_BDIE 0x0020 |
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94 | #define HMDMA_CONTROL_OIE 0x0010 |
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95 | #define HMDMA_CONTROL_UTE 0x0008 |
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96 | #define HMDMA_CONTROL_REP 0x0002 |
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97 | #define HMDMA_CONTROL_HMDMAEN 0x0001 |
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98 | |
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99 | #endif /* _dmaRegs_h_ */ |
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100 | |
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