| 1 | /* Blackfin BF537 Definitions |
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| 2 | * |
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| 3 | * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA |
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| 4 | * written by Allan Hessenflow <allanh@kallisti.com> |
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| 5 | * |
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| 6 | * The license and distribution terms for this file may be |
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| 7 | * found in the file LICENSE in this distribution or at |
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| 8 | * http://www.rtems.com/license/LICENSE. |
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| 9 | */ |
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| 10 | |
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| 11 | #ifndef _bf537_h_ |
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| 12 | #define _bf537_h_ |
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| 13 | |
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| 14 | /* register (or register block) addresses */ |
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| 15 | |
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| 16 | #define SIC_BASE_ADDRESS 0xffc00100 |
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| 17 | #define WDOG_BASE_ADDRESS 0xffc00200 |
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| 18 | #define RTC_BASE_ADDRESS 0xffc00300 |
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| 19 | #define UART0_BASE_ADDRESS 0xffc00400 |
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| 20 | #define SPI_BASE_ADDRESS 0xffc00500 |
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| 21 | #define TIMER_BASE_ADDRESS 0xffc00600 |
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| 22 | #define TIMER_CHANNELS 8 |
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| 23 | #define TIMER_PITCH 0x10 |
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| 24 | #define TIMER0_BASE_ADDRESS 0xffc00600 |
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| 25 | #define TIMER1_BASE_ADDRESS 0xffc00610 |
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| 26 | #define TIMER2_BASE_ADDRESS 0xffc00620 |
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| 27 | #define TIMER3_BASE_ADDRESS 0xffc00630 |
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| 28 | #define TIMER4_BASE_ADDRESS 0xffc00640 |
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| 29 | #define TIMER5_BASE_ADDRESS 0xffc00650 |
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| 30 | #define TIMER6_BASE_ADDRESS 0xffc00660 |
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| 31 | #define TIMER7_BASE_ADDRESS 0xffc00670 |
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| 32 | #define TIMER_ENABLE 0xffc00680 |
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| 33 | #define TIMER_DISABLE 0xffc00684 |
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| 34 | #define TIMER_STATUS 0xffc00688 |
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| 35 | #define PORTFIO_BASE_ADDRESS 0xffc00700 |
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| 36 | #define SPORT0_BASE_ADDRESS 0xffc00800 |
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| 37 | #define SPORT1_BASE_ADDRESS 0xffc00900 |
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| 38 | #define EBIU_BASE_ADDRESS 0xffc00a00 |
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| 39 | #define DMA_TC_PER 0xffc00b0c |
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| 40 | #define DMA_TC_CNT 0xffc00b10 |
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| 41 | #define DMA_BASE_ADDRESS 0xffc00c00 |
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| 42 | #define DMA_CHANNELS 12 |
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| 43 | #define DMA_PITCH 0x40 |
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| 44 | #define DMA0_BASE_ADDRESS 0xffc00c00 |
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| 45 | #define DMA1_BASE_ADDRESS 0xffc00c40 |
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| 46 | #define DMA2_BASE_ADDRESS 0xffc00c80 |
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| 47 | #define DMA3_BASE_ADDRESS 0xffc00cc0 |
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| 48 | #define DMA4_BASE_ADDRESS 0xffc00d00 |
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| 49 | #define DMA5_BASE_ADDRESS 0xffc00d40 |
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| 50 | #define DMA6_BASE_ADDRESS 0xffc00d80 |
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| 51 | #define DMA7_BASE_ADDRESS 0xffc00dc0 |
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| 52 | #define DMA8_BASE_ADDRESS 0xffc00e00 |
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| 53 | #define DMA9_BASE_ADDRESS 0xffc00e40 |
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| 54 | #define DMA10_BASE_ADDRESS 0xffc00e80 |
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| 55 | #define DMA11_BASE_ADDRESS 0xffc00ec0 |
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| 56 | #define MDMA_BASE_ADDRESS 0xffc00f00 |
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| 57 | #define MDMA_CHANNELS 2 |
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| 58 | #define MDMA_D_S 0x40 |
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| 59 | #define MDMA_PITCH 0x80 |
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| 60 | #define MDMA0D_BASE_ADDRESS 0xffc00f00 |
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| 61 | #define MDMA0S_BASE_ADDRESS 0xffc00f40 |
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| 62 | #define MDMA1D_BASE_ADDRESS 0xffc00f80 |
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| 63 | #define MDMA1S_BASE_ADDRESS 0xffc00fc0 |
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| 64 | #define PPI_BASE_ADDRESS 0xffc01000 |
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| 65 | #define TWI_BASE_ADDRESS 0xffc01400 |
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| 66 | #define PORTGIO_BASE_ADDRESS 0xffc01500 |
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| 67 | #define PORTHIO_BASE_ADDRESS 0xffc01700 |
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| 68 | #define UART1_BASE_ADDRESS 0xffc02000 |
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| 69 | #define CAN_BASE_ADDRESS 0xffc02a00 |
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| 70 | #define CAN_AM_BASE_ADDRESS 0xffc02b00 |
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| 71 | #define CAN_MB_BASE_ADDRESS 0xffc02c00 |
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| 72 | #define EMAC_BASE_ADDRESS 0xffc03000 |
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| 73 | #define PORTF_FER 0xffc03200 |
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| 74 | #define PORTG_FER 0xffc03204 |
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| 75 | #define PORTH_FER 0xffc03208 |
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| 76 | #define PORT_MUX 0xffc0320c |
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| 77 | #define HMDMA0_BASE_ADDRESS 0xffc03300 |
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| 78 | #define HMDMA1_BASE_ADDRESS 0xffc03340 |
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| 79 | |
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| 80 | |
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| 81 | /* register fields */ |
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| 82 | |
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| 83 | #define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK 0xf800 |
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| 84 | #define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT 11 |
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| 85 | #define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK 0x0700 |
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| 86 | #define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT 8 |
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| 87 | #define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK 0x00f0 |
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| 88 | #define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT 4 |
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| 89 | #define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK 0x000f |
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| 90 | #define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT 0 |
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| 91 | |
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| 92 | #define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK 0xf800 |
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| 93 | #define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT 11 |
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| 94 | #define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK 0x0700 |
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| 95 | #define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT 8 |
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| 96 | #define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK 0x00f0 |
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| 97 | #define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT 4 |
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| 98 | #define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK 0x000f |
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| 99 | #define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT 0 |
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| 100 | |
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| 101 | #define TIMER_ENABLE_TIMEN7 0x0080 |
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| 102 | #define TIMER_ENABLE_TIMEN6 0x0040 |
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| 103 | #define TIMER_ENABLE_TIMEN5 0x0020 |
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| 104 | #define TIMER_ENABLE_TIMEN4 0x0010 |
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| 105 | #define TIMER_ENABLE_TIMEN3 0x0008 |
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| 106 | #define TIMER_ENABLE_TIMEN2 0x0004 |
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| 107 | #define TIMER_ENABLE_TIMEN1 0x0002 |
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| 108 | #define TIMER_ENABLE_TIMEN0 0x0001 |
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| 109 | |
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| 110 | #define TIMER_DISABLE_TIMDIS7 0x0080 |
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| 111 | #define TIMER_DISABLE_TIMDIS6 0x0040 |
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| 112 | #define TIMER_DISABLE_TIMDIS5 0x0020 |
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| 113 | #define TIMER_DISABLE_TIMDIS4 0x0010 |
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| 114 | #define TIMER_DISABLE_TIMDIS3 0x0008 |
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| 115 | #define TIMER_DISABLE_TIMDIS2 0x0004 |
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| 116 | #define TIMER_DISABLE_TIMDIS1 0x0002 |
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| 117 | #define TIMER_DISABLE_TIMDIS0 0x0001 |
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| 118 | |
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| 119 | #define TIMER_STATUS_TRUN7 0x80000000 |
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| 120 | #define TIMER_STATUS_TRUN6 0x40000000 |
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| 121 | #define TIMER_STATUS_TRUN5 0x20000000 |
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| 122 | #define TIMER_STATUS_TRUN4 0x10000000 |
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| 123 | #define TIMER_STATUS_TOVF_ERR7 0x00800000 |
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| 124 | #define TIMER_STATUS_TOVF_ERR6 0x00400000 |
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| 125 | #define TIMER_STATUS_TOVF_ERR5 0x00200000 |
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| 126 | #define TIMER_STATUS_TOVF_ERR4 0x00100000 |
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| 127 | #define TIMER_STATUS_TIMIL7 0x00080000 |
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| 128 | #define TIMER_STATUS_TIMIL6 0x00040000 |
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| 129 | #define TIMER_STATUS_TIMIL5 0x00020000 |
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| 130 | #define TIMER_STATUS_TIMIL4 0x00010000 |
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| 131 | #define TIMER_STATUS_TRUN3 0x00008000 |
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| 132 | #define TIMER_STATUS_TRUN2 0x00004000 |
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| 133 | #define TIMER_STATUS_TRUN1 0x00002000 |
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| 134 | #define TIMER_STATUS_TRUN0 0x00001000 |
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| 135 | #define TIMER_STATUS_TOVF_ERR3 0x00000080 |
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| 136 | #define TIMER_STATUS_TOVF_ERR2 0x00000040 |
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| 137 | #define TIMER_STATUS_TOVF_ERR1 0x00000020 |
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| 138 | #define TIMER_STATUS_TOVF_ERR0 0x00000010 |
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| 139 | #define TIMER_STATUS_TIMIL3 0x00000008 |
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| 140 | #define TIMER_STATUS_TIMIL2 0x00000004 |
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| 141 | #define TIMER_STATUS_TIMIL1 0x00000002 |
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| 142 | #define TIMER_STATUS_TIMIL0 0x00000001 |
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| 143 | |
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| 144 | #define PORT_MUX_PGTE 0x0800 |
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| 145 | #define PORT_MUX_PGRE 0x0400 |
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| 146 | #define PORT_MUX_PGSE 0x0200 |
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| 147 | #define PORT_MUX_PFFE 0x0100 |
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| 148 | #define PORT_MUX_PFS4E 0x0080 |
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| 149 | #define PORT_MUX_PFS5E 0x0040 |
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| 150 | #define PORT_MUX_PFS6E 0x0020 |
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| 151 | #define PORT_MUX_PFTE 0x0010 |
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| 152 | #define PORT_MUX_PFDE 0x0008 |
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| 153 | #define PORT_MUX_PJCE_MASK 0x0006 |
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| 154 | #define PORT_MUX_PJCE_DR0SEC_DTOSEC 0x0000 |
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| 155 | #define PORT_MUX_PJCE_CANRX_CANTX 0x0002 |
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| 156 | #define PORT_MUX_PJCE_SPISSEL7 0x0004 |
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| 157 | #define PORT_MUX_PJSE 0x0001 |
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| 158 | |
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| 159 | |
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| 160 | /* Core Event Controller vectors */ |
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| 161 | |
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| 162 | #define CEC_EMULATION_VECTOR 0 |
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| 163 | #define CEC_RESET_VECTOR 1 |
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| 164 | #define CEC_NMI_VECTOR 2 |
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| 165 | #define CEC_EXCEPTIONS_VECTOR 3 |
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| 166 | #define CEC_HARDWARE_ERROR_VECTOR 5 |
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| 167 | #define CEC_CORE_TIMER_VECTOR 6 |
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| 168 | #define CEC_INTERRUPT_BASE_VECTOR 7 |
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| 169 | #define CEC_INTERRUPT_COUNT 9 |
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| 170 | |
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| 171 | |
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| 172 | /* System Interrupt Controller vectors */ |
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| 173 | |
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| 174 | #define SIC_IAR_COUNT 4 |
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| 175 | |
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| 176 | #define SIC_PLL_WAKEUP_VECTOR 0 |
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| 177 | #define SIC_DMA_ERROR_VECTOR 1 |
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| 178 | #define SIC_DMAR0_BLOCK_DONE_VECTOR 1 |
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| 179 | #define SIC_DMAR1_BLOCK_DONE_VECTOR 1 |
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| 180 | #define SIC_DMAR0_OVERFLOW_VECTOR 1 |
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| 181 | #define SIC_DMAR1_OVERFLOW_VECTOR 1 |
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| 182 | #define SIC_CAN_ERROR_VECTOR 2 |
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| 183 | #define SIC_MAC_ERROR_VECTOR 2 |
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| 184 | #define SIC_SPORT0_ERROR_VECTOR 2 |
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| 185 | #define SIC_SPORT1_ERROR_VECTOR 2 |
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| 186 | #define SIC_PPI_ERROR_VECTOR 2 |
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| 187 | #define SIC_SPI_ERROR_VECTOR 2 |
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| 188 | #define SIC_UART0_ERROR_VECTOR 2 |
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| 189 | #define SIC_UART1_ERROR_VECTOR 2 |
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| 190 | #define SIC_RTC_VECTOR 3 |
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| 191 | #define SIC_DMA0_PPI_VECTOR 4 |
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| 192 | #define SIC_DMA3_SPORT0_RX_VECTOR 5 |
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| 193 | #define SIC_DMA4_SPORT0_TX_VECTOR 6 |
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| 194 | #define SIC_DMA5_SPORT1_RX_VECTOR 7 |
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| 195 | #define SIC_DMA5_SPORT1_TX_VECTOR 8 |
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| 196 | #define SIC_TWI_VECTOR 9 |
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| 197 | #define SIC_DMA7_SPI_VECTOR 10 |
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| 198 | #define SIC_DMA8_UART0_RX_VECTOR 11 |
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| 199 | #define SIC_DMA9_UART0_TX_VECTOR 12 |
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| 200 | #define SIC_DMA10_UART1_RX_VECTOR 13 |
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| 201 | #define SIC_DMA11_UART1_TX_VECTOR 14 |
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| 202 | #define SIC_CAN_RX_VECTOR 15 |
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| 203 | #define SIC_CAN_TX_VECTOR 16 |
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| 204 | #define SIC_DMA1_MAC_RX_VECTOR 17 |
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| 205 | #define SIC_PORTH_IRQ_A_VECTOR 17 |
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| 206 | #define SIC_DMA2_MAC_TX_VECTOR 18 |
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| 207 | #define SIC_PORTH_IRQ_B_VECTOR 18 |
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| 208 | #define SIC_TIMER0_VECTOR 19 |
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| 209 | #define SIC_TIMER1_VECTOR 20 |
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| 210 | #define SIC_TIMER2_VECTOR 21 |
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| 211 | #define SIC_TIMER3_VECTOR 22 |
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| 212 | #define SIC_TIMER4_VECTOR 23 |
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| 213 | #define SIC_TIMER5_VECTOR 24 |
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| 214 | #define SIC_TIMER6_VECTOR 25 |
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| 215 | #define SIC_TIMER7_VECTOR 26 |
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| 216 | #define SIC_PORTF_IRQ_A_VECTOR 27 |
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| 217 | #define SIC_PORTG_IRQ_A_VECTOR 27 |
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| 218 | #define SIC_PORTG_IRQ_B_VECTOR 28 |
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| 219 | #define SIC_MDMA0_VECTOR 29 |
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| 220 | #define SIC_MDMA1_VECTOR 30 |
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| 221 | #define SIC_WATCHDOG_VECTOR 31 |
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| 222 | #define SIC_PORTF_IRQ_B_VECTOR 31 |
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| 223 | |
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| 224 | |
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| 225 | #endif /* _bf537_h_ */ |
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| 226 | |
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