source: rtems/c/src/lib/libcpu/bfin/cache/cache_.h @ 30abd24

4.104.114.95
Last change on this file since 30abd24 was 30abd24, checked in by Joel Sherrill <joel.sherrill@…>, on 08/15/08 at 20:18:41

2008-08-15 Allan Hessenflow <allanh@…>

  • ChangeLog?, Makefile.am, README, configure.ac, preinstall.am, cache/cache.c, cache/cache_.h, clock/clock.c, clock/rtc.c, clock/tod.h, include/bf533.h, include/bf537.h, include/cecRegs.h, include/coreTimerRegs.h, include/dmaRegs.h, include/ebiuRegs.h, include/ethernetRegs.h, include/gpioRegs.h, include/memoryRegs.h, include/mmuRegs.h, include/ppiRegs.h, include/rtcRegs.h, include/sicRegs.h, include/spiRegs.h, include/sportRegs.h, include/timerRegs.h, include/twiRegs.h, include/uartRegs.h, include/wdogRegs.h, interrupt/interrupt.c, interrupt/interrupt.h, mmu/mmu.c, mmu/mmu.h, network/ethernet.c, network/ethernet.h, serial/spi.c, serial/spi.h, serial/sport.c, serial/sport.h, serial/twi.c, serial/twi.h, serial/uart.c, serial/uart.h, timer/timer.c: New files.
  • Property mode set to 100644
File size: 403 bytes
Line 
1/*
2 *  Blackfin Cache Manager Support
3 *
4 *  $Id$
5 */
6
7#ifndef _cache__h_
8#define _cache__h_
9
10#define CPU_DATA_CACHE_ALIGNMENT          32
11#define CPU_INSTRUCTION_CACHE_ALIGNMENT   32
12
13#ifdef BSP_DATA_CACHE_CONFIG
14#define LIBCPU_DATA_CACHE_CONFIG BSP_DATA_CACHE_CONFIG
15#else
16/* use 16K of each SRAM bank */
17#define LIBCPU_DATA_CACHE_CONFIG (3 << DMEM_CONTROL_DMC_SHIFT)
18#endif
19
20#endif /* _cache__h_ */
21
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