1 | /* Blackfin Cache Support |
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2 | * |
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3 | * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA |
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4 | * written by Allan Hessenflow <allanh@kallisti.com> |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.com/license/LICENSE. |
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9 | * |
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10 | * $Id$ |
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11 | */ |
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12 | |
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13 | |
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14 | #include <rtems.h> |
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15 | #include <bsp.h> |
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16 | #include <libcpu/memoryRegs.h> |
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17 | #include "cache_.h" |
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18 | |
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19 | |
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20 | /* There are many syncs in the following code because they should be |
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21 | harmless except for wasting time, and this is easier than figuring out |
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22 | exactly where they're needed to protect from the effects of write |
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23 | buffers and queued reads. Many of them are likely unnecessary. */ |
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24 | |
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25 | |
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26 | void _CPU_cache_flush_1_data_line(const void *d_addr) { |
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27 | |
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28 | __asm__ __volatile__ ("ssync; flush [%0]; ssync" :: "a" (d_addr)); |
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29 | } |
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30 | |
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31 | /* Blackfins can't just invalidate cache; they can only do flush + |
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32 | invalidate. If the line isn't dirty then this is equivalent to |
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33 | just an invalidate. Even if it is dirty, this should still be |
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34 | okay since with a pure invalidate method the caller would have no |
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35 | way to insure the dirty line hadn't been written out anyway prior |
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36 | to the invalidate. */ |
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37 | void _CPU_cache_invalidate_1_data_line(const void *d_addr) { |
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38 | |
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39 | __asm__ __volatile__ ("ssync; flushinv [%0]; ssync" :: "a" (d_addr)); |
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40 | } |
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41 | |
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42 | void _CPU_cache_freeze_data(void) { |
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43 | } |
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44 | |
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45 | void _CPU_cache_unfreeze_data(void) { |
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46 | } |
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47 | |
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48 | void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) { |
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49 | |
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50 | __asm__ __volatile__ ("ssync; iflush [%0]; ssync" :: "a" (d_addr)); |
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51 | } |
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52 | |
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53 | void _CPU_cache_freeze_instruction(void) { |
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54 | } |
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55 | |
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56 | void _CPU_cache_unfreeze_instruction(void) { |
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57 | } |
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58 | |
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59 | /* incredibly inefficient... It would be better to make use of the |
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60 | DTEST_COMMAND/DTEST_DATAx registers to find the addresses in each |
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61 | cache line and flush just those. However the documentation I've |
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62 | seen on those is a bit sketchy, and I sure wouldn't want to get it |
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63 | wrong. */ |
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64 | void _CPU_cache_flush_entire_data(void) { |
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65 | uint32_t i; |
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66 | |
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67 | i = 0; |
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68 | __asm__ __volatile__ ("ssync"); |
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69 | do { |
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70 | __asm__ __volatile__ ("flush [%0]" :: "a" (i)); |
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71 | i += CPU_DATA_CACHE_ALIGNMENT; |
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72 | } while (i); |
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73 | __asm__ __volatile__ ("ssync"); |
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74 | } |
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75 | |
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76 | void _CPU_cache_invalidate_entire_data(void) { |
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77 | uint32_t dmemControl; |
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78 | |
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79 | __asm__ __volatile__ ("ssync"); |
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80 | dmemControl = *(uint32_t volatile *) DMEM_CONTROL; |
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81 | *(uint32_t volatile *) DMEM_CONTROL = dmemControl & ~DMEM_CONTROL_DMC_MASK; |
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82 | *(uint32_t volatile *) DMEM_CONTROL = dmemControl; |
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83 | __asm__ __volatile__ ("ssync"); |
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84 | } |
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85 | |
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86 | /* this does not actually enable data cache unless CPLBs are also enabled. |
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87 | LIBCPU_DATA_CACHE_CONFIG contains the DMEM_CONTROL_DMC bits to set. */ |
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88 | void _CPU_cache_enable_data(void) { |
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89 | |
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90 | __asm__ __volatile__ ("ssync"); |
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91 | *(uint32_t volatile *) DMEM_CONTROL |= LIBCPU_DATA_CACHE_CONFIG; |
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92 | __asm__ __volatile__ ("ssync"); |
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93 | } |
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94 | |
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95 | void _CPU_cache_disable_data(void) { |
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96 | |
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97 | __asm__ __volatile__ ("ssync"); |
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98 | *(uint32_t volatile *) DMEM_CONTROL &= ~DMEM_CONTROL_DMC_MASK; |
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99 | __asm__ __volatile__ ("ssync"); |
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100 | } |
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101 | |
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102 | void _CPU_cache_invalidate_entire_instruction(void) { |
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103 | uint32_t imemControl; |
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104 | |
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105 | __asm__ __volatile__ ("ssync"); |
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106 | imemControl = *(uint32_t volatile *) IMEM_CONTROL; |
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107 | *(uint32_t volatile *) IMEM_CONTROL = imemControl & ~IMEM_CONTROL_IMC; |
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108 | *(uint32_t volatile *) IMEM_CONTROL = imemControl; |
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109 | __asm__ __volatile__ ("ssync"); |
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110 | } |
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111 | |
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112 | /* this only actually enables the instruction cache if the CPLBs are also |
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113 | enabled. */ |
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114 | void _CPU_cache_enable_instruction(void) { |
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115 | |
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116 | __asm__ __volatile__ ("ssync"); |
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117 | *(uint32_t volatile *) IMEM_CONTROL |= IMEM_CONTROL_IMC; |
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118 | __asm__ __volatile__ ("ssync"); |
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119 | } |
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120 | |
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121 | void _CPU_cache_disable_instruction(void) { |
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122 | |
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123 | __asm__ __volatile__ ("ssync"); |
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124 | *(uint32_t volatile *) IMEM_CONTROL &= ~IMEM_CONTROL_IMC; |
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125 | __asm__ __volatile__ ("ssync"); |
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126 | } |
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127 | |
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