1 | /** |
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2 | *@file interrupt.h |
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3 | * |
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4 | *@brief |
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5 | * - This file implements interrupt dispatcher. The init code is taken from |
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6 | * the 533 implementation for blackfin. Since 52X supports 56 line and 2 ISR |
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7 | * registers some portion is written twice. |
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8 | * |
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9 | * Target: TLL6527v1-0 |
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10 | * Compiler: |
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11 | * |
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12 | * COPYRIGHT (c) 2010 by ECE Northeastern University. |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.com/license |
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17 | * |
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18 | * @author Rohan Kangralkar, ECE, Northeastern University |
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19 | * (kangralkar.r@husky.neu.edu) |
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20 | * |
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21 | * LastChange: |
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22 | * $Id$ |
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23 | * |
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24 | */ |
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25 | |
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26 | #ifndef _BFIN_INTERRUPT_H_ |
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27 | #define _BFIN_INTERRUPT_H_ |
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28 | |
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29 | |
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30 | #ifdef __cplusplus |
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31 | extern "C" { |
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32 | #endif |
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33 | |
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34 | /** The type of interrupts handled by the SIC |
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35 | */ |
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36 | typedef enum { |
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37 | IRQ_PLL_WAKEUP_INTERRUPT, /* 0 */ |
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38 | IRQ_DMA_ERROR_0, /* 1 */ |
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39 | IRQ_DMAR0_BLOCK_INTERRUPT, /* 2 */ |
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40 | IRQ_DMAR1_BLOCK_INTERRUPT, /* 3 */ |
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41 | IRQ_DMAR0_OVERFLOW_ERROR, /* 4 */ |
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42 | IRQ_DMAR1_OVERFLOW_ERROR, /* 5 */ |
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43 | IRQ_PPI_STATUS, /* 6 */ |
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44 | IRQ_MAC_STATUS, /* 7 */ |
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45 | IRQ_SPORT0_STATUS, /* 8 */ |
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46 | IRQ_SPORT1_STATUS, /* 9 */ |
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47 | IRQ_RESERVED_10, /* 10 */ |
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48 | IRQ_RESERVED_11, /* 11 */ |
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49 | IRQ_UART0_STATUS, /* 12 */ |
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50 | IRQ_UART1_STATUS, /* 13 */ |
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51 | IRQ_REAL_TIME_CLOCK, /* 14 */ |
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52 | IRQ_DMA0_PPI_NFC, /* 15 */ |
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53 | IRQ_DMA3_SPORT0_RX, /* 16 */ |
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54 | IRQ_DMA4_SPORT0_TX, /* 17 */ |
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55 | IRQ_DMA5_SPORT1_RX, /* 18 */ |
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56 | IRQ_DMA6_SPORT1_TX, /* 19 */ |
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57 | IRQ_TWI_INTERRUPT, /* 20 */ |
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58 | IRQ_DMA7_SPI, /* 21 */ |
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59 | IRQ_DMA8_UART0_RX, /* 22 */ |
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60 | IRQ_DMA9_UART0_TX, /* 23 */ |
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61 | IRQ_DMA10_UART1_RX, /* 24 */ |
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62 | IRQ_DMA11_UART1_TX, /* 25 */ |
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63 | IRQ_OTP, /* 26 */ |
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64 | IRQ_GP_COUNTER, /* 27 */ |
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65 | IRQ_DMA1_MAC_RX_HOSTDP, /* 28 */ |
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66 | IRQ_PORT_H_INTERRUPT_A, /* 29 */ |
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67 | IRQ_DMA2_MAC_TX_NFC, /* 30 */ |
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68 | IRQ_PORT_H_INTERRUPT_B, /* 31 */ |
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69 | SIC_ISR0_MAX, /* 32 ***/ |
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70 | IRQ_TIMER0 = SIC_ISR0_MAX, /* 32 */ |
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71 | IRQ_TIMER1, /* 33 */ |
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72 | IRQ_TIMER2, /* 34 */ |
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73 | IRQ_TIMER3, /* 35 */ |
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74 | IRQ_TIMER4, /* 36 */ |
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75 | IRQ_TIMER5, /* 37 */ |
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76 | IRQ_TIMER6, /* 38 */ |
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77 | IRQ_TIMER7, /* 39 */ |
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78 | IRQ_PORT_G_INTERRUPT_A, /* 40 */ |
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79 | IRQ_PORT_G_INTERRUPT_B, /* 41 */ |
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80 | IRQ_MDMA0_STREAM_0_INTERRUPT, /* 42 */ |
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81 | IRQ_MDMA1_STREAM_0_INTERRUPT, /* 43 */ |
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82 | IRQ_SOFTWARE_WATCHDOG_INTERRUPT, /* 44 */ |
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83 | IRQ_PORT_F_INTERRUPT_A, /* 45 */ |
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84 | IRQ_PORT_F_INTERRUPT_B, /* 46 */ |
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85 | IRQ_SPI_STATUS, /* 47 */ |
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86 | IRQ_NFC_STATUS, /* 48 */ |
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87 | IRQ_HOSTDP_STATUS, /* 49 */ |
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88 | IRQ_HOREAD_DONE_INTERRUPT, /* 50 */ |
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89 | IRQ_RESERVED_19, /* 51 */ |
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90 | IRQ_USB_INT0_INTERRUPT, /* 52 */ |
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91 | IRQ_USB_INT1_INTERRUPT, /* 53 */ |
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92 | IRQ_USB_INT2_INTERRUPT, /* 54 */ |
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93 | IRQ_USB_DMAINT, /* 55 */ |
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94 | IRQ_MAX, /* 56 */ |
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95 | } e_isr_t; |
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96 | |
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97 | |
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98 | |
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99 | |
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100 | /* source is the source to the SIC (the bit number in SIC_ISR). isr is |
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101 | the function that will be called when the interrupt is active. */ |
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102 | typedef struct bfin_isr_s { |
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103 | #if INTERRUPT_USE_TABLE |
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104 | e_isr_t source; |
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105 | void (*pFunc)(void *arg); |
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106 | void *pArg; |
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107 | int priority; /** not used */ |
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108 | #else |
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109 | int source; |
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110 | void (*isr)(void *arg); |
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111 | void *_arg; |
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112 | /* the following are for internal use only */ |
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113 | uint32_t mask0; |
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114 | uint32_t mask1; |
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115 | uint32_t vector; |
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116 | struct bfin_isr_s *next; |
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117 | #endif |
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118 | } bfin_isr_t; |
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119 | |
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120 | /** |
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121 | * This routine registers a new ISR. It will write a new entry to the IVT table |
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122 | * @param isr contains a callback function and source |
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123 | * @return rtems status code |
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124 | */ |
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125 | rtems_status_code bfin_interrupt_register(bfin_isr_t *isr); |
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126 | |
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127 | /** |
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128 | * This function unregisters a registered interrupt handler. |
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129 | * @param isr |
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130 | */ |
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131 | rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr); |
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132 | |
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133 | /** |
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134 | * blackfin interrupt initialization routine. It initializes the bfin ISR |
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135 | * dispatcher. It will also create SIC CEC map which will be used for |
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136 | * identifying the ISR. |
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137 | */ |
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138 | void bfin_interrupt_init(void); |
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139 | |
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140 | |
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141 | #ifdef __cplusplus |
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142 | } |
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143 | #endif |
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144 | |
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145 | #endif /* _BFIN_INTERRUPT_H_ */ |
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146 | |
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