source: rtems/c/src/lib/libcpu/arm/shared/include/cache_.h @ c499856

4.115
Last change on this file since c499856 was c499856, checked in by Chris Johns <chrisj@…>, on Mar 20, 2014 at 9:10:47 PM

Change all references of rtems.com to rtems.org.

  • Property mode set to 100644
File size: 2.9 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup arm
5 *
6 * @brief ARM cache defines and implementation.
7 */
8
9/*
10 * Copyright (c) 2009-2011 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef LIBCPU_ARM_CACHE__H
24#define LIBCPU_ARM_CACHE__H
25
26#ifdef __ARM_ARCH_5TEJ__
27  #include <libcpu/arm-cp15.h>
28
29  #define CPU_DATA_CACHE_ALIGNMENT 32
30  #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
31
32  static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
33  {
34    arm_cp15_data_cache_clean_line(d_addr);
35  }
36
37  static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
38  {
39    arm_cp15_data_cache_invalidate_line(d_addr);
40  }
41
42  static inline void _CPU_cache_freeze_data(void)
43  {
44    /* TODO */
45  }
46
47  static inline void _CPU_cache_unfreeze_data(void)
48  {
49    /* TODO */
50  }
51
52  static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
53  {
54    arm_cp15_instruction_cache_invalidate_line(d_addr);
55  }
56
57  static inline void _CPU_cache_freeze_instruction(void)
58  {
59    /* TODO */
60  }
61
62  static inline void _CPU_cache_unfreeze_instruction(void)
63  {
64    /* TODO */
65  }
66
67  static inline void _CPU_cache_flush_entire_data(void)
68  {
69    arm_cp15_data_cache_test_and_clean();
70  }
71
72  static inline void _CPU_cache_invalidate_entire_data(void)
73  {
74    arm_cp15_data_cache_invalidate();
75  }
76
77  static inline void _CPU_cache_enable_data(void)
78  {
79    rtems_interrupt_level level;
80    uint32_t ctrl;
81
82    rtems_interrupt_disable(level);
83    ctrl = arm_cp15_get_control();
84    ctrl |= ARM_CP15_CTRL_C;
85    arm_cp15_set_control(ctrl);
86    rtems_interrupt_enable(level);
87  }
88
89  static inline void _CPU_cache_disable_data(void)
90  {
91    rtems_interrupt_level level;
92    uint32_t ctrl;
93
94    rtems_interrupt_disable(level);
95    arm_cp15_data_cache_test_and_clean_and_invalidate();
96    ctrl = arm_cp15_get_control();
97    ctrl &= ~ARM_CP15_CTRL_C;
98    arm_cp15_set_control(ctrl);
99    rtems_interrupt_enable(level);
100  }
101
102  static inline void _CPU_cache_invalidate_entire_instruction(void)
103  {
104    arm_cp15_instruction_cache_invalidate();
105  }
106
107  static inline void _CPU_cache_enable_instruction(void)
108  {
109    rtems_interrupt_level level;
110    uint32_t ctrl;
111
112    rtems_interrupt_disable(level);
113    ctrl = arm_cp15_get_control();
114    ctrl |= ARM_CP15_CTRL_I;
115    arm_cp15_set_control(ctrl);
116    rtems_interrupt_enable(level);
117  }
118
119  static inline void _CPU_cache_disable_instruction(void)
120  {
121    rtems_interrupt_level level;
122    uint32_t ctrl;
123
124    rtems_interrupt_disable(level);
125    ctrl = arm_cp15_get_control();
126    ctrl &= ~ARM_CP15_CTRL_I;
127    arm_cp15_set_control(ctrl);
128    rtems_interrupt_enable(level);
129  }
130#endif
131
132#endif /* LIBCPU_ARM_CACHE__H */
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