[39c8fdb] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup arm |
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| 5 | * |
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[07f8af1] | 6 | * @brief ARM cache defines and implementation. |
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[39c8fdb] | 7 | */ |
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| 8 | |
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| 9 | /* |
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[07f8af1] | 10 | * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. |
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| 11 | * |
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| 12 | * embedded brains GmbH |
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| 13 | * Obere Lagerstr. 30 |
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| 14 | * 82178 Puchheim |
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| 15 | * Germany |
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| 16 | * <rtems@embedded-brains.de> |
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[39c8fdb] | 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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[c499856] | 20 | * http://www.rtems.org/license/LICENSE. |
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[39c8fdb] | 21 | */ |
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| 22 | |
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| 23 | #ifndef LIBCPU_ARM_CACHE__H |
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| 24 | #define LIBCPU_ARM_CACHE__H |
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| 25 | |
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[07f8af1] | 26 | #ifdef __ARM_ARCH_5TEJ__ |
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| 27 | #include <libcpu/arm-cp15.h> |
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| 28 | |
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| 29 | #define CPU_DATA_CACHE_ALIGNMENT 32 |
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| 30 | #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32 |
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| 31 | |
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| 32 | static inline void _CPU_cache_flush_1_data_line(const void *d_addr) |
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| 33 | { |
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| 34 | arm_cp15_data_cache_clean_line(d_addr); |
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| 35 | } |
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| 36 | |
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| 37 | static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr) |
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| 38 | { |
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| 39 | arm_cp15_data_cache_invalidate_line(d_addr); |
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| 40 | } |
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| 41 | |
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| 42 | static inline void _CPU_cache_freeze_data(void) |
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| 43 | { |
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| 44 | /* TODO */ |
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| 45 | } |
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| 46 | |
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| 47 | static inline void _CPU_cache_unfreeze_data(void) |
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| 48 | { |
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| 49 | /* TODO */ |
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| 50 | } |
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| 51 | |
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| 52 | static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) |
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| 53 | { |
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| 54 | arm_cp15_instruction_cache_invalidate_line(d_addr); |
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| 55 | } |
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| 56 | |
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| 57 | static inline void _CPU_cache_freeze_instruction(void) |
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| 58 | { |
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| 59 | /* TODO */ |
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| 60 | } |
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| 61 | |
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| 62 | static inline void _CPU_cache_unfreeze_instruction(void) |
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| 63 | { |
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| 64 | /* TODO */ |
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| 65 | } |
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| 66 | |
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| 67 | static inline void _CPU_cache_flush_entire_data(void) |
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| 68 | { |
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| 69 | arm_cp15_data_cache_test_and_clean(); |
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| 70 | } |
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| 71 | |
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| 72 | static inline void _CPU_cache_invalidate_entire_data(void) |
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| 73 | { |
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| 74 | arm_cp15_data_cache_invalidate(); |
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| 75 | } |
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| 76 | |
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| 77 | static inline void _CPU_cache_enable_data(void) |
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| 78 | { |
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| 79 | rtems_interrupt_level level; |
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| 80 | uint32_t ctrl; |
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| 81 | |
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| 82 | rtems_interrupt_disable(level); |
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| 83 | ctrl = arm_cp15_get_control(); |
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| 84 | ctrl |= ARM_CP15_CTRL_C; |
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| 85 | arm_cp15_set_control(ctrl); |
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| 86 | rtems_interrupt_enable(level); |
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| 87 | } |
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| 88 | |
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| 89 | static inline void _CPU_cache_disable_data(void) |
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| 90 | { |
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| 91 | rtems_interrupt_level level; |
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| 92 | uint32_t ctrl; |
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| 93 | |
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| 94 | rtems_interrupt_disable(level); |
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| 95 | arm_cp15_data_cache_test_and_clean_and_invalidate(); |
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| 96 | ctrl = arm_cp15_get_control(); |
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| 97 | ctrl &= ~ARM_CP15_CTRL_C; |
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| 98 | arm_cp15_set_control(ctrl); |
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| 99 | rtems_interrupt_enable(level); |
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| 100 | } |
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| 101 | |
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| 102 | static inline void _CPU_cache_invalidate_entire_instruction(void) |
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| 103 | { |
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| 104 | arm_cp15_instruction_cache_invalidate(); |
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| 105 | } |
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| 106 | |
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| 107 | static inline void _CPU_cache_enable_instruction(void) |
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| 108 | { |
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| 109 | rtems_interrupt_level level; |
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| 110 | uint32_t ctrl; |
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| 111 | |
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| 112 | rtems_interrupt_disable(level); |
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| 113 | ctrl = arm_cp15_get_control(); |
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| 114 | ctrl |= ARM_CP15_CTRL_I; |
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| 115 | arm_cp15_set_control(ctrl); |
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| 116 | rtems_interrupt_enable(level); |
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| 117 | } |
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| 118 | |
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| 119 | static inline void _CPU_cache_disable_instruction(void) |
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| 120 | { |
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| 121 | rtems_interrupt_level level; |
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| 122 | uint32_t ctrl; |
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| 123 | |
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| 124 | rtems_interrupt_disable(level); |
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| 125 | ctrl = arm_cp15_get_control(); |
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| 126 | ctrl &= ~ARM_CP15_CTRL_I; |
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| 127 | arm_cp15_set_control(ctrl); |
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| 128 | rtems_interrupt_enable(level); |
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| 129 | } |
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| 130 | #endif |
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[39c8fdb] | 131 | |
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| 132 | #endif /* LIBCPU_ARM_CACHE__H */ |
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